Patents by Inventor Yoshihiko Kamata
Yoshihiko Kamata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190348120Abstract: A semiconductor memory device comprises a first memory cell array including a first memory cell and a second memory cell array including a second memory cell, a first transistor electrically connectable to a first end of the first memory cell via a first source line, a second transistor connectable to a first end of the second memory cell via a second source line, a pad supplied with a reference voltage from outside, a first wiring that electrically connects the first transistor and the pad, and a second wiring that is different from the first wiring and electrically connects the second transistor and the pad.Type: ApplicationFiled: September 2, 2018Publication date: November 14, 2019Inventors: Yuki SHIMIZU, Yoshihiko KAMATA, Tsukasa KOBAYASHI, Hideyuki KATAOKA, Koji KATO, Takumi FUJIMOTO, Yoshinao SUZUKI, Yuui SHIMIZU
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Publication number: 20190244671Abstract: A semiconductor memory device includes a memory cell, a bit line connected to the memory cell, a sense amplifier connected to the memory cell through the bit line, and a control circuit. The sense amplifier includes a sense node connected to the bit line, a first capacitive element connected to the sense node and a sense transistor having a gate connected to the sense node. The control circuit is configured to adjust a voltage applied to a back gate of the sense transistor or a source of the sense transistor to correct a variation of a threshold voltage of the sense transistor.Type: ApplicationFiled: April 17, 2019Publication date: August 8, 2019Inventors: Yoshihiko KAMATA, Yoko DEGUCHI, Takuyo KODAMA, Tsukasa KOBAYASHI, Mario SAKO, Kosuke YANAGIDAIRA
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Publication number: 20190189213Abstract: A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.Type: ApplicationFiled: February 22, 2019Publication date: June 20, 2019Inventors: Mai SHIMIZU, Koji KATO, Yoshihiko KAMATA, Mario SAKO
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Patent number: 10297326Abstract: A semiconductor memory device includes a memory cell, a bit line connected to the memory cell, and a sense amplifier connected to the memory cell through the bit line. The sense amplifier includes a sense node connected to the bit line, a first capacitive element connected to the sense node, and a static latch circuit connected to the sense node and retains data of the sense node.Type: GrantFiled: January 20, 2017Date of Patent: May 21, 2019Assignee: Toshiba Memory CorporationInventors: Yoshihiko Kamata, Yoko Deguchi, Takuyo Kodama, Tsukasa Kobayashi, Mario Sako, Kosuke Yanagidaira
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Publication number: 20190122740Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells, a first word line, first and second sense amplifiers, first and second bit lines, a controller. The first and second sense amplifiers each include first and second transistors. The first bit line is connected between the first memory cell and the first transistor. The second bit line is connected between the second memory cell and the second transistor. In the read operation, the controller is configured to apply a kick voltage to the first word line before applying the read voltage to the first word line, and to apply a first voltage to a gate of the first transistor and a second voltage to a gate of the second transistor while applying the kick voltage to the first word line.Type: ApplicationFiled: December 14, 2018Publication date: April 25, 2019Applicant: Toshiba Memory CorporationInventors: Yoshihiko KAMATA, Naofumi Abiko
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Patent number: 10255977Abstract: A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.Type: GrantFiled: September 5, 2017Date of Patent: April 9, 2019Assignee: Toshiba Memory CorporationInventors: Mai Shimizu, Koji Kato, Yoshihiko Kamata, Mario Sako
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Patent number: 10210924Abstract: A semiconductor memory device includes a memory cell transistor, a bit line, a sense amplifier circuit, a voltage generation circuit, and a control unit. The bit line is electrically connected to a terminal of the memory cell transistor. The sense amplifier circuit includes a first transistor having a gate electrically connected to the bit line and a second transistor connected in series to a first terminal of the first transistor. The control unit controls the voltage generation circuit to apply a first voltage to the second terminal of the first transistor during a first sense period and a second voltage to the second terminal of the first transistor during a second sense period. The first voltage is equal to or higher than 0 V and the second voltage is higher than 0 V, and the first and second voltages have voltage levels different from each other.Type: GrantFiled: August 29, 2017Date of Patent: February 19, 2019Assignee: Toshiba Memory CorporationInventor: Yoshihiko Kamata
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Patent number: 10204692Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells, a first word line, first and second sense amplifiers, first and second bit lines, a controller. The first and second sense amplifiers each include first and second transistors. The first bit line is connected between the first memory cell and the first transistor. The second bit line is connected between the second memory cell and the second transistor. In the read operation, the controller is configured to apply a kick voltage to the first word line before applying the read voltage to the first word line, and to apply a first voltage to a gate of the first transistor and a second voltage to a gate of the second transistor while applying the kick voltage to the first word line.Type: GrantFiled: February 1, 2018Date of Patent: February 12, 2019Assignee: Toshiba Memory CorporationInventors: Yoshihiko Kamata, Naofumi Abiko
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Publication number: 20180277218Abstract: A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.Type: ApplicationFiled: September 5, 2017Publication date: September 27, 2018Inventors: Mai SHIMIZU, Koji KATO, Yoshihiko KAMATA, Mario SAKO
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Publication number: 20180211700Abstract: A semiconductor memory device includes a memory cell transistor, a bit line, a sense amplifier circuit, a voltage generation circuit, and a control unit. The bit line is electrically connected to a terminal of the memory cell transistor. The sense amplifier circuit includes a first transistor having a gate electrically connected to the bit line and a second transistor connected in series to a first terminal of the first transistor. The control unit controls the voltage generation circuit to apply a first voltage to the second terminal of the first transistor during a first sense period and a second voltage to the second terminal of the first transistor during a second sense period. The first voltage is equal to or higher than 0 V and the second voltage is higher than 0 V, and the first and second voltages have voltage levels different from each other.Type: ApplicationFiled: August 29, 2017Publication date: July 26, 2018Inventor: Yoshihiko KAMATA
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Patent number: 10014064Abstract: According to one embodiment, a semiconductor storage device includes a memory cell array having memory cell capable of holding N-bit data; and a sense amplifier comprising a first latch holding information on a threshold distribution, a second latch holding write data, and a third latch holding lower information of the N-bit data, and supplying a first to a fourth voltages to the memory cell to write the data to the memory cell using the first to fourth voltages. The sense amplifier supplies the first to third voltages to the memory cell based on information in the second and the third latches, and based on a result of transfer of the information held by the first latch to the second latch, supplies the fourth voltage or the first voltage to the memory cell.Type: GrantFiled: March 10, 2017Date of Patent: July 3, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yoshihiko Kamata, Koji Tabata
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Publication number: 20170365348Abstract: A semiconductor memory device includes a memory cell, a bit line connected to the memory cell, and a sense amplifier connected to the memory cell through the bit line. The sense amplifier includes a sense node connected to the bit line, a first capacitive element connected to the sense node, and a static latch circuit connected to the sense node and retains data of the sense node.Type: ApplicationFiled: January 20, 2017Publication date: December 21, 2017Inventors: Yoshihiko KAMATA, Yoko DEGUCHI, Takuyo KODAMA, Tsukasa KOBAYASHI, Mario SAKO, Kosuke YANAGIDAIRA
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Publication number: 20170263325Abstract: According to one embodiment, a semiconductor memory device includes a first transistor which includes a first end coupled to a first node, a second end, and a gate coupled to the second end. A second transistor includes a third end coupled to the first node, a fourth end, and a gate coupled to the fourth end. A third transistor is provided between a first bit line and a second node in a first sense amplifier. A selector is configured to supply a gate of the third transistor with one of a potential of the second end and a potential of the fourth end.Type: ApplicationFiled: September 9, 2016Publication date: September 14, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yoshihiko KAMATA, Mario SAKO, Naofumi ABIKO, Toshifumi WATANABE
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Publication number: 20170186492Abstract: According to one embodiment, a semiconductor storage device includes a memory cell array having memory cell capable of holding N-bit data; and a sense amplifier comprising a first latch holding information on a threshold distribution, a second latch holding write data, and a third latch holding lower information of the N-bit data, and supplying a first to a fourth voltages to the memory cell to write the data to the memory cell using the first to fourth voltages. The sense amplifier supplies the first to third voltages to the memory cell based on information in the second and the third latches, and based on a result of transfer of the information held by the first latch to the second latch, supplies the fourth voltage or the first voltage to the memory cell.Type: ApplicationFiled: March 10, 2017Publication date: June 29, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yoshihiko KAMATA, Koji TABATA
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Publication number: 20160343441Abstract: According to one embodiment, a semiconductor device includes: a first semiconductor chip including a first via and a second via; and a second semiconductor chip including a third via and a fourth via and being located above the first semiconductor chip. The first semiconductor chip includes: a first detector capable of coupling to the third via through the second and fourth vias; and a first current source configured to control an output current in accordance with a voltage of the third via detected by the first detector.Type: ApplicationFiled: August 31, 2015Publication date: November 24, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Naofumi ABIKO, Masahiro YOSHIHARA, Yoshihiko KAMATA
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Patent number: 9496042Abstract: According to one embodiment, a semiconductor device includes: a first semiconductor chip including a first via and a second via; and a second semiconductor chip including a third via and a fourth via and being located above the first semiconductor chip. The first semiconductor chip includes: a first detector capable of coupling to the third via through the second and fourth vias; and a first current source configured to control an output current in accordance with a voltage of the third via detected by the first detector.Type: GrantFiled: August 31, 2015Date of Patent: November 15, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Naofumi Abiko, Masahiro Yoshihara, Yoshihiko Kamata
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Patent number: 9236135Abstract: According to one embodiment, a nonvolatile semiconductor storage device includes a memory cell, a voltage generator configured to output a first voltage and a second voltage, and a controller. The controller executes a write operation, which includes a first read operation, a program operation, and a verify operation. The controller executes the first read operation before the program operation and the verify operation. The controller executes the first read operation by applying the first voltage to a gate of the memory cell. The controller executes an erase verify operation by applying the second voltage to the gate of the memory cell. The first voltage is higher than the second voltage.Type: GrantFiled: September 11, 2014Date of Patent: January 12, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Yoshihiko Kamata, Yuko Yokota
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Patent number: 9171631Abstract: According to one embodiment, a semiconductor memory device includes a first transistor, a detector, and a second transistor. The first transistor is capable of transferring a first voltage to a bit line. The detector reads data held by a memory cell connected to the bit line. The second transistor is capable of transferring a second voltage and a third voltage to the detector. The second voltage is generated by a source different from a source of the first voltage. The third voltage is larger than the second voltage. The second transistor charges the detector to one of the second voltage and the third voltage, while the first transistor transferring the first voltage to the bit line.Type: GrantFiled: March 15, 2013Date of Patent: October 27, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Yoshihiko Kamata, Yuko Yokota, Koji Tabata, Tomoyuki Hamano, Mario Sako
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Patent number: 9147481Abstract: According to one embodiment, a semiconductor memory apparatus includes an array, a source, a bit line, a sense, and current circuit. The array includes a NAND string. The NAND string includes memory cell. The sense includes a first transistor. One end of transistor is connected to a first node, and other end of the transistor is connected to a second. The first node is used for reading the data held by the memory cell. An internal voltage is smaller than the source voltage. The current circuit outputs a first voltage to a gate of the transistor, and the first voltage is smaller than the internal voltage. The transistor limits a first current from the source to the sense based on a threshold voltage of the memory cell to be read.Type: GrantFiled: March 15, 2013Date of Patent: September 29, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventor: Yoshihiko Kamata
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Publication number: 20150262691Abstract: According to one embodiment, a nonvolatile semiconductor storage device includes a memory cell, a voltage generator configured to output a first voltage and a second voltage, and a controller. The controller executes a write operation, which includes a first read operation, a program operation, and a verify operation. The controller executes the first read operation before the program operation and the verify operation. The controller executes the first read operation by applying the first voltage to a gate of the memory cell. The controller executes an erase verify operation by applying the second voltage to the gate of the memory cell. The first voltage is higher than the second voltage.Type: ApplicationFiled: September 11, 2014Publication date: September 17, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yoshihiko KAMATA, Yuko YOKOTA