Abstract: A voltage generating circuit for outputting a voltage from an output terminal, has a first voltage dividing circuit which is connected between the output terminal and ground; a switch circuit connected between the output terminal and the first voltage dividing circuit; a first voltage detecting circuit which outputs a first pumping signal corresponding to a comparison result; a second voltage dividing circuit which is connected between the output terminal and the ground; a second voltage detecting circuit which outputs a second pumping signal corresponding to a comparison result; a pump circuit that outputs a voltage boosted from a power supply voltage; and a boost circuit which has a capacitive element having one end connected to the voltage dividing resistor of the first voltage dividing circuit.

Abstract: A semiconductor memory device includes first and second memory cells and a sense amplifier. The first memory cell includes a MOS transistor and is capable of retaining n-bit (n is a natural number more than one) first data. The MOS transistor includes a charge accumulation layer and a control gate. The second memory cell retains second data. The second data is a criterion for the first data. The sense amplifier determines the first data read out from the first memory cell and amplifies the first data using a first reference level and a second reference level. The first reference level is obtained based on the second data read out from the second memory cell. The second reference level is generated inside based on the first reference level.

Abstract: A semiconductor storage device comprises a memory cell array having memory cells arranged in a matrix, each memory cell mainly composed of a flip-flop formed of a pair of cross-coupled inverters, a first wiring configured to each row and each column of the memory cell array and connected to a predetermined power supply node, a second wiring configured in parallel to the first wiring, and a switching circuit that is connected between the power supply node and the second wiring and opens when initial data is set to the memory cells, wherein a receiving node of each pair of inverters is selectively connected to the first wiring or the second wiring in accordance with a logical value of initial data to be set to each one of the plurality of the memory cells belonging to each row and each column of the memory cell array.

Abstract: A nonvolatile semiconductor memory device includes a first memory cell having a conductive/nonconductive state thereof substantially controlled in response to data stored therein and providing passage of a first current amount in the conductive state, a first bit line connected to the first memory cell, a reference cell connected to the first bit line and providing passage of a second current amount smaller than the first current amount, a second bit line, a second memory cell connected to the second bit line and providing passage of the first current amount, and a sense amplifier connectable to the first bit line and the second bit line through electrical couplings.

Abstract: A semiconductor memory device includes memory cells, redundant cells, a redundancy repair control circuit and a test mode control circuit. Each of the memory cells is assigned a unique address to be accessed by a corresponding address. The redundant cells are replaceable with the memory cells. The redundancy repair control circuit replaces predetermined memory cells among the memory cells with the redundant cells. The test mode control circuit invalidates an operation of the redundancy repair control circuit and assigns an additional unique address to the redundant cells so that all of the memory cells and the redundant cells are accessible during a test mode.

Abstract: A nonvolatile semiconductor memory device includes a first memory cell having a conductive/nonconductive state thereof substantially controlled in response to data stored therein and providing passage of a first current amount in the conductive state, a first bit line connected to the first memory cell, a reference cell connected to the first bit line and providing passage of a second current amount smaller than the first current amount, a second bit line, a second memory cell connected to the second bit line and providing passage of the first current amount, and a sense amplifier connectable to the first bit line and the second bit line through electrical couplings.

Abstract: A POR circuit includes a signal generator which has a PMOS transistor and a first and second resistors connected in series. The PMOS transistor is controlled in accordance with a DPWD signal. A first signal obtained by dividing a voltage difference between the ground voltage and the supply voltage is output from a first node between the first and second resistors. The POR circuit also includes an edge generator which includes a third resistor and an NMOS transistor connected in series, and an inverter coupled to a second node between the third resistor and the NMOS transistor. The NMOS transistor is controlled in accordance with a voltage of the first signal output from the first node. When the NMOS transistor turns on, a second signal having an edge waveform is generated at the second node, the first inverter outputs a third signal which is a reversal of the second signal.

Abstract: A semiconductor memory device includes memory cells, redundant cells, a redundancy repair control circuit and a test mode control circuit. Each of the memory cells is assigned a unique address to be accessed by a corresponding address. The redundant cells are replaceable with the memory cells. The redundancy repair control circuit replaces predetermined memory cells among the memory cells with the redundant cells. The test mode control circuit invalidates an operation of the redundancy repair control circuit and assigns an additional unique address to the redundant cells so that all of the memory cells and the redundant cells are accessible during a test mode.

Abstract: A POR circuit includes a signal generator which has a PMOS transistor and a first and second resistors connected in series. The PMOS transistor is controlled in accordance with a DPWD signal. A first signal obtained by dividing a voltage difference between the ground voltage and the supply voltage is output from a first node between the first and second resistors. The POR circuit also includes an edge generator which includes a third resistor and an NMOS transistor connected in series, and an inverter coupled to a second node between the third resistor and the NMOS transistor. The NMOS transistor is controlled in accordance with a voltage of the first signal output from the first node. When the NMOS transistor turns on, a second signal having an edge waveform is generated at the second node, the first inverter outputs a third signal which is a reversal of the second signal.

Abstract: A voltage translator enabling a high speed non-selection switching with regard to the word line voltage. The voltage translator (10) includes one inverter (made up of transistors N1 and P1) arranged on the output side of the voltage transistor circuit, a feedback PMOS type transistor (P2), an NMOS type transistor (N4) having a earth terminal and controlled by the output signal from the other inverter newly added on the input side of the voltage translator circuit, an NMOS type transistor (N3) controlled by the word line, and a PMOS type transistor (P3) controlled by a signal given through an NOMS transistor (N2) connected with the output of the above newly added inverter located on the input side of the voltage translator circuit.

Abstract: A voltage translator enabling a high speed non-selection switching with regard to the word line voltage. The voltage translator (10) includes one inverter (made up of transistors N1 and P1) arranged on the output side of the voltage transistor circuit, a feedback PMOS type transistor (P2), an NMOS type transistor (N4) having a earth terminal and controlled by the output signal from the other inverter newly added on the input side of the voltage translator circuit, an NMOS type transistor (N3) controlled by the word line, and a PMOS type transistor (P3) controlled by a signal given through an NOMS transistor (N2) connected with the output of the above newly added inverter located on the input side of the voltage translator circuit.