Patents by Inventor Yoshihiko Kanzawa
Yoshihiko Kanzawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8338816Abstract: A nonvolatile memory element of the present invention comprises a first electrode (503); a second electrode (505); and a resistance variable layer (504) which is disposed between the first electrode (503) and the second electrode (505), a resistance value of the resistance variable layer being changeable in response to electric signals which are applied between the first electrode (503) and the second electrode (505), wherein the first electrode and the second electrode comprise materials which are made of different elements.Type: GrantFiled: March 31, 2008Date of Patent: December 25, 2012Assignee: Panasonic CorporationInventors: Yoshihiko Kanzawa, Shunsaku Muraoka, Satoru Mitani, Zhiqiang Wei, Takeshi Takagi
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Patent number: 8320159Abstract: Each of memory cells (MC) includes one transistor and one resistance variable element. The transistor includes a first main terminal, a second main terminal and a control terminal. The resistance variable element includes a first electrode, a second electrode and a resistance variable layer provided between the first electrode and the second electrode. A first main terminal of one of two adjacent memory cells is connected to a second main terminal of the other memory cell, to form a series path (SP) sequentially connecting main terminals of the plurality of memory cells in series.Type: GrantFiled: March 15, 2010Date of Patent: November 27, 2012Assignee: Panasonic CorporationInventors: Zhiqiang Wei, Ryotaro Azuma, Takeshi Takagi, Mitsuteru Iijima, Yoshihiko Kanzawa
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Patent number: 8309946Abstract: A resistance variable element of the present invention comprises a first electrode (103), a second electrode (107), and a resistance variable layer which is interposed between the first electrode (103) and the second electrode (107) to contact the first electrode (103) and the second electrode (107), the resistance variable layer being configured to change in response to electric signals with different polarities which are applied between the first electrode (103) and the second electrode (107), the resistance variable layer comprising an oxygen-deficient transition metal oxide layer, and the second electrode (107) comprising platinum having minute hillocks (108).Type: GrantFiled: July 22, 2009Date of Patent: November 13, 2012Assignee: Panasonic CorporationInventors: Satoru Mitani, Shunsaku Muraoka, Yoshihiko Kanzawa, Koji Katayama, Ryoko Miyanaga, Satoru Fujii, Takeshi Takagi
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Publication number: 20120281453Abstract: The variable resistance nonvolatile storage device includes a memory cell (300) that is formed by connecting in series a variable resistance element (309) including a variable resistance layer (309b) which reversibly changes based on electrical signals each having a different polarity and a transistor (317) including a semiconductor substrate (301) and two N-type diffusion layer regions (302a, 302b), wherein the variable resistance layer (309b) includes an oxygen-deficient oxide of a transition metal, lower and upper electrodes (309a, 309c) are made of materials of different elements, a standard electrode potential V1 of the lower electrode (309a), a standard electrode potential V2 of the upper electrode (309c), and a standard electrode potential Vt of the transition metal satisfy Vt<V2 and V1<V2, and the lower electrode (309a) is connected with the N-type diffusion layer region (302b), the electrical signals being applied between the lower and upper electrodes (309a, 309c).Type: ApplicationFiled: June 27, 2012Publication date: November 8, 2012Inventors: Kazuhiko SHIMAKAWA, Yoshihiko KANZAWA, Satoru MITANI, Shunsaku MURAOKA
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Patent number: 8279657Abstract: Provided is a nonvolatile memory element which is capable of performing a stable resistance change operation at a low breakdown voltage. A nonvolatile memory element (100) includes: a first electrode layer (103); a second electrode layer (105); and a variable resistance layer (104) which is placed between the electrodes (103 and 105), and whose resistance state reversibly changes between a high resistance state and a low resistance state based on a polarity of a voltage applied between the electrodes (103 and 105). The variable resistance layer (104) is formed by stacking a first oxide layer (104a) including an oxide of a first transition metal and a second oxide layer (104b) including an oxide of a second transition metal which is different from the first transition metal.Type: GrantFiled: December 4, 2009Date of Patent: October 2, 2012Assignee: Panasonic CorporationInventors: Takeshi Takagi, Zhiqiang Wei, Takeki Ninomiya, Shunsaku Muraoka, Yoshihiko Kanzawa
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Patent number: 8264865Abstract: A nonvolatile memory element of the present invention comprises a first electrode (103), a second electrode (108); a resistance variable layer (107) which is interposed between the first electrode (103) and the second electrode (107) and is configured to switch a resistance value reversibly in response to an electric signal applied between the electrodes (103) and (108), and the resistance variable layer (107) has at least a multi-layer structure in which a first hafnium-containing layer having a composition expressed as HfOx (0.9?x?1.6), and a second hafnium-containing layer having a composition expressed as HfOy (1.8<y<2.0) are stacked together.Type: GrantFiled: July 1, 2009Date of Patent: September 11, 2012Assignee: Panasonic CorporationInventors: Satoru Mitani, Yoshihiko Kanzawa, Koji Katayama, Takeshi Takagi
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Patent number: 8233311Abstract: The variable resistance nonvolatile storage device includes a memory cell (300) that is formed by connecting in series a variable resistance element (309) including a variable resistance layer (309b) which reversibly changes based on electrical signals each having a different polarity and a transistor (317) including a semiconductor substrate (301) and two N-type diffusion layer regions (302a, 302b), wherein the variable resistance layer (309b) includes an oxygen-deficient oxide of a transition metal, lower and upper electrodes (309a, 309c) are made of materials of different elements, a standard electrode potential V1 of the lower electrode (309a), a standard electrode potential V2 of the upper electrode (309c), and a standard electrode potential Vt of the transition metal satisfy Vt<V2 and V1<V2, and the lower electrode (309a) is connected with the N-type diffusion layer region (302b), the electrical signals being applied between the lower and upper electrodes (309a, 309c).Type: GrantFiled: December 5, 2011Date of Patent: July 31, 2012Assignee: Panasonic CorporationInventors: Kazuhiko Shimakawa, Yoshihiko Kanzawa, Satoru Mitani, Shunsaku Muraoka
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Patent number: 8179713Abstract: A nonvolatile memory element comprises a first electrode (103), a second electrode (105), and a resistance variable layer (104) which is provided between the first electrode and the second electrode, and is configured to reversibly switch an interelectrode resistance value which is a resistance value between the first electrode and the second electrode, in response to an interelectrode voltage which is an electric potential of the second electrode on the basis of the first electrode, the resistance variable layer includes an oxygen-deficient transition metal oxide, the first electrode side and the second electrode side have an asymmetric structure, a portion of the resistance variable layer which is located at the first electrode side and a portion of the resistance variable layer which is located at the second electrode side are each configured to be selectively placed into one of a low-resistance state and a high-resistance state, so as to attain a stable state in three or more different interelectrode resiType: GrantFiled: May 18, 2009Date of Patent: May 15, 2012Assignee: Panasonic CorporationInventors: Yoshihiko Kanzawa, Satoru Mitani, Zhiqiang Wei, Takeshi Takagi
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Patent number: 8148711Abstract: A nonvolatile semiconductor apparatus of the present invention comprises (103), a second electrode (105), and a resistance variable layer (104) disposed between the first electrode (103) and the second electrode (105), a resistance value of the resistance variable layer being switchable reversibly in response to an electric signal applied between the electrodes (103), (105), wherein the resistance variable layer (104) comprises an oxide containing tantalum and nitrogen.Type: GrantFiled: May 16, 2008Date of Patent: April 3, 2012Assignee: Panasonic CorporationInventors: Satoru Fujii, Yoshihiko Kanzawa, Takeshi Takagi, Kazuhiko Shimakawa
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Publication number: 20120074375Abstract: The variable resistance nonvolatile storage device includes a memory cell (300) that is formed by connecting in series a variable resistance element (309) including a variable resistance layer (309b) which reversibly changes based on electrical signals each having a different polarity and a transistor (317) including a semiconductor substrate (301) and two N-type diffusion layer regions (302a, 302b), wherein the variable resistance layer (309b) includes an oxygen-deficient oxide of a transition metal, lower and upper electrodes (309a, 309c) are made of materials of different elements, a standard electrode potential V1 of the lower electrode (309a), a standard electrode potential V2 of the upper electrode (309c), and a standard electrode potential Vt of the transition metal satisfy Vt<V2 and V1<V2, and the lower electrode (309a) is connected with the N-type diffusion layer region (302b), the electrical signals being applied between the lower and upper electrodes (309a, 309c).Type: ApplicationFiled: December 5, 2011Publication date: March 29, 2012Inventors: Kazuhiko SHIMAKAWA, Yoshihiko Kanzawa, Satoru Mitani, Shunsaku Muraoka
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Publication number: 20120044749Abstract: A variable resistance nonvolatile storage device which includes (i) a semiconductor substrate (301), (ii) a variable resistance element (309) having: lower and upper electrodes (309a, 309c); and a variable resistance layer (309b) whose resistance value reversibly varies based on voltage signals each of which has a different polarity and is applied between the electrodes (309a, 309c), and (iii) a MOS transistor (317) formed on the substrate (301), wherein the variable resistance layer (309b) includes: oxygen-deficient transition metal oxide layers (309b-1, 309b-2) having compositions MOx and MOy (where x<y) and in contact with the electrodes (309a, 309c) respectively, and a diffusion layer region (302b) is connected with the lower electrode (309a) to form a memory cell (300), the region (302b) serving as a drain of the transistor (317) upon application of a voltage signal which causes a resistance change to high resistance state in the variable resistance layer (309b).Type: ApplicationFiled: November 2, 2010Publication date: February 23, 2012Inventors: Shunsaku Muraoka, Yoshihiko Kanzawa, Takeshi Takagi, Kazuhiko Shimakawa
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Patent number: 8094485Abstract: The variable resistance nonvolatile storage device includes a memory cell (300) that is formed by connecting in series a variable resistance element (309) including a variable resistance layer (309b) which reversibly changes based on electrical signals each having a different polarity and a transistor (317) including a semiconductor substrate (301) and two N-type diffusion layer regions (302a, 302b), wherein the variable resistance layer (309b) includes an oxygen-deficient oxide of a transition metal, lower and upper electrodes (309a, 309c) are made of materials of different elements, a standard electrode potential V1 of the lower electrode (309a), a standard electrode potential V2 of the upper electrode (309c), and a standard electrode potential Vt of the transition metal satisfy Vt<V2 and V1<V2, and the lower electrode (309a) is connected with the N-type diffusion layer region (302b), the electrical signals being applied between the lower and upper electrodes (309a, 309c).Type: GrantFiled: December 15, 2008Date of Patent: January 10, 2012Assignee: Panasonic CorporationInventors: Kazuhiko Shimakawa, Yoshihiko Kanzawa, Satoru Mitani, Shunsaku Muraoka
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Publication number: 20110294259Abstract: A nonvolatile memory element comprises a first electrode layer (103), a second electrode (107), and a resistance variable layer (106) which is disposed between the first electrode layer (103) and the second electrode layer (107), a resistance value of the resistance variable layer varying reversibly according to electric signals having different polarities which are applied between the electrodes (103), (107), wherein the resistance variable layer (106) has a first region comprising a first oxygen-deficient tantalum oxide having a composition represented by TaOx (0<x<2.5) and a second region comprising a second oxygen-deficient tantalum oxide having a composition represented by TaOy (x<y<2.5), the first region and the second region being arranged in a thickness direction of the resistance variable layer.Type: ApplicationFiled: August 8, 2011Publication date: December 1, 2011Applicant: Panasonic CorporationInventors: Yoshihiko KANZAWA, Koji Katayama, Satoru Fujii, Shunsaku Muraoka, Koichi Osano, Satoru Mitani, Ryoko Miyanaga, Takeshi Takagi, Kazuhiko Shimakawa
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Publication number: 20110244645Abstract: A semiconductor device includes: a semiconductor substrate in which a trench is formed; a source region and a drain region each of which is buried in the trench and contains an impurity of the same conductive type; a semiconductor FIN buried in the trench and provided between the source and drain regions; a gate insulating film provided on a side surface of the semiconductor FIN as well as the upper surface of the semiconductor FIN; and a gate electrode formed on the gate insulating film.Type: ApplicationFiled: June 16, 2011Publication date: October 6, 2011Applicant: Panasonic CorporationInventors: Junko IWANAGA, Takeshi Takagi, Yoshihiko Kanzawa, Haruyuki Sorada, Tohru Saitoh, Takahiro Kawashima
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Publication number: 20110233510Abstract: A nonvolatile memory element of the present invention comprises a first electrode (103); a second electrode (109); and a resistance variable layer (106) disposed between the first electrode and the second electrode, resistance values of the resistance variable layer reversibly changing in response to electric signals applied between the first electrode and the second electrode; at least one of the first electrode and the second electrode including a platinum-containing layer (107) comprising platinum; the resistance variable layer including at least a first oxygen-deficient transition metal oxide layer (104) which is not physically in contact with the platinum-containing layer and a second oxygen-deficient transition metal oxide layer (105) which is disposed between the first oxygen-deficient transition metal oxide layer and the platinum-containing layer and is physically in contact with the platinum-containing layer; x<y being satisfied when an oxygen-deficient transition metal oxide included in the firstType: ApplicationFiled: December 1, 2009Publication date: September 29, 2011Inventors: Yoshihiko Kanzawa, Satoru Mitani, Zhiqiang Wei, Takeshi Takagi, Koji Katayama
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Patent number: 8022502Abstract: A nonvolatile memory element comprises a first electrode layer (103), a second electrode (107), and a resistance variable layer (106) which is disposed between the first electrode layer (103) and the second electrode layer (107), a resistance value of the resistance variable layer varying reversibly according to electric signals having different polarities which are applied between the electrodes (103), (107), wherein the resistance variable layer (106) has a first region comprising a first oxygen-deficient tantalum oxide having a composition represented by TaOx (0<x<2.5) and a second region comprising a second oxygen-deficient tantalum oxide having a composition represented by TaOy (x<y<2.5), the first region and the second region being arranged in a thickness direction of the resistance variable layer.Type: GrantFiled: March 26, 2008Date of Patent: September 20, 2011Assignee: Panasonic CorporationInventors: Yoshihiko Kanzawa, Koji Katayama, Satoru Fujii, Shunsaku Muraoka, Koichi Osano, Satoru Mitani, Ryoko Miyanaga, Takeshi Takagi, Kazuhiko Shimakawa
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Publication number: 20110182109Abstract: A variable resistance nonvolatile memory device (100) according to an aspect of the present invention includes: a plurality of memory cells (M11, M12, M21, M22) in each of which a variable resistance element (R11, R12, R21, R22) and a current steering element (D11, D12, D21, D22) having two terminals are connected in series; a current limit circuit (105b) which limits a first current flowing in a direction for changing the memory cells (M11, M12, M21, M22) to a low resistance state; and a boost circuit (105d) which increases, when one of the memory cells (M11, M12, M21, M22) changes to the low resistance state, the first current in a first period before the memory cell changes to the low resistance state.Type: ApplicationFiled: July 26, 2010Publication date: July 28, 2011Inventors: Yuichiro Ikeda, Kazuhiko Shimakawa, Yoshihiko Kanzawa, Shunsaku Muraoka, Yoshikazu Katoh
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Patent number: 7986002Abstract: A semiconductor device includes: a semiconductor substrate in which a trench is formed; a source region and a drain region each of which is buried in the trench and contains an impurity of the same conductive type; a semiconductor FIN buried in the trench and provided between the source and drain regions; a gate insulating film provided on a side surface of the semiconductor FIN as well as the upper surface of the semiconductor FIN; and a gate electrode formed on the gate insulating film.Type: GrantFiled: March 19, 2004Date of Patent: July 26, 2011Assignee: Panasonic CorporationInventors: Junko Iwanaga, Takeshi Takagi, Yoshihiko Kanzawa, Haruyuki Sorada, Tohru Saitoh, Takahiro Kawashima
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Publication number: 20110122680Abstract: A nonvolatile resistance variable memory device (100) includes memory cells (M11, M12, . . . ) in each of which a variable resistance element (R11, R12, . . . ) including a variable resistance layer placed between and in contact with a first electrode and a second electrode, and a current steering element (D11, D12, . . . ) including a current steering layer placed between and in contact with a third electrode and a fourth electrode, are connected in series, and the device is driven by a first LR drive circuit (105a1) via a current limit circuit (105b) to decrease resistance of the variable resistance element while the device is driven by a second HR drive circuit (105a2) to increase resistance of the variable resistance element, thus using the current limit circuit (105b) to make a current for decreasing resistance of the variable resistance element lower than a current for increasing resistance of the variable resistance element.Type: ApplicationFiled: April 14, 2010Publication date: May 26, 2011Inventors: Yuuichirou Ikeda, Kazuhiko Shimakawa, Yoshihiko Kanzawa, Shunsaku Muraoka, Ryotaro Azuma
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Publication number: 20110110143Abstract: Provided is a programming method for improving the retention characteristics of information in a variable resistance nonvolatile memory element. The method includes: a first writing process of applying a first voltage V1 having a first polarity to set the variable resistance nonvolatile storage element to a low resistance state LR indicating first logic information (S01); a second writing process of applying a second voltage V2 having a second polarity different from the first polarity to set the variable resistance nonvolatile storage element to a first high resistance state HR1 (S02); and a partial write process of applying a third voltage V3 having the first polarity so as to set the variable resistance layer to a second high resistance state HR2 indicating second logic information different from the first logic information (S05). Here, |V3|<|V1|, and resistance values in HR1, HR2, LR are greater in this order.Type: ApplicationFiled: April 9, 2010Publication date: May 12, 2011Inventors: Yoshihiko Kanzawa, Takeshi Takagi