Abstract: Memory cells (MC) are formed at intersections of bit lines (BL) extending in the X direction and word lines (WL) extending in the Y direction. A plurality of basic array planes sharing the word lines (WL), each formed for a group of bit lines (BL) aligned in the Z direction, are arranged side by side in the Y direction. In each basic array plane, bit lines in even layers and bit lines in odd layers are individually connected in common. Each of selection switch elements (101 to 104) controls switching of electrical connection/non-connection between the common-connected even layer bit line and a global bit line (GBL), and each of selection switch elements (111 to 114) control switching of connection/non-connection between the common-connected odd layer bit line and the global bit line (GBL).

Abstract: Each of memory cells (MC) includes one transistor and one resistance variable element. The transistor includes a first main terminal, a second main terminal and a control terminal. The resistance variable element includes a first electrode, a second electrode and a resistance variable layer provided between the first electrode and the second electrode. A first main terminal of one of two adjacent memory cells is connected to a second main terminal of the other memory cell, to form a series path (SP) sequentially connecting main terminals of the plurality of memory cells in series.

Abstract: Provided is a nonvolatile memory element which is capable of performing a stable resistance change operation at a low breakdown voltage. A nonvolatile memory element (100) includes: a first electrode layer (103); a second electrode layer (105); and a variable resistance layer (104) which is placed between the electrodes (103 and 105), and whose resistance state reversibly changes between a high resistance state and a low resistance state based on a polarity of a voltage applied between the electrodes (103 and 105). The variable resistance layer (104) is formed by stacking a first oxide layer (104a) including an oxide of a first transition metal and a second oxide layer (104b) including an oxide of a second transition metal which is different from the first transition metal.

Abstract: A variable resistance nonvolatile storage device which includes (i) a semiconductor substrate (301), (ii) a variable resistance element (309) having: lower and upper electrodes (309a, 309c); and a variable resistance layer (309b) whose resistance value reversibly varies based on voltage signals each of which has a different polarity and is applied between the electrodes (309a, 309c), and (iii) a MOS transistor (317) formed on the substrate (301), wherein the variable resistance layer (309b) includes: oxygen-deficient transition metal oxide layers (309b-1, 309b-2) having compositions MOx and MOy (where x<y) and in contact with the electrodes (309a, 309c) respectively, and a diffusion layer region (302b) is connected with the lower electrode (309a) to form a memory cell (300), the region (302b) serving as a drain of the transistor (317) upon application of a voltage signal which causes a resistance change to high resistance state in the variable resistance layer (309b).

Abstract: A resistance variable element of the present invention comprises a first electrode (103), a second electrode (107), and a resistance variable layer which is interposed between the first electrode (103) and the second electrode (107) to contact the first electrode (103) and the second electrode (107), the resistance variable layer being configured to change in response to electric signals with different polarities which are applied between the first electrode (103) and the second electrode (107), the resistance variable layer comprising an oxygen-deficient transition metal oxide layer, and the second electrode (107) comprising platinum having minute hillocks (108).

Abstract: A nonvolatile memory element of the present invention comprises a first electrode (103), a second electrode (108); a resistance variable layer (107) which is interposed between the first electrode (103) and the second electrode (107) and is configured to switch a resistance value reversibly in response to an electric signal applied between the electrodes (103) and (108), and the resistance variable layer (107) has at least a multi-layer structure in which a first hafnium-containing layer having a composition expressed as HfOx (0.9?x?1.6), and a second hafnium-containing layer having a composition expressed as HfOy (1.8<y<2.0) are stacked together.

Abstract: A nonvolatile memory element comprises a first electrode (103), a second electrode (105), and a resistance variable layer (104) which is provided between the first electrode and the second electrode, and is configured to reversibly switch an interelectrode resistance value which is a resistance value between the first electrode and the second electrode, in response to an interelectrode voltage which is an electric potential of the second electrode on the basis of the first electrode, the resistance variable layer includes an oxygen-deficient transition metal oxide, the first electrode side and the second electrode side have an asymmetric structure, a portion of the resistance variable layer which is located at the first electrode side and a portion of the resistance variable layer which is located at the second electrode side are each configured to be selectively placed into one of a low-resistance state and a high-resistance state, so as to attain a stable state in three or more different interelectrode resi

Abstract: A nonvolatile memory element of the present invention comprises a first electrode (503); a second electrode (505); and a resistance variable layer (504) which is disposed between the first electrode (503) and the second electrode (505), a resistance value of the resistance variable layer being changeable in response to electric signals which are applied between the first electrode (503) and the second electrode (505), wherein the first electrode and the second electrode comprise materials which are made of different elements.

Abstract: A nonvolatile memory element comprises a first electrode (503), a second electrode (505), and a resistance variable layer (504) disposed between the first electrode and the second electrode, a resistance value between the first electrode and the second electrode being switchable reversibly in response to positive and negative electric signals applied between the first electrode and the second electrode; wherein the resistance variable layer includes an oxygen-deficient hafnium oxide; wherein the first electrode and the second electrode comprise elements which are different from each other; and wherein a standard electrode potential V1 of an element forming the first electrode, a standard electrode potential V2 of an element forming the second electrode and a standard electrode potential V0 of hafnium satisfy a relationship of V1<V2 and V0<V2.

Abstract: The variable resistance nonvolatile storage device includes a memory cell (300) that is formed by connecting in series a variable resistance element (309) including a variable resistance layer (309b) which reversibly changes based on electrical signals each having a different polarity and a transistor (317) including a semiconductor substrate (301) and two N-type diffusion layer regions (302a, 302b), wherein the variable resistance layer (309b) includes an oxygen-deficient oxide of a transition metal, lower and upper electrodes (309a, 309c) are made of materials of different elements, a standard electrode potential V1 of the lower electrode (309a), a standard electrode potential V2 of the upper electrode (309c), and a standard electrode potential Vt of the transition metal satisfy Vt<V2 and V1<V2, and the lower electrode (309a) is connected with the N-type diffusion layer region (302b), the electrical signals being applied between the lower and upper electrodes (309a, 309c).

Abstract: A nonvolatile semiconductor apparatus of the present invention comprises (103), a second electrode (105), and a resistance variable layer (104) disposed between the first electrode (103) and the second electrode (105), a resistance value of the resistance variable layer being switchable reversibly in response to an electric signal applied between the electrodes (103), (105), wherein the resistance variable layer (104) comprises an oxide containing tantalum and nitrogen.

Abstract: A bipolar transistor 120 comprises a substrate 1, a intrinsic base region 11 and an extrinsic base region 12. The intrinsic base region 11 comprises a silicon buffer layer 109 comprised of silicon which is formed on the substrate 1, and a composition-ratio graded base layer 111 which is formed on the silicon buffer layer and comprises silicon and at least germanium and where a composition ratio of the germanium to the silicon varies in a thickness direction of the composition-ratio graded base layer 111. The extrinsic base region 12 comprises an extrinsic base formation layer 113 comprised of silicon which is formed on the substrate and adjacent to the silicon buffer layer. And the thickness of the extrinsic base formation layer 113 is not less than 40 nm.

Abstract: A nonvolatile memory element comprises a first electrode layer (103), a second electrode (107), and a resistance variable layer (106) which is disposed between the first electrode layer (103) and the second electrode layer (107), a resistance value of the resistance variable layer varying reversibly according to electric signals having different polarities which are applied between the electrodes (103), (107), wherein the resistance variable layer (106) has a first region comprising a first oxygen-deficient tantalum oxide having a composition represented by TaOx (0<x<2.5) and a second region comprising a second oxygen-deficient tantalum oxide having a composition represented by TaOy (x<y<2.5), the first region and the second region being arranged in a thickness direction of the resistance variable layer.

Abstract: A semiconductor device according to this invention includes: a first insulating layer (11); a first body section (13) including an island-shaped semiconductor formed on the first insulating layer; a second body section (14) including an island-shaped semiconductor formed on the first insulating layer; a ridge-shaped connecting section (15) formed on the first insulating layer to interconnect the first body section and the second body section; a channel region (15a) formed by at least a part of the connecting section in lengthwise direction of the connecting section; a gate electrode (18) formed to cover a periphery of the channel region, with a second insulating layer intervening therebetween; a source region formed to extend over the first body section and a portion of the connecting section between the first body section and the channel region; and a drain region formed to extend over the second body section and a portion of the connecting section between the second body section and the channel region, wher

Abstract: A bipolar transistor 120 comprises a substrate 1, a intrinsic base region 11 and an extrinsic base region 12. The intrinsic base region 11 comprises a silicon buffer layer 109 comprised of silicon which is formed on the substrate 1, and a composition-ratio graded base layer 111 which is formed on the silicon buffer layer and comprises silicon and at least germanium and where a composition ratio of the germanium to the silicon varies in a thickness direction of the composition-ratio graded base layer 111. The extrinsic base region 12 comprises an extrinsic base formation layer 113 comprised of silicon which is formed on the substrate and adjacent to the silicon buffer layer. And the thickness of the extrinsic base formation layer 113 is not less than 40 nm.

Abstract: A semiconductor device according to this invention includes: a first insulating layer (11); a first body section (13) including an island-shaped semiconductor formed on the first insulating layer; a second body section (14) including an island-shaped semiconductor formed on the first insulating layer; a ridge-shaped connecting section (15) formed on the first insulating layer to interconnect the first body section and the second body section; a channel region (15a) formed by at least a part of the connecting section in lengthwise direction of the connecting section; a gate electrode (18) formed to cover a periphery of the channel region, with a second insulating layer intervening therebetween; a source region formed to extend over the first body section and a portion of the connecting section between the first body section and the channel region; and a drain region formed to extend over the second body section and a portion of the connecting section between the second body section and the channel region, wher

Abstract: A method of forming semiconductor crystal of the present invention comprises the steps of heating a Si substrate to clean a surface of the Si substrate, epitaxially growing Si crystal on the Si substrate inside a crystal growth chamber at a growth temperature lower than a substrate temperature of the Si substrate in the cleaning step and higher than a growth temperature at which SiGe crystal is epitaxially grown later, and epitaxially growing the SiGe crystal on the Si crystal.

Abstract: A semiconductor device includes: a semiconductor substrate in which a trench is formed; a source region and a drain region each of which is buried in the trench and contains an impurity of the same conductive type; a semiconductor FIN buried in the trench and provided between the source and drain regions; a gate insulating film provided on a side surface of the semiconductor FIN as well as the upper surface of the semiconductor FIN; and a gate electrode formed on the gate insulating film.

Abstract: A method for fabricating a semiconductor crystal that has a first step for forming a semiconductor crystal layer (202) that contains carbon atoms and at least one kind of Group IV element other than carbon on a substrate (201), a second step for adding an impurity that is capable of reacting with oxygen to the semiconductor crystal layer (202), and a third step for removing the carbon atoms contained in the semiconductor crystal layer (202) by reacting the carbon with the impurity. This method makes it possible to fabricate a semiconductor crystal substrate in which the concentration of interstitial carbon atoms is satisfactorily reduced, thus resulting in excellent electrical properties when the substrate is applied to a semiconductor device.

Abstract: A Si substrate 1 with a SiGeC crystal layer 8 deposited thereon is annealed to form an annealed SiGeC crystal layer 10 on the Si substrate 1. The annealed SiGeC crystal layer includes a matrix SiGeC crystal layer 7, which is lattice-relieved and hardly has dislocations, and SiC microcrystals 6 dispersed in the matrix SiGeC crystal layer 7. A Si crystal layer is then deposited on the annealed SiGeC crystal layer 10, to form a strained Si crystal layer 4 hardly having dislocations.