Patents by Inventor Yoshihisa Iwata

Yoshihisa Iwata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Magnetic random access memory
    Patent number: 6912154
    Abstract: In the first read operation, a read current is supplied to TMR elements connected in parallel in one column or one block to detect initial data. Trial data is then written in a selected memory cell. At the same time of or in parallel with writing of the trial data, the second read operation is performed. In the second read operation, a read current is supplied to the TMR elements connected in parallel in one column or one block to read comparison data. Subsequently, the initial data is compared with the comparison data to determine the data value in the selected memory cell. Finally, rewrite operation is performed for the selected memory cell.
    Type: Grant
    Filed: September 14, 2004
    Date of Patent: June 28, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshihisa Iwata
  • Magnetic random access memory
    Patent number: 6912152
    Abstract: A magnetic random access memory includes a memory cell array having memory cells using a magnetoresistive effect, a first functional line which runs in a first direction in the memory cell array and is commonly connected without an intervening select switch to one terminal of each of the memory cells, second functional lines which are arranged in correspondence with the memory cells and run in a second direction perpendicular to the first direction in the memory cell array, each second functional line being connected without an intervening select switch to a corresponding memory cell, and a third functional line which is electrically insulated from the memory cells and generates a magnetic field to write data in the memory cells such that the magnetic field is shared by the memory cells.
    Type: Grant
    Filed: February 21, 2003
    Date of Patent: June 28, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshihisa Iwata, Tomoki Higashi
  • Magnetic random access memory
    Patent number: 6906948
    Abstract: In the first read operation, a read current is supplied to TMR elements connected in parallel in one column or one block to detect initial data. Trial data is then written in a selected memory cell. At the same time of or in parallel with writing of the trial data, the second read operation is performed. In the second read operation, a read current is supplied to the TMR elements connected in parallel in one column or one block to read comparison data. Subsequently, the initial data is compared with the comparison data to determine the data value in the selected memory cell. Finally, rewrite operation is performed for the selected memory cell.
    Type: Grant
    Filed: September 14, 2004
    Date of Patent: June 14, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshihisa Iwata
  • Magnetic random access memory
    Publication number: 20050105375
    Abstract: In the first read operation, a read current is supplied to TMR elements connected in parallel in one column or one block to detect initial data. Trial data is then written in a selected memory cell. At the same time of or in parallel with writing of the trial data, the second read operation is performed. In the second read operation, a read current is supplied to the TMR elements connected in parallel in one column or one block to read comparison data. Subsequently, the initial data is compared with the comparison data to determine the data value in the selected memory cell. Finally, rewrite operation is performed for the selected memory cell.
    Type: Application
    Filed: September 14, 2004
    Publication date: May 19, 2005
    Inventor: Yoshihisa Iwata
  • MRAM having memory cell array in which cross-point memory cells are arranged by hierarchical bit line scheme and data read method thereof
    Patent number: 6891748
    Abstract: A memory cell array is of a hierarchical bit line scheme in which cross-point memory cells that exhibit a magnetoresistive effect are laid out in a matrix, and a read bit line to be used in a data read mode is constituted by a main bit line and a sub bit line. A column select circuit selects a main bit line and connects it to a sense amplifier. A row select circuit selects a word line for each cell unit, and in read operation, sets, in a floating state, word lines to which unselected memory cells connected to the sub bit line to which a selected memory cell is connected are connected, and sets the remaining word lines connected to sub bit lines which do not include the selected memory cell to a potential substantially equal to the main bit line.
    Type: Grant
    Filed: July 18, 2003
    Date of Patent: May 10, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenji Tsuchida, Yoshihisa Iwata, Tomoki Higashi
  • Magnetic memory
    Publication number: 20050083745
    Abstract: A magnetic memory includes: a magnetoresistance effect element having a magnetic recording layer; a first writing wiring extending in a first direction on or below the magnetoresistance effect element, a center of gravity of an axial cross section of the wiring being apart from a center of thickness at the center of gravity, and the center of gravity being eccentric toward the magnetoresistance effect element; and a writing circuit configured to pass a current through the first writing wiring in order to record an information in the magnetic recording layer by a magnetic field generated by the current.
    Type: Application
    Filed: November 5, 2004
    Publication date: April 21, 2005
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tatsuya Kishi, Minoru Amano, Yoshiaki Saito, Shigeki Takahashi, Katsuya Nishiyama, Yoshiaki Asao, Hiroaki Yoda, Tomomasa Ueda, Yoshihisa Iwata
  • Magnetic random access memory
    Publication number: 20050083730
    Abstract: A read block is formed from a plurality of TMR elements stacked in the vertical direction. One terminal of each TMR element in the read block is connected to a source line through a read select switch. The source line extends in the Y-direction and is connected to a ground point through a column select switch. The other terminal of each TMR element is independently connected to a corresponding one of read/write bit lines. Each read/write bit line extends in the Y-direction and is connected to a read circuit through the column select switch.
    Type: Application
    Filed: November 4, 2004
    Publication date: April 21, 2005
    Inventor: Yoshihisa Iwata
  • Magnetic random access memory
    Publication number: 20050083734
    Abstract: A read block is formed from a plurality of TMR elements stacked in the vertical direction. One terminal of each TMR element in the read block is connected to a source line through a read select switch. The source line extends in the Y-direction and is connected to a ground point through a column select switch. The other terminal of each TMR element is independently connected to a corresponding one of read/write bit lines. Each read/write bit line extends in the Y-direction and is connected to a read circuit through the column select switch.
    Type: Application
    Filed: November 4, 2004
    Publication date: April 21, 2005
    Inventor: Yoshihisa Iwata
  • Magnetic random access memory
    Publication number: 20050083731
    Abstract: A read block is formed from a plurality of TMR elements stacked in the vertical direction. One terminal of each TMR element in the read block is connected to a source line through a read select switch. The source line extends in the Y-direction and is connected to a ground point through a column select switch. The other terminal of each TMR element is independently connected to a corresponding one of read/write bit lines. Each read/write bit line extends in the Y-direction and is connected to a read circuit through the column select switch.
    Type: Application
    Filed: November 4, 2004
    Publication date: April 21, 2005
    Inventor: Yoshihisa Iwata
  • Magnetic random access memory
    Patent number: 6873023
    Abstract: A write word line is disposed right under an MTJ element. The write word line extends in an X direction, and a lower surface of the line is coated with a yoke material which has a high permeability. A data selection line (read/write bit line) is disposed right on the MTJ element. A data selection line extends in a Y direction intersecting with the X direction, and an upper surface of the line is coated with the yoke material which has the high permeability. At a write operation time, a magnetic field generated by a write current flowing through a write word line B and data selection line functions on the MTJ element by the yoke material with good efficiency.
    Type: Grant
    Filed: April 18, 2003
    Date of Patent: March 29, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiaki Asao, Yoshihisa Iwata, Yoshiaki Saito, Hiroaki Yoda, Tomomasa Ueda, Minoru Amano, Shigeki Takahashi, Tatsuya Kishi
  • Magnetic random access memory having test circuit and test method therefor
    Publication number: 20050047202
    Abstract: An MRAM has an internal test circuit. This test circuit detects a bit in a memory cell array, which has a shift in write characteristics, as a defective bit by using a method of applying a one-axis write current along an axis of hard magnetization.
    Type: Application
    Filed: December 8, 2003
    Publication date: March 3, 2005
    Inventors: Yuui Shimizu, Yoshihisa Iwata, Kenji Tsuchida, Tatsuya Kishi
  • Magnetic random access memory for storing information utilizing magneto-resistive effects
    Patent number: 6862210
    Abstract: A memory cell comprises a magneto-resistive element of which electrical resistance value varies with magnetism. A sub-bit line is connected to one end of the memory cell. A main-bit line is connected to the sub-bit line via a first selection circuit. A sense-amplifier is connected to the main-bit line via a second selection circuit. A wiring line is connected to the other end of the memory cell and arranged in a first direction. A first operation circuit is connected to one end of the wiring line via a third selection circuit. A second operation circuit is connected to the other end of the wiring line. A word line passes over an intersection between the memory cell and the wiring line and is arranged in a second direction perpendicular to the first direction.
    Type: Grant
    Filed: April 25, 2003
    Date of Patent: March 1, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenji Tsuchida, Yoshihisa Iwata, Tomoki Higashi
  • Magnetic random access memory
    Publication number: 20050036354
    Abstract: In the first read operation, a read current is supplied to TMR elements connected in parallel in one column or one block to detect initial data. Trial data is then written in a selected memory cell. At the same time of or in parallel with writing of the trial data, the second read operation is performed. In the second read operation, a read current is supplied to the TMR elements connected in parallel in one column or one block to read comparison data. Subsequently, the initial data is compared with the comparison data to determine the data value in the selected memory cell. Finally, rewrite operation is performed for the selected memory cell.
    Type: Application
    Filed: September 14, 2004
    Publication date: February 17, 2005
    Inventor: Yoshihisa Iwata
  • Magnetic random access memory
    Publication number: 20050036376
    Abstract: TMR elements are arranged at the intersections between word lines and bit lines. One end of each word line is connected to the ground point through a row select switch. One end of each bit line is connected to a bit line bias circuit. In read operation, the bit line bias circuit applies a bias potential to all the bit lines. The selected word line is short-circuited to the ground point. Unselected word lines are set in a floating state.
    Type: Application
    Filed: September 21, 2004
    Publication date: February 17, 2005
    Inventors: Yoshihisa Iwata, Tomoki Higashi
  • Semiconductor memory device having memory cells including ferromagnetic films and control method thereof
    Publication number: 20050036362
    Abstract: A semiconductor memory device comprises word lines, bit lines, memory cells, a row decoder, a column decoder, and a write circuit. The word lines are formed along a first direction. The bit lines are formed along a second direction. Memory cells include magneto-resistive elements and are arranged at intersections of the word lines and the bit lines. The row decoder selects at least one of the word lines. The column decoder selects at least one of the bit lines. The write circuit supplies first and second write currents to a selected word line and selected bit line respectively and writes data into a selected memory cell arranged at the intersection of the selected word line and the selected bit line. The write circuit changes the current values of the first and second write currents according to a temperature change.
    Type: Application
    Filed: March 24, 2004
    Publication date: February 17, 2005
    Inventors: Yoshihisa Iwata, Kentaro Nakajima, Masayuki Sagoi, Yuui Shimizu
  • Magnetic random access memory
    Publication number: 20050036384
    Abstract: In the first read operation, a read current is supplied to TMR elements connected in parallel in one column or one block to detect initial data. Trial data is then written in a selected memory cell. At the same time of or in parallel with writing of the trial data, the second read operation is performed. In the second read operation, a read current is supplied to the TMR elements connected in parallel in one column or one block to read comparison data. Subsequently, the initial data is compared with the comparison data to determine the data value in the selected memory cell. Finally, rewrite operation is performed for the selected memory cell.
    Type: Application
    Filed: September 14, 2004
    Publication date: February 17, 2005
    Inventor: Yoshihisa Iwata
  • Magnetic random access memory
    Publication number: 20050030830
    Abstract: In the first read operation, a read current is supplied to TMR elements connected in parallel in one column or one block to detect initial data. Trial data is then written in a selected memory cell. At the same time of or in parallel with writing of the trial data, the second read operation is performed. In the second read operation, a read current is supplied to the TMR elements connected in parallel in one column or one block to read comparison data. Subsequently, the initial data is compared with the comparison data to determine the data value in the selected memory cell. Finally, rewrite operation is performed for the selected memory cell.
    Type: Application
    Filed: September 14, 2004
    Publication date: February 10, 2005
    Inventor: Yoshihisa Iwata
  • Magnetic random access memory
    Publication number: 20050030785
    Abstract: In the first read operation, a read current is supplied to TMR elements connected in parallel in one column or one block to detect initial data. Trial data is then written in a selected memory cell. At the same time of or in parallel with writing of the trial data, the second read operation is performed. In the second read operation, a read current is supplied to the TMR elements connected in parallel in one column or one block to read comparison data. Subsequently, the initial data is compared with the comparison data to determine the data value in the selected memory cell. Finally, rewrite operation is performed for the selected memory cell.
    Type: Application
    Filed: September 14, 2004
    Publication date: February 10, 2005
    Inventor: Yoshihisa Iwata
  • Magnetic random access memory
    Patent number: 6842362
    Abstract: One end of a write word line is connected to a decoder/driver unit. The decoder/driver unit is constituted by a P channel MOS transistor, an N channel MOS transistor, a differential amplifier, and an NAND circuit. When WRITE, CHRDY and RA1 all become “H”, an output signal from the NAND circuit becomes “H”, and a write current flows through the write word line. At this moment, a value of the write current is restricted to a value which does not exceed VLIMIT/R1 by the differential amplifier. R1 is a wiring resistance of the write word line.
    Type: Grant
    Filed: February 20, 2003
    Date of Patent: January 11, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuyuki Fujita, Yoshihisa Iwata
  • Magnetic random access memory
    Patent number: 6839269
    Abstract: TMR elements are arranged at the intersections between word lines and bit lines. One end of each word line is connected to the ground point through a row select switch. One end of each bit line is connected to a bit line bias circuit. In read operation, the bit line bias circuit applies a bias potential to all the bit lines. The selected word line is short-circuited to the ground point. Unselected word lines are set in a floating state.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: January 4, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshihisa Iwata, Tomoki Higashi