Patents by Inventor Yoshihisa Iwata

Yoshihisa Iwata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor apparatus having logic level decision circuit and inter-semiconductor apparatus signal transmission system
    Publication number: 20060023518
    Abstract: In a signal transmission system between a plurality of semiconductor apparatuses, a logic level decision circuit deciding a logic level of an input signal in accordance with which of two reference signals a signal level of the input signal is close to, by using two reference signals Vref1, Vref0 having a “1” level and a “0” level as reference signals for deciding the logic level of the input signal having a binary logic level, is used as an input receiver of the each semiconductor apparatus.
    Type: Application
    Filed: July 22, 2003
    Publication date: February 2, 2006
    Inventor: Yoshihisa Iwata
  • Magnetic random access memory
    Patent number: 6990004
    Abstract: A read block is formed from a plurality of TMR elements stacked in the vertical direction. One terminal of each TMR element in the read block is connected to a source line through a read select switch. The source line extends in the Y-direction and is connected to a ground point through a column select switch. The other terminal of each TMR element is independently connected to a corresponding one of read/write bit lines. Each read/write bit line extends in the Y-direction and is connected to a read circuit through the column select switch.
    Type: Grant
    Filed: November 4, 2004
    Date of Patent: January 24, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshihisa Iwata
  • Semiconductor integrated circuit device and method of manufacturing the same
    Publication number: 20050274984
    Abstract: A semiconductor integrated circuit device includes a cell transistor; a bit line provided above the cell transistor; a magnetoresistive element provided above the bit line, a first end portion of the magnetoresistive element being electrically connected to the bit line; an intracell local interconnection provided above the magnetoresistive element, the intracell local interconnection coupling one of source and drain regions of the cell transistor to a second end portion of the magnetoresistive element; and a write word line provided above the intracell local interconnection, a portion between the write word line and the intracell local interconnection being filled with an insulator alone.
    Type: Application
    Filed: June 15, 2005
    Publication date: December 15, 2005
    Inventors: Keiji Hosotani, Yoshiaki Asao, Yoshiaki Saito, Minoru Amano, Shigeki Takahashi, Tatsuya Kishi, Yoshihisa Iwata
  • Non-volatile semiconductor memory device and memory system using the same
    Patent number: 6967892
    Abstract: The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite oepration, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.
    Type: Grant
    Filed: March 19, 2004
    Date of Patent: November 22, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomoharu Tanaka, Masaki Momodomi, Hideo Kato, Hiroto Nakai, Yoshiyuki Tanaka, Riichiro Shirota, Seiichi Aritome, Yasuo Itoh, Yoshihisa Iwata, Hiroshi Nakamura, Hideko Odaira, Yutaka Okamoto, Masamichi Asano, Kaoru Tokushige
  • Magnetic random access memory
    Publication number: 20050254294
    Abstract: A magnetic random access memory according to examples of the present invention comprises a magneto resistive element MTJ, and current source circuits I1, I2 and I3 which give a bias current/voltage to the magneto resistive element MTJ when data in the magneto resistive element MTJ is read, wherein a value of the bias current/voltage changes depending on temperature without depending on a power supply potential.
    Type: Application
    Filed: July 14, 2004
    Publication date: November 17, 2005
    Inventor: Yoshihisa Iwata
  • MRAM and method of manufacturing the same
    Publication number: 20050242384
    Abstract: A magnetic memory device comprising, a magneto-resistance effect element that is provided at an intersection between a first write line and a second write line. And the magneto-resistance effect element having, an easy axis that extends in a direction of extension of the first write line, and a first conductive layer for electrical connection to the magneto-resistance effect element, the first conductive layer having sides which are in flush with sides of the magneto-resistance effect element.
    Type: Application
    Filed: September 3, 2004
    Publication date: November 3, 2005
    Inventors: Yoshihisa Iwata, Yoshiaki Fukuzumi, Tadashi Kai
  • Magnetic random access memory and data read method thereof
    Patent number: 6961261
    Abstract: A magnetic random access memory having a memory cell array in which one block is formed from a plurality of magnetoresistive elements using a magnetoresistive effect, and a plurality of blocks are arranged in row and column directions, includes a plurality of first magnetoresistive elements arranged in a first block, a plurality of first word lines each of which is independently connected to one terminal of a corresponding one of the first magnetoresistive elements and runs in the row direction, a first read sub bit line commonly connected to the other terminal of each of the first magnetoresistive elements, a first block select switch whose first current path has one end connected to one end of the first read sub bit line, and a first read main bit line which is connected to the other end of the first current path and runs in the column direction.
    Type: Grant
    Filed: May 8, 2003
    Date of Patent: November 1, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshihisa Iwata
  • Semiconductor integrated circuit device and method of manufacturing the same
    Patent number: 6958932
    Abstract: A semiconductor integrated circuit device includes a cell transistor; a bit line provided above the cell transistor; a magnetoresistive element provided above the bit line, a first end portion of the magnetoresistive element being electrically connected to the bit line; an intracell local interconnection provided above the magnetoresistive element, the intracell local interconnection coupling one of source and drain regions of the cell transistor to a second end portion of the magnetoresistive element; and a write word line provided above the intracell local interconnection, a portion between the write word line and the intracell local interconnection being filled with an insulator alone.
    Type: Grant
    Filed: July 22, 2002
    Date of Patent: October 25, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keiji Hosotani, Yoshiaki Asao, Yoshiaki Saito, Minoru Amano, Shigeki Takahashi, Tatsuya Kishi, Yoshihisa Iwata
  • Magnetic random access memory
    Publication number: 20050232006
    Abstract: There is disclosed a magnetic random access memory according to an example of the present invention, comprising first and second write lines which intersect with each other, and a plurality of magneto resistive elements stacked on an intersecting portion of the first and second write lines, wherein easy axis directions of magnetizations of storage layers of the plurality of magneto resistive elements are different from each other.
    Type: Application
    Filed: June 23, 2004
    Publication date: October 20, 2005
    Inventor: Yoshihisa Iwata
  • Magnetic random access memory
    Publication number: 20050232002
    Abstract: Blocks are connected to a read bit line. One block has MTJ elements which are connected to each other in series between the read bit line and a ground terminal. A MTJ elements are superposed on, e.g., a semiconductor substrate. A read bit line is arranged on the superposed MTJ elements. A write word line extending in a X-direction and a write bit line extending in a Y-direction are arranged in the vicinity of the MTJ elements in the block.
    Type: Application
    Filed: June 8, 2005
    Publication date: October 20, 2005
    Inventor: Yoshihisa Iwata
  • Magnetic random access memory having test circuit and test method therefor
    Patent number: 6950334
    Abstract: An MRAM has an internal test circuit. This test circuit detects a bit in a memory cell array, which has a shift in write characteristics, as a defective bit by using a method of applying a one-axis write current along an axis of hard magnetization.
    Type: Grant
    Filed: December 8, 2003
    Date of Patent: September 27, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuui Shimizu, Yoshihisa Iwata, Kenji Tsuchida, Tatsuya Kishi
  • Magnetic random access memory device having write test mode
    Patent number: 6947315
    Abstract: Magnetoresistive elements as memory cells are two-dimensionally arranged. To write data in magnetoresistive elements, selected memory cells are subjected to current magnetic fields generated by a current in a row direction and current magnetic fields generated by a current in a column direction. A setting circuit holds set values used to set a write current, in order to vary the magnitudes of magnetic field in the row and column direction between a write test mode period and a normal operation period. In the write test mode, the value of a write current flowing through write interconnects is set on the basis of the set values held in the setting circuit.
    Type: Grant
    Filed: November 7, 2003
    Date of Patent: September 20, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshihisa Iwata
  • Magnetic random access memory
    Patent number: 6947317
    Abstract: In the first read operation, a read current is supplied to TMR elements connected in parallel in one column or one block to detect initial data. Trial data is then written in a selected memory cell. At the same time of or in parallel with writing of the trial data, the second read operation is performed. In the second read operation, a read current is supplied to the TMR elements connected in parallel in one column or one block to read comparison data. Subsequently, the initial data is compared with the comparison data to determine the data value in the selected memory cell. Finally, rewrite operation is performed for the selected memory cell.
    Type: Grant
    Filed: September 14, 2004
    Date of Patent: September 20, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshihisa Iwata
  • Magnetic random access memory
    Patent number: 6944048
    Abstract: Blocks are connected to a read bit line. One block has MTJ elements which are connected to each other in series between the read bit line and a ground terminal. A MTJ elements are superposed on, e.g., a semiconductor substrate. A read bit line is arranged on the superposed MTJ elements. A write word line extending in a X-direction and a write bit line extending in a Y-direction are arranged in the vicinity of the MTJ elements in the block.
    Type: Grant
    Filed: June 4, 2002
    Date of Patent: September 13, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshihisa Iwata
  • Magnetoresistive random access memory and driving method thereof
    Publication number: 20050195644
    Abstract: The number of read errors can be reduced, and a large read signal can be produced.
    Type: Application
    Filed: March 1, 2005
    Publication date: September 8, 2005
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Sumio Ikegawa, Yoshihisa Iwata, Kenji Tsuchida
  • Magnetic random access memory having memory cells configured by use of tunneling magnetoresistive elements
    Publication number: 20050195673
    Abstract: A magnetic random access memory includes memory cells each including a TMR element and a selection element, and a read circuit which reads storage information from the TMR element by applying read voltage to a selected one of the memory cells and causing a current to flow through the TMR element via the selection element. The read circuit includes a voltage setting section used to apply voltage which makes a resistance variation rate of the TMR element substantially equal to half a resistance variation rate thereof obtained when 0 V is applied across the TMR element to the TMR element at the information read time.
    Type: Application
    Filed: July 14, 2003
    Publication date: September 8, 2005
    Inventors: Yoshiaki Asao, Yoshihisa Iwata
  • Magnetic memory
    Patent number: 6934184
    Abstract: A highly reliable magnetic memory exhibits enhanced data-holding stability at high storage density in a storage layer of a magnetoresistive effect element used for memory cells. A magnetic memory includes a memory cell array having first wirings, second wirings intersecting the first wirings and memory cells each provided at an intersection area of the corresponding first and second wirings. Each memory cell is selected when the corresponding first and second wirings are selected.
    Type: Grant
    Filed: July 20, 2004
    Date of Patent: August 23, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Minoru Amano, Tatsuya Kishi, Hiroaki Yoda, Yoshiaki Saito, Shigeki Takahashi, Tomomasa Ueda, Katsuya Nishiyama, Yoshiaki Asao, Yoshihisa Iwata
  • Magnetic memory device and method of reading information
    Publication number: 20050180204
    Abstract: A memory cell of a magnetic memory device has an MTJ element and one end of the memory cell is selectively electrically connected to a ground potential line. A first bit line is electrically connected to the other end of the memory cell. A sense amplifier amplifies a difference in potential between the first bit line and a second bit line complementary to the first bit line so that the difference is equal to or larger than a difference between an internal power potential and a ground potential. A connection circuit disconnects the MTJ element from an electric connection between the ground potential line and the sense amplifier.
    Type: Application
    Filed: May 28, 2004
    Publication date: August 18, 2005
    Inventors: Ryousuke Takizawa, Kenji Tsuchida, Yoshihisa Iwata, Tsuneo Inaba
  • Magnetic random access memory
    Publication number: 20050157541
    Abstract: Memory cell arrays include a data cell array, a reference cell array and a dummy cell array. First read word lines are connected respectively to the gates of the read selection switches of the data cells. Second read word lines are connected respectively to the gates of the read selection switches of the reference cells. The gates of the read selection switches of the dummy cells are also connected respectively to the first and second read word lines but the dummy cells do not function as memory cells because the read selection switch and the MTJ element are cut apart in each of the dummy cells.
    Type: Application
    Filed: March 22, 2004
    Publication date: July 21, 2005
    Inventor: Yoshihisa Iwata
  • Semiconductor memory device for dynamically storing data with channel body of transistor used as storage node
    Publication number: 20050141262
    Abstract: A semiconductor memory device includes a plurality of MIS transistors arranged at intersections of first word lines and bit lines formed on an SOI substrate and each configuring a memory cell. Each of the plurality of MIS transistors includes a channel body formed in a semiconductor layer on an insulating film and set in an electrically floating state, a first extension region formed in contact with the channel body in the semiconductor layer and arranged in a first word line direction, a gate insulating film formed on the channel body, a gate electrode formed on the gate insulating film and electrically connected to a corresponding one of the first word lines, and source and drain regions separately formed in a bit line direction in the semiconductor layer to sandwich the channel body.
    Type: Application
    Filed: May 14, 2004
    Publication date: June 30, 2005
    Inventors: Takashi Yamada, Fumio Horiguchi, Takashi Ohsawa, Yoshihisa Iwata, Yoshiaki Asao