Patents by Inventor Yoshihisa Iwata

Yoshihisa Iwata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Magnetic random access memory device
    Patent number: 7079414
    Abstract: A memory cell array is constructed by two-dimensionally arranging a plurality of memory cells each composed of a magnetoresistive element, in a row and column directions. Write word lines are provided along the row direction of the memory cell array. Write bit lines are provided along the column direction of the memory cell array. To write data, a pulse-like write current is applied to an appropriate word and bit lines to generate magnetic fields in the column and row directions. A combined magnetic field of the magnetic fields in the column and row directions is applied to a memory cell to write data. A control circuit controls the pulse width of the pulse-like write current applied to the word and bit lines so that the pulse width has a predetermined temperature dependence.
    Type: Grant
    Filed: January 28, 2004
    Date of Patent: July 18, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshihisa Iwata, Yuui Shimizu
  • Semiconductor memory device for dynamically storing data with channel body of transistor used as storage node
    Patent number: 7075820
    Abstract: A semiconductor memory device includes a plurality of MIS transistors arranged at intersections of first word lines and bit lines formed on an SOI substrate and each configuring a memory cell. Each of the plurality of MIS transistors includes a channel body formed in a semiconductor layer on an insulating film and set in an electrically floating state, a first extension region formed in contact with the channel body in the semiconductor layer and arranged in a first word line direction, a gate insulating film formed on the channel body, a gate electrode formed on the gate insulating film and electrically connected to a corresponding one of the first word lines, and source and drain regions separately formed in a bit line direction in the semiconductor layer to sandwich the channel body.
    Type: Grant
    Filed: May 14, 2004
    Date of Patent: July 11, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Yamada, Fumio Horiguchi, Takashi Ohsawa, Yoshihisa Iwata, Yoshiaki Asao
  • Data write method of magnetic random access memory
    Publication number: 20060133136
    Abstract: A data write method of a magnetic random access memory including a magnetoresistive element which has axis of easy and hard magnetizations, a first write wiring which runs in a direction of the axis of easy magnetization, and a second write wiring which runs in a direction of the axis of hard magnetization, includes a first phase of supplying a first current to the first write wiring in a first direction and supplying a second current to the second write wiring in a second direction, a second phase of stopping supplying the first current to the first write wiring and supplying the second current to the second write wiring in the second direction, and a third phase of supplying the first current to the first write wiring in a third direction reverse to the first direction and supplying the second current to the second write wiring in the second direction.
    Type: Application
    Filed: February 9, 2005
    Publication date: June 22, 2006
    Inventor: Yoshihisa Iwata
  • Magnetic random access memory
    Patent number: 7064975
    Abstract: A read block is formed from a plurality of TMR elements stacked in the vertical direction. One terminal of each TMR element in the read block is connected to a source line through a read select switch. The source line extends in the Y-direction and is connected to a ground point through a column select switch. The other terminal of each TMR element is independently connected to a corresponding one of read/write bit lines. Each read/write bit line extends in the Y-direction and is connected to a read circuit through the column select switch.
    Type: Grant
    Filed: November 4, 2004
    Date of Patent: June 20, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshihisa Iwata
  • Magnetic random access memory
    Publication number: 20060118842
    Abstract: A magnetic random access memory according to an example of the present invention comprises a magnetoresistive element, a write line for use in generation of a magnetic field for data writing with respect to the magnetoresistive element, and a strained layer which is disposed so as to correspond to the magnetoresistive element, and which has a function of being physically deformed at the time of data writing, and of controlling a magnitude of an switching magnetic field of the magnetoresistive element.
    Type: Application
    Filed: January 19, 2005
    Publication date: June 8, 2006
    Inventor: Yoshihisa Iwata
  • Non-volatile semiconductor memory device and memory system using the same
    Publication number: 20060114729
    Abstract: The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.
    Type: Application
    Filed: October 6, 2005
    Publication date: June 1, 2006
    Inventors: Tomoharu Tanaka, Masaki Momodomi, Hideo Kato, Hiroto Nakai, Yoshiyuki Tanaka, Riichiro Shirota, Seiichi Aritome, Yasuo Itoh, Yoshihisa Iwata, Hiroshi Nakamura, Hideko Odaira, Yutaka Okamoto, Masamichi Asano, Kaoru Tokushige
  • Magnetic random access memory
    Patent number: 7054186
    Abstract: There is disclosed a magnetic random access memory according to an example of the present invention, comprising first and second write lines which intersect with each other, and a plurality of magneto resistive elements stacked on an intersecting portion of the first and second write lines, wherein easy axis directions of magnetizations of storage layers of the plurality of magneto resistive elements are different from each other.
    Type: Grant
    Filed: June 23, 2004
    Date of Patent: May 30, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshihisa Iwata
  • Magnetic memory device
    Patent number: 7054188
    Abstract: A magnetic memory device includes a memory cell array including MTJ elements provided at the coordinates (x, y). First write lines extend in a direction neither perpendicular nor parallel to the magnetization easy axis direction of the MTJ elements. One and the other end of one first write line pass an upper or lower periphery of the memory cell array and a left or right periphery of the memory cell array, respectively. The first write lines and second write lines sandwich the MTJ elements. First write line drivers are connected to both ends of the first write lines, one and the other end of a pair of the first write line drivers connected to ends of one first write lines are located outside the upper or lower periphery and outside the left or right periphery, respectively. Second write line drivers are connected to both ends of the second write lines.
    Type: Grant
    Filed: December 16, 2004
    Date of Patent: May 30, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryousuke Takizawa, Junichi Miyamoto, Yoshihisa Iwata
  • Magnetic memory
    Patent number: 7054187
    Abstract: A magnetic memory includes: a magnetoresistance effect element having a magnetic recording layer; a first writing wiring extending in a first direction on or below the magnetoresistance effect element, a center of gravity of an axial cross section of the wiring being apart from a center of thickness at the center of gravity, and the center of gravity being eccentric toward the magnetoresistance effect element; and a writing circuit configured to pass a current through the first writing wiring in order to record an information in the magnetic recording layer by a magnetic field generated by the current.
    Type: Grant
    Filed: November 5, 2004
    Date of Patent: May 30, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuya Kishi, Minoru Amano, Yoshiaki Saito, Shigeki Takahashi, Katsuya Nishiyama, Yoshiaki Asao, Hiroaki Yoda, Tomomasa Ueda, Yoshihisa Iwata
  • Magnetic random access memory
    Patent number: 7054189
    Abstract: Blocks are connected to a read bit line. One block has MTJ elements which are connected to each other in series between the read bit line and a ground terminal. A MTJ elements are superposed on, e.g., a semiconductor substrate. A read bit line is arranged on the superposed MTJ elements. A write word line extending in a X-direction and a write bit line extending in a Y-direction are arranged in the vicinity of the MTJ elements in the block.
    Type: Grant
    Filed: June 8, 2005
    Date of Patent: May 30, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshihisa Iwata
  • Magnetic random access memory
    Patent number: 7050325
    Abstract: In a magnetic random access memory (MRAM), setting data which determines the supply/cutoff timing, magnitude, and temporal change (current waveform) of a write word/bit line current is registered in a setting circuit. A write current waveform control circuit generates a write word line drive signal, write word line sink signal, write bit line drive signal, and write bit line sink signal on the basis of the setting data. The current waveform of the write word/bit line current is controlled for each chip or memory cell array.
    Type: Grant
    Filed: May 15, 2003
    Date of Patent: May 23, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshihisa Iwata, Kentaro Nakajima
  • Read circuit of semiconductor memory
    Publication number: 20060092734
    Abstract: A read circuit of a semiconductor memory according to the present invention is based on a self-reference sensing technique by which data stored in a memory cell is determined by first and second signals read out from a memory cell through first and second read operations. This read circuit includes a sense amplifier which determines the data stored in the memory cell based on a potential of an input node, a transfer transistor which is connected between the memory cell and the input node, a precharge circuit which sets the input node to a precharge potential, and a VBIAS generator which turns the transfer transistor cutoff based on the first signal.
    Type: Application
    Filed: December 20, 2004
    Publication date: May 4, 2006
    Inventors: Kenji Tsuchida, Junichi Miyamoto, Yoshihisa Iwata
  • Magnetic random access memory
    Publication number: 20060092692
    Abstract: Setting data which determines the supply/cutoff timing, magnitude, and temporal change (current waveform) of a write word/bit line current is registered in a setting circuit. A write current waveform control circuit generates a write word line drive signal, write word line sink signal, write bit line drive signal, and write bit line sink signal on the basis of the setting data. The current waveform of the write word/bit line current is controlled for each chip or memory cell array.
    Type: Application
    Filed: December 19, 2005
    Publication date: May 4, 2006
    Inventors: Yoshihisa Iwata, Kentaro Nakajima
  • Semiconductor memory device having memory cells including ferromagnetic films and control method thereof
    Patent number: 7035137
    Abstract: A semiconductor memory device comprises word lines, bit lines, memory cells, a row decoder, a column decoder, and a write circuit. The word lines are formed along a first direction. The bit lines are formed along a second direction. Memory cells include magneto-resistive elements and are arranged at intersections of the word lines and the bit lines. The row decoder selects at least one of the word lines. The column decoder selects at least one of the bit lines. The write circuit supplies first and second write currents to a selected word line and selected bit line respectively and writes data into a selected memory cell arranged at the intersection of the selected word line and the selected bit line. The write circuit changes the current values of the first and second write currents according to a temperature change.
    Type: Grant
    Filed: March 24, 2004
    Date of Patent: April 25, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshihisa Iwata, Kentaro Nakajima, Masayuki Sagoi, Yuui Shimizu
  • Magnetic random access memory
    Patent number: 7031184
    Abstract: In the first read operation, a read current is supplied to TMR elements connected in parallel in one column or one block to detect initial data. Trial data is then written in a selected memory cell. At the same time of or in parallel with writing of the trial data, the second read operation is performed. In the second read operation, a read current is supplied to the TMR elements connected in parallel in one column or one block to read comparison data. Subsequently, the initial data is compared with the comparison data to determine the data value in the selected memory cell. Finally, rewrite operation is performed for the selected memory cell.
    Type: Grant
    Filed: September 14, 2004
    Date of Patent: April 18, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshihisa Iwata
  • Magnetic random access memory
    Patent number: 7027325
    Abstract: A magnetic random access memory according to examples of the present invention comprises a magneto resistive element MTJ, and current source circuits I1, I2 and I3 which give a bias current/voltage to the magneto resistive element MTJ when data in the magneto resistive element MTJ is read, wherein a value of the bias current/voltage changes depending on temperature without depending on a power supply potential.
    Type: Grant
    Filed: July 14, 2004
    Date of Patent: April 11, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshihisa Iwata
  • Semiconductor memory
    Publication number: 20060067149
    Abstract: A semiconductor memory comprises a memory cell, a pair of reference cells for use in generation of a reference electric potential, a first read circuit which compares a read electric potential obtained from the memory cell with the reference electric potential and determines data in the memory cell, a second read circuit which detects a state of the pair of reference cells and outputs a detection signal indicating the state of the pair of reference cells, and a control circuit which controls a write operation for the pair of reference cells based on the detection signal.
    Type: Application
    Filed: March 21, 2005
    Publication date: March 30, 2006
    Inventors: Yuui Shimizu, Yoshihisa Iwata, Kenji Tsuchida
  • Magnetic memory device
    Publication number: 20060056217
    Abstract: A magnetic memory device includes a memory cell array including MTJ elements provided at the coordinates (x, y). First write lines extend in a direction neither perpendicular nor parallel to the magnetization easy axis direction of the MTJ elements. One and the other end of one first write line pass an upper or lower periphery of the memory cell array and a left or right periphery of the memory cell array, respectively. The first write lines and second write lines sandwich the MTJ elements. First write line drivers are connected to both ends of the first write lines, one and the other end of a pair of the first write line drivers connected to ends of one first write lines are located outside the upper or lower periphery and outside the left or right periphery, respectively. Second write line drivers are connected to both ends of the second write lines.
    Type: Application
    Filed: December 16, 2004
    Publication date: March 16, 2006
    Inventors: Ryousuke Takizawa, Junichi Miyamoto, Yoshihisa Iwata
  • Magnetic memory device and method of reading information
    Patent number: 7006374
    Abstract: A memory cell of a magnetic memory device has an MTJ element and one end of the memory cell is selectively electrically connected to a ground potential line. A first bit line is electrically connected to the other end of the memory cell. A sense amplifier amplifies a difference in potential between the first bit line and a second bit line complementary to the first bit line so that the difference is equal to or larger than a difference between an internal power potential and a ground potential. A connection circuit disconnects the MTJ element from an electric connection between the ground potential line and the sense amplifier.
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: February 28, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryousuke Takizawa, Kenji Tsuchida, Yoshihisa Iwata, Tsuneo Inaba
  • Magnetic random access memory
    Patent number: 7006372
    Abstract: In the first read operation, a read current is supplied to TMR elements connected in parallel in one column or one block to detect initial data. Trial data is then written in a selected memory cell. At the same time of or in parallel with writing of the trial data, the second read operation is performed. In the second read operation, a read current is supplied to the TMR elements connected in parallel in one column or one block to read comparison data. Subsequently, the initial data is compared with the comparison data to determine the data value in the selected memory cell. Finally, rewrite operation is performed for the selected memory cell.
    Type: Grant
    Filed: September 14, 2004
    Date of Patent: February 28, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshihisa Iwata