Abstract: A control circuit, on selecting a memory cell as a selected memory cell to perform a write operation, before executing the write operation, applies a first voltage to the selected memory cell via a first line and a second line to perform a first read operation. The control circuit, when judged that a result of the first read operation does not match write data intended to be written, executes the write operation. The control circuit, when judged that a result of the first read operation matches write data intended to be written, omits a voltage application operation for the write operation. The first voltage is larger than a second voltage which is applied to the selected memory cell via the first line and the second line in a second read operation, the second read operation acting as a normal read operation for reading held data of the memory cell.

Abstract: A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.

Abstract: A semiconductor device comprises a stacked layer memory block and associated peripheral circuits, such as a booster circuit, in stacked layer arrangements. The booster circuit includes plural rectifier cells that are series-connected and plural first capacitors. The plural first capacitors receive a first clock signal on one end, and the other ends thereof are each connected to one end of a different rectifier cell. Each first capacitor is composed of plural first conductive layers that are arrayed with a set pitch perpendicular to the substrate. Either the even numbered or the odd numbered first conductive layers are supplied with the first clock signal. The other of the even numbered or odd numbered first conductive layers are each individually connected to one end of a different rectifier cell.

Abstract: A memory cell array comprises first wiring lines, second wiring lines, and memory cells disposed at intersections thereof. A control circuit comprises a first power-supply line supplying a first voltage to selected ones of the first or second wiring lines, and first selection circuits connected between the first or second wiring lines and the first power-supply line, each first selection circuit comprising first and second transistors connected in series. The first selection circuits arranged along a first direction are connected to a first selection line. The first selection circuits arranged along a second direction perpendicular to the first direction are commonly connected to a second selection line. The first and second transistors each comprise a columnar semiconductor portion extending in a direction perpendicular to a semiconductor substrate, a gate-insulating film in contact with a side surface of the columnar semiconductor, and a gate electrode in contact with the gate-insulating film.

Abstract: According to one embodiment, provided is a semiconductor storage device that includes a control circuit to control the voltage that is applied to the memory cell. The control circuit is configured to execute a reset operation that applies a reset voltage of a first polarity to a selected memory cell that is connected to a selected first wire and a selected second wire during a reset operation. The control circuit is configured to execute a cancel operation that applies a cancel voltage of a second polarity that is opposite to the first polarity to an unselected memory cell and at the same time can execute a verify operation that reads out the state of the selected memory cell by applying a readout voltage of the second polarity to the selected memory cell. The cancel voltage and the readout voltage are the same voltage value.

Abstract: According to one embodiment, provided is a semiconductor storage device that includes a control circuit to control the voltage that is applied to the memory cell. The control circuit is configured to execute a reset operation that applies a reset voltage of a first polarity to a selected memory cell that is connected to a selected first wire and a selected second wire during a reset operation. The control circuit is configured to execute a cancel operation that applies a cancel voltage of a second polarity that is opposite to the first polarity to an unselected memory cell and at the same time can execute a verify operation that reads out the state of the selected memory cell by applying a readout voltage of the second polarity to the selected memory cell. The cancel voltage and the readout voltage are the same voltage value.

Abstract: A semiconductor memory device comprises: a plurality of first lines; a plurality of second lines extending to intersect the first lines; a plurality of memory cells disposed respectively at intersections of the first and second lines and including a variable resistance element; and a control circuit configured to control a voltage applied to the memory cell. The control circuit is configured able to, during a setting operation that changes the memory cell to a set state, execute the setting operation such that a setting voltage is applied to a selected memory cell connected to a selected first line and a selected second line. The control circuit is configured able to change a voltage application time of the setting voltage according to a state of change of the selected memory cell during the setting operation to execute an additional setting operation that applies the setting voltage to the selected memory cell.

Abstract: A magnetic memory device includes a magnetic thin wire including magnetic domains along a direction in which the magnetic thin wire extends. Magnetization directions of the magnetic domains are variable. A magnetic tunnel junction (MTJ) structure includes a pinned layer with a fixed magnetization direction and an insulator, and makes an MTJ including the pinned layer and insulator and a magnetic domain in the magnetic thin wire in a first position to sandwich the insulator with pinned layer. First and second electrodes are at both ends of the magnetic thin wire. At least one third electrode is coupled to the magnetic thin wire between the first and second electrodes.

Abstract: In a nonvolatile semiconductor memory device, a stacked body is formed by alternately stacking dielectric films and conductive films on a silicon substrate and a plurality of through holes extending in the stacking direction are formed in a matrix configuration. A shunt interconnect and a bit interconnect are provided above the stacked body. Conductor pillars are buried inside the through holes arranged in a line immediately below the shunt interconnect out of the plurality of through holes, and semiconductor pillars are buried inside the remaining through holes. The conductive pillars are formed from a metal, or low resistance silicon. Its upper end portion is connected to the shunt interconnect and its lower end portion is connected to a cell source formed in an upper layer portion of the silicon substrate.

Abstract: A control circuit is configured to set a drain-side select transistor and a source-side select transistor connected to a selected memory string to non-conductive states. The control circuit is configured to apply a first voltage to a non-selected word line connected to a gate of a non-selected memory cell in the selected memory string. The control circuit is configured to apply a second voltage to a selected word line connected to a gate of a selected memory cell in the selected memory string. The second voltage is smaller than the first voltage in an erasing operation.

Abstract: A semiconductor storage device has a nonvolatile storage region, a voltage generating circuit that generates an operational voltage for the storage region, and a control circuit that sends the voltage generated by the voltage generating circuit to the storage region. The voltage generating circuit has a transistor, a first resistance element, a second resistance element, and a comparator. The first resistance element and the second resistance element have wiring structure for resistance. The resistance wiring in the wiring structure has the same line width as the finest line width in the wiring formed in the storage region.

Abstract: In a nonvolatile semiconductor memory device, a stacked body is formed by alternately stacking dielectric films and conductive films on a silicon substrate and a plurality of through holes extending in the stacking direction are formed in a matrix configuration. A shunt interconnect and a bit interconnect are provided above the stacked body. Conductor pillars are buried inside the through holes arranged in a line immediately below the shunt interconnect out of the plurality of through holes, and semiconductor pillars are buried inside the remaining through holes. The conductive pillars are formed from a metal, or low resistance silicon. Its upper end portion is connected to the shunt interconnect and its lower end portion is connected to a cell source formed in an upper layer portion of the silicon substrate.

Abstract: A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.

Abstract: A non-volatile semiconductor memory device includes first through third memory strings, a first word line group shared by first and second memory strings and a second word line group shared by second and third memory strings, the first and second word line groups extending in a first direction and disposed adjacent to each other in a second direction that is perpendicular to the first direction. The first word line group includes laminated first word lines with each upper first word line extending in the first direction less than the first word line directly below, and the second word line group includes laminated second word lines with each upper second word line extending in the first direction less than the second word line directly below.

Abstract: A control circuit, on selecting a memory cell as a selected memory cell to perform a write operation, before executing the write operation, applies a first voltage to the selected memory cell via a first line and a second line to perform a first read operation. The control circuit, when judged that a result of the first read operation does not match write data intended to be written, executes the write operation. The control circuit, when judged that a result of the first read operation matches write data intended to be written, omits a voltage application operation for the write operation. The first voltage is larger than a second voltage which is applied to the selected memory cell via the first line and the second line in a second read operation, the second read operation acting as a normal read operation for reading held data of the memory cell.

Abstract: According to one embodiment, provided is a semiconductor storage device that includes a control circuit to control the voltage that is applied to the memory cell. The control circuit is configured to execute a reset operation that applies a reset voltage of a first polarity to a selected memory cell that is connected to a selected first wire and a selected second wire during a reset operation. The control circuit is configured to execute a cancel operation that applies a cancel voltage of a second polarity that is opposite to the first polarity to an unselected memory cell and at the same time can execute a verify operation that reads out the state of the selected memory cell by applying a readout voltage of the second polarity to the selected memory cell. The cancel voltage and the readout voltage are the same voltage value.

Abstract: According to one embodiment, a programmable logic switch includes first and second word lines above a first path transistor, a first pillar passing through the first and second word lines and connected to the first path transistor, a second pillar passing through the first and second word lines and connected to the first path transistor, a first memory device between the first pillar and the first word line, a second memory device between the first pillar and the second word line, a third memory device between the second pillar and the first word line, and a fourth memory device between the second pillar and the second word line.

Abstract: A memory cell array comprises first wiring lines, second wiring lines, and memory cells disposed at intersections thereof. A control circuit comprises a first power-supply line supplying a first voltage to selected ones of the first or second wiring lines, and first selection circuits connected between the first or second wiring lines and the first power-supply line, each first selection circuit comprising first and second transistors connected in series. The first selection circuits arranged along a first direction are connected to a first selection line. The first selection circuits arranged along a second direction perpendicular to the first direction are commonly connected to a second selection line. The first and second transistors each comprise a columnar semiconductor portion extending in a direction perpendicular to a semiconductor substrate, a gate-insulating film in contact with a side surface of the columnar semiconductor, and a gate electrode in contact with the gate-insulating film.

Abstract: A control circuit is configured to set a drain-side select transistor and a source-side select transistor connected to a selected memory string to non-conductive states. The control circuit is configured to apply a first voltage to a non-selected word line connected to a gate of a non-selected memory cell in the selected memory string. The control circuit is configured to apply a second voltage to a selected word line connected to a gate of a selected memory cell in the selected memory string. The second voltage is smaller than the first voltage in an erasing operation.

Abstract: A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.