Abstract: A non-volatile semiconductor storage device includes: a memory string including a plurality of memory cells connected in series; a first selection transistor having one end connected to one end of the memory string; a first wiring having one end connected to the other end of the first selection transistor; a second wiring connected to a gate of the first selection transistor. A control circuit is configured to boost voltages of the second wiring and the first wiring in the erase operation, while keeping the voltage of the first wiring greater than the voltage of the second wiring by a certain potential difference. The certain potential difference is a potential difference that causes a GIDL current.

Abstract: A nonvolatile semiconductor memory device comprises: a plurality of first memory strings; a first select transistor having one end thereof connected to one end of the first memory strings; a first line commonly connected to the other end of a plurality of the first select transistors; a switch circuit having one end thereof connected to the first line; and a second line commonly connected to the other end of a plurality of the switch circuits. The switch circuit controls electrical connection between the second line and the first line.

Abstract: An dielectric film is formed above the semiconductor substrate. A first conductive layer is formed in the dielectric film and extending in a first direction. The first conductive layer is connected to a first select transistor. A second conductive layer formed in the dielectric film and extending in the first direction. The second conductive layer is connected to a second select transistor. A semiconductor layer is connected to both the first and second conductive layers and functioning as a channel layer of a memory transistor. A gate-insulating film is formed on the semiconductor layer. The gate-insulating film includes a charge accumulation film as a portion thereof. A third conductive layer is surrounded by the gate-insulating film.

Abstract: A memory string is configured by a plurality of memory transistors and a spare memory transistor connected in series. Word lines are connected to gates of the memory transistors. A spare word line is connected to a gate of the spare memory transistor. The memory string comprises a first semiconductor layer, a charge storage layer, a plurality of first conductive layers, and a second conductive layer. The first semiconductor layer extends in a perpendicular direction with respect to a substrate. The charge storage layer surrounds a side surface of the first semiconductor layer. The plurality of first conductive layers surround a side surface of the first semiconductor layer with the charge storage layer interposed therebetween, and function as the word lines. The second conductive layer surrounds a side surface of the first semiconductor layer with the charge storage layer interposed therebetween, and functions as the spare word line.

Abstract: In a nonvolatile semiconductor memory device, a stacked body is formed by alternately stacking dielectric films and conductive films on a silicon substrate and a plurality of through holes extending in the stacking direction are formed in a matrix configuration. A shunt interconnect and a bit interconnect are provided above the stacked body. Conductor pillars are buried inside the through holes arranged in a line immediately below the shunt interconnect out of the plurality of through holes, and semiconductor pillars are buried inside the remaining through holes. The conductive pillars are formed from a metal, or low resistance silicon. Its upper end portion is connected to the shunt interconnect and its lower end portion is connected to a cell source formed in an upper layer portion of the silicon substrate.

Abstract: A semiconductor memory device includes a memory cell array having a plurality of memory cells which are set into low-resistance states/high-resistance states according to “0” data/“1” data. An allocation of the “0” data/“1” data and the low-resistance state/high-resistance state is switched when a power source is turned on.

Abstract: A nonvolatile semiconductor memory device comprises: a memory cell array having a plurality of memory strings each having a plurality of memory cells connected in series; and a control circuit configured to execute a read operation for reading data from the memory cells included in a selected memory string from among the plurality of memory strings. During the read operation, the control circuit is configured to apply a first voltage to a gate of at least one of the memory cells in a non-selected memory string not subject to the read operation, and apply a second voltage lower than the first voltage to a gate of another of the memory cells in the non-selected memory string not subject to the read operation.

Abstract: In a nonvolatile semiconductor memory device, a stacked body is formed by alternately stacking dielectric films and conductive films on a silicon substrate and a plurality of through holes extending in the stacking direction are formed in a matrix configuration. A shunt interconnect and a bit interconnect are provided above the stacked body. Conductor pillars are buried inside the through holes arranged in a line immediately below the shunt interconnect out of the plurality of through holes, and semiconductor pillars are buried inside the remaining through holes. The conductive pillars are formed from a metal, or low resistance silicon. Its upper end portion is connected to the shunt interconnect and its lower end portion is connected to a cell source formed in an upper layer portion of the silicon substrate.

Abstract: According to one embodiment, in the case of performing an operation for increasing a threshold voltage of a first transistor or a third transistor, a control circuit is configured to apply a first voltage to a bit line, and apply a second voltage greater than the first voltage to a gate of a second transistor, thereby rendering the second transistor in a conductive state to transfer the first voltage to a second semiconductor layer, and then apply a program voltage to a gate of the first transistor or the third transistor to store a charge in a second charge storage layer.

Abstract: Each of the memory blocks includes: a first conductive layer expanding in parallel to the substrate over the first area, n layers of the first conductive layers being formed in a lamination direction and shared by the plurality of memory strings; a first semiconductor layer; and an electric charge accumulation layer. The memory strings are arranged with m columns in a second direction for each of the memory blocks. The wiring layers are arranged in the second direction, formed to extend to the vicinity of one end of the first conductive layer in the first direction from one side of the memory block, and connected via contact plugs to the first conductive layers.

Abstract: A control circuit is configured to erase a selected block in the erase operation by applying a predetermined potential to the source-line and the third conductive layer to generate a current to increase a potential of the first columnar semiconductor layer and by providing a first voltage to the first conductive layer. The control circuit is configured to keep first conductive layers at a floating state during the first period, while during the second period after the first period, to switch the first conductive layers from the floating state to a state in which the conductive layer is charged to a second voltage higher than the first voltage, in an unselected block in the erase operation.

Abstract: A nonvolatile semiconductor memory device comprises a cell array having plural memory cells arranged in matrix, each memory cell including a variable resistor having a resistance reversibly variable to store data corresponding to the resistance of the variable resistor; a selection circuit operative to select a memory cell from the cell array; and a write circuit operative to execute certain voltage or current supply to the memory cell selected by the selection circuit to vary the resistance of a variable resistor in the selected memory cell to erase or write data. The write circuit terminates the voltage or current supply to the selected memory cell in accordance with resistance variation situation of the variable resistor in the selected memory cell when current flowing in the selected memory cell reaches a certain level appeared after the data erase or write.

Abstract: Memory strings includes: a first semiconductor layer including a columnar portion extending in a direction perpendicular to a substrate; a first electric charge storage layer formed to surround a side surface of the columnar portion; and a first conductive layer formed to surround the first electric charge storage layer. First selection transistors includes: a second semiconductor layer extending upward from a top surface of the columnar portion; a second electric charge storage layer formed to surround a side surface of the second semiconductor layer; and a second conductive layer formed to surround the second electric charge storage layer. The non-volatile semiconductor storage device further includes a control circuit that causes, prior to reading data from a selected one of the memory strings, electric charges to be accumulated in the second electric charge storage layer of one of the first selection transistors connected to an unselected one of the memory strings.

Abstract: A nonvolatile semiconductor memory device comprises: a memory cell array having a plurality of memory strings each having a plurality of memory cells connected in series; and a control circuit configured to execute a read operation for reading data from the memory cells included in a selected memory string from among the plurality of memory strings. During the read operation, the control circuit is configured to apply a first voltage to a gate of at least one of the memory cells in a non-selected memory string not subject to the read operation, and apply a second voltage lower than the first voltage to a gate of another of the memory cells in the non-selected memory string not subject to the read operation.

Abstract: A nonvolatile semiconductor memory device comprises: a plurality of first memory strings; a first select transistor having one end thereof connected to one end of the first memory strings; a first line commonly connected to the other end of a plurality of the first select transistors; a switch circuit having one end thereof connected to the first line; and a second line commonly connected to the other end of a plurality of the switch circuits. The switch circuit controls electrical connection between the second line and the first line.

Abstract: A magnetic memory device includes a first magnetic line which has a plurality of cells made of magnetic domains partitioned by domain walls, and in which information is recorded in each cell, a first write element formed at one end portion of the first magnetic line, and a first read element formed at the other end portion of the first magnetic line.

Abstract: A magnetoresistive effect memory of an aspect of the present invention including a magnetoresistive effect element including a first magnetic layer having an invariable magnetization direction, a second magnetic layer having a variable magnetization direction, and an interlayer provided between the first magnetic layer and the second magnetic layer, and a reading circuit which passes a pulse-shaped read current through the magnetoresistive effect element to read data stored in the magnetoresistive effect element, wherein the pulse width of the read current is shorter than a period from an initial state to a cooperative coherent precession movement of magnetizations included in the second magnetic layer.

Abstract: When a data erase operation is performed in one memory cell block, a first voltage is applied to one source line selected from m source lines in the one memory cell block. A second voltage equal to a voltage of the source lines before the data erase operation begins is applied to the other source lines. Then, after a certain time delay from application of the first voltage, a third voltage smaller than the first voltage is applied to a third conductive layer of a source-side selection transistor connected to a selected source line. Then, a hole current is produced near a third gate insulation layer due to a potential difference between the first and third voltage. A fourth voltage is applied to one of first conductive layers connected to one of the memory transistor to be erased. The other first conductive layers are brought into a floating state.

Abstract: A sense amplifier according to an example of the present invention has first, second, third and fourth FETs with a flip-flop connection. A drain of a fifth FET is connected to a first input node, and its source is connected to a power source node. A drain of a sixth FET is connected to a second input node, and its source is connected to the power source node. A sense operation is started by charging a first output node from the first input node with a first current and by charging a second output node from the second input node with a second current. The fifth and sixth FET are turned on after starting the sense operation.

Abstract: A non-volatile semiconductor storage device includes a control circuit performing an erase operation to erase data from a selected one of memory transistors. The control circuit applies a first voltage to the other end of selected one of selection transistors, causes the selected one of the selection transistors to turn on, and causes any one of the memory transistors to turn on that is closer to the selection transistor than the selected one of the memory transistors. The control circuit also applies a second voltage lower than the first voltage to a gate of the selected one of the memory transistors. Such a potential difference between the first voltage and the second voltage causing a change in electric charges in the electric charge storage layer.