Patents by Inventor Yoshihisa Kojima

Yoshihisa Kojima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory system and nonvolatile memory
    Patent number: 10910068
    Abstract: A memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes memory cells at intersection locations of stacked word lines and a memory pillar passing through the word lines in a stacking direction, the word lines including a first group of word lines stacked above a second group of word lines. The controller reads data of a first memory cell in a first read mode and reads data of a second memory cell in a second read mode. The first memory cell is, and the second memory cell is not, at an intersection location of a word line that is in a boundary area of the first and second groups of word lines and the memory pillar. The boundary area is adjacent to a location of the memory pillar where a width of the memory pillar discontinuously changes along the stacking direction.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: February 2, 2021
    Assignee: KIOXIA CORPORATION
    Inventors: Kazutaka Takizawa, Yoshihisa Kojima, Masaaki Niijima
  • Air-conditioner remote controller and air-conditioning control system
    Patent number: 10895395
    Abstract: An air-conditioner remote controller in an air conditioner system that includes the air-conditioner remote controller and an air conditioner that performs air-conditioning control using room temperature information received from the air-conditioner remote controller, includes: a storage unit to store room temperature information that is information on room temperature measured by a plurality of temperature sensors and store schedule information that sets, for each time zone, a temperature sensor to measure a room temperature to be used as room temperature information in the air-conditioning control of the air conditioner; and a control unit to perform control such that the room temperature information from the set temperature sensor is acquired from the storage unit and the acquired room temperature information is transmitted to the air conditioner in accordance with the schedule information.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: January 19, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yoshihisa Kojima, Yoshiaki Koizumi, Hidetoshi Muramatsu
  • MEMORY SYSTEM INCLUDING A SEMICONDUCTOR MEMORY HAVING A MEMORY CELL AND A WRITE CIRCUIT CONFIGURED TO WRITE DATA TO THE MEMORY CELL
    Publication number: 20210005264
    Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory, and a controller. The semiconductor memory includes a memory cell, and a write circuit configured to write data to the memory cell by applying a program voltage to the memory cell and comparing a threshold voltage of the memory cell with a first reference voltage corresponding to the write data. The write circuit is configured to execute a first programming operation to obtain a value of a write parameter by comparing the threshold voltage with a second reference voltage different from the first reference voltage.
    Type: Application
    Filed: September 21, 2020
    Publication date: January 7, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Suguru NISHIKAWA, Yoshihisa KOJIMA, Riki SUZUKI, Masanobu SHIRAKAWA, Toshikatsu HIDA
  • MEMORY SYSTEM
    Publication number: 20210004169
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller electrically connected to the nonvolatile memory. The controller selects a write mode from a first mode in which data having N bits is written per one memory cell and a second mode in which data having M bits is written per one memory cell. N is equal to or larger than one. M is larger than N. The controller writes data into the nonvolatile memory in the selected write mode. The controller selects either the first mode or the second mode at least based on a total number of logical addresses mapped in a physical address space of the nonvolatile memory.
    Type: Application
    Filed: September 22, 2020
    Publication date: January 7, 2021
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Shunichi Igahara, Toshikatsu Hida, Riki Suzuki, Takehiko Amaki, Suguru Nishikawa, Yoshihisa Kojima
  • NONVOLATILE MEMORY AND MEMORY SYSTEM
    Publication number: 20200402596
    Abstract: According to one embodiment, a nonvolatile memory includes: a memory cell array including memory cells; and a controller configured to execute a first refresh process on receiving a first command. The first refresh process includes reprogramming at least one second memory cell among first memory cells to which data has been programmed in a first group. In executing the first refresh process, the controller is configured to: select the second memory cell by verifying with a first voltage using a first amount in a case where the second memory cell has been programmed using the first voltage; and select the second memory cell by verifying with a second voltage using a second amount in a case where the second memory cell has been programmed using the second voltage.
    Type: Application
    Filed: August 31, 2020
    Publication date: December 24, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Riki Suzuki, Masanobu Shirakawa, Yoshihisa Kojima, Marie Takada, Tsukasa Tokutomi
  • MEMORY SYSTEM FOR RESTRAINING THRESHOLD VARIATION TO IMPROVE DATA READING
    Publication number: 20200402581
    Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes: first memory cells, first word lines, a first row decoder, and a driver circuit. The first row decoder includes first transistors capable of coupling the first word lines to first signal lines, and a first block decoder supplying a first block selection signal to the first transistors. When the controller issues a data read command, the first block decoder asserts the first block selection signal to allow the first transistors to transfer a first voltage to a selected first word line, and a second voltage to unselected other first word lines. After data is read, the first block decoder continues asserting the first block selection signal, and the driver circuit transfers a third voltage.
    Type: Application
    Filed: September 8, 2020
    Publication date: December 24, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Masanobu SHIRAKAWA, Marie TAKADA, Tsukasa TOKUTOMI, Yoshihisa KOJIMA, Kiichi TACHI
  • Memory system
    Patent number: 10871901
    Abstract: According to one embodiment, a memory system includes a memory and a memory controller. The memory includes a first buffer and a memory cell array. The memory controller includes a second buffer for receiving first data from a host. The memory controller transfers the first data to the first buffer without accumulating a predetermined size of the first data in the second buffer. The memory controller creates second data in the first buffer and programs the second data created in the first buffer into the memory cell array. The second data is formed of a plurality of third data. The third data is first data received from the memory controller by the memory. The size of the second data is equal to a size of a unit in which to program into the memory cell array.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: December 22, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Yoshihisa Kojima, Tatsuhiro Suzumura, Tokumasa Hara, Hiroyuki Moro, Yohei Hasegawa, Yoshiki Saito
  • MEMORY SYSTEM
    Publication number: 20200387425
    Abstract: A memory system includes a non-volatile memory and a controller that includes a toggle encoder configured to encode first data having a first bit length and a first number of toggles, into second data having a second bit length longer than the first bit length and a second number of toggles smaller than the first number of toggles, and transmit the second data to the non-volatile memory. The memory system may further include a toggle decoder configured to decode third data received from the non-volatile memory into fourth data, the third data having the second bit length and the second number of toggles and the fourth data having the first bit length and the first number of toggles.
    Type: Application
    Filed: January 28, 2020
    Publication date: December 10, 2020
    Inventors: Shunichi IGAHARA, Yoshihisa KOJIMA, Takehiko AMAKI, Suguru NISHIKAWA
  • MEMORY SYSTEM AND CONTROLLER
    Publication number: 20200371571
    Abstract: In a memory system in an embodiment, in a case of normal operation, a control unit returns a write completion response upon completion of reception of write data from a host, and writes the write data into nonvolatile memory in a multiple values. In a case of unordinary power-off, changeover to operation using a backup battery is conducted and the control unit writes dirty data that is not completed in writing into the nonvolatile memory, into the nonvolatile memory with two values. When next boot, the control unit reads the dirty data from the nonvolatile memory into the volatile memory, and thereafter writes the dirty data into the nonvolatile memory in a multiple values.
    Type: Application
    Filed: August 7, 2020
    Publication date: November 26, 2020
    Inventors: Yoshihisa Kojima, Katsuhiko Ueki
  • Memory system, control method, and control device
    Patent number: 10831395
    Abstract: According to one embodiment, a memory system includes a memory and a controller electrically connected to the memory. The memory includes blocks. Each of the blocks includes one or more sub-blocks. Each of the one or more sub-blocks includes nonvolatile memory cells. The controller is configured to obtain read frequency of at least one of the sub-blocks, and move data stored in the at least one of the sub-blocks so that data having substantially the same read frequency are written into one block.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: November 10, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Riki Suzuki, Yoshihisa Kojima, Toshikatsu Hida
  • Memory system
    Patent number: 10824353
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller electrically connected to the nonvolatile memory. The controller selects a write mode from a first mode in which data having N bits is written per one memory cell and a second mode in which data having M bits is written per one memory cell. N is equal to or larger than one. M is larger than N. The controller writes data into the nonvolatile memory in the selected write mode. The controller selects either the first mode or the second mode at least based on a total number of logical addresses mapped in a physical address space of the nonvolatile memory.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: November 3, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Shunichi Igahara, Toshikatsu Hida, Riki Suzuki, Takehiko Amaki, Suguru Nishikawa, Yoshihisa Kojima
  • Memory device that controls timing of receiving write data from a host
    Patent number: 10824553
    Abstract: A memory device includes a nonvolatile memory unit, a write buffer, and a controller. The controller is configured to receive a write command from a host, send a permission signal to the host after the write command is received, receive write data associated with a write command from the host in response to the permission signal, store the write data in the write buffer, and transfer the write data stored in the write buffer to the nonvolatile memory unit. The controller controls a timing of transmitting the permission signal, such that the write buffer is full for no longer than a predetermined length of time.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: November 3, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yoshihisa Kojima
  • ALLOCATION OF MEMORY REGIONS OF A NONVOLATILE SEMICONDUCTOR MEMORY FOR STREAM-BASED DATA WRITING
    Publication number: 20200341654
    Abstract: A semiconductor storage device comprises a nonvolatile semiconductor memory with memory regions, threads, and a controller. Each thread includes a buffer region in which write data from a host are stored before the write data are written to one of the memory regions, and the buffer region of each thread is different from buffer regions of the other threads. The controller receives stream data from the host, each stream data being associated with one of multiple stream identifications, allocates each stream identification to one of the threads according to priority levels assigned to the stream identifications, such that a stream identification assigned a highest priority level is allocated to a thread to which none of other stream identifications are allocated, and writes each stream data stored in the buffer regions to one of the memory regions according to stream identification of the stream data.
    Type: Application
    Filed: July 13, 2020
    Publication date: October 29, 2020
    Inventors: Motohiro MATSUYAMA, Yoshihisa KOJIMA
  • Memory system including a semiconductor memory having a memory cell and a write circuit configured to write data to the memory cell
    Patent number: 10818358
    Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory, and a controller. The semiconductor memory includes a memory cell, and a write circuit configured to write data to the memory cell by applying a program voltage to the memory cell and comparing a threshold voltage of the memory cell with a first reference voltage corresponding to the write data. The write circuit is configured to execute a first programming operation to obtain a value of a write parameter by comparing the threshold voltage with a second reference voltage different from the first reference voltage.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: October 27, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Suguru Nishikawa, Yoshihisa Kojima, Riki Suzuki, Masanobu Shirakawa, Toshikatsu Hida
  • MEMORY SYSTEM CHIP THAT SUSPENDS TRANSFER PHASE AND RESUMES TRANSFER PHASE
    Publication number: 20200326862
    Abstract: According to one embodiment, a memory system includes a non-volatile memory and a controller. The memory includes a memory cell array. The controller is configured to control a transfer phase in which a command, an address, and first data are transferred to the memory, and a program phase in which the first data is programmed into the memory cell array by the memory after the transfer phase. The controller is configured to suspend the transfer phase after initiating the transfer phase before completion of the transfer phase, then read second data from the memory, and resume the transfer phase after reading of the second data is completed.
    Type: Application
    Filed: June 26, 2020
    Publication date: October 15, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Shizuka ENDO, Riki SUZUKI, Yoshihisa KOJIMA
  • Memory system for restraining threshold variation to improve data reading
    Patent number: 10803953
    Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes: first memory cells, first word lines, a first row decoder, and a driver circuit. The first row decoder includes first transistors capable of coupling the first word lines to first signal lines, and a first block decoder supplying a first block selection signal to the first transistors. When the controller issues a data read command, the first block decoder asserts the first block selection signal to allow the first transistors to transfer a first voltage to a selected first word line, and a second voltage to unselected other first word lines. After data is read, the first block decoder continues asserting the first block selection signal, and the driver circuit transfers a third voltage.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: October 13, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Masanobu Shirakawa, Marie Takada, Tsukasa Tokutomi, Yoshihisa Kojima, Kiichi Tachi
  • Memory system including a memory controller and error correction circuit for reading multi-bit data and for detecting and correcting read data errors
    Patent number: 10803930
    Abstract: According to one embodiment, a memory system comprising includes a semiconductor memory and a memory controller. The memory controller is configured to obtain first data read from the semiconductor memory using a first voltage, obtain second data read from the semiconductor memory using a second voltage, calculate a first value for a first section of the first data using the first data and the second data, calculate a second value for a second section of the first data using the first data and the second data, calculate a third value for a third section of the first data using the first data and the second data, and correct an error of the first data using the first to third values.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: October 13, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Masahiro Kiyooka, Yoshihisa Kojima, Toshikatsu Hida
  • Nonvolatile memory and memory system
    Patent number: 10796776
    Abstract: According to one embodiment, a nonvolatile memory includes: a memory cell array including memory cells; and a controller configured to execute a first refresh process on receiving a first command. The first refresh process includes reprogramming at least one second memory cell among first memory cells to which data has been programmed in a first group. In executing the first refresh process, the controller is configured to: select the second memory cell by verifying with a first voltage using a first amount in a case where the second memory cell has been programmed using the first voltage; and select the second memory cell by verifying with a second voltage using a second amount in a case where the second memory cell has been programmed using the second voltage.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: October 6, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Riki Suzuki, Masanobu Shirakawa, Yoshihisa Kojima, Marie Takada, Tsukasa Tokutomi
  • MEMORY SYSTEM
    Publication number: 20200301611
    Abstract: A memory system includes a non-volatile memory chip that includes a memory cell array, and a memory controller. The memory controller is configured to perform a read operation on the non-volatile memory chip by instructing the non-volatile memory chip to perform a sensing operation to read data stored in the memory cell array, estimating a time when the read data becomes ready to be transferred from the non-volatile memory chip to the memory controller, and instructing the non-volatile memory chip, after the estimated time, to perform a transfer operation to transfer the read data to the memory controller.
    Type: Application
    Filed: August 30, 2019
    Publication date: September 24, 2020
    Inventors: Marie SIA, Yoshihisa KOJIMA, Suguru NISHIKAWA, Riki SUZUKI
  • MEMORY SYSTEM AND NONVOLATILE MEMORY
    Publication number: 20200303018
    Abstract: A memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes memory cells at intersection locations of stacked word lines and a memory pillar passing through the word lines in a stacking direction, the word lines including a first group of word lines stacked above a second group of word lines. The controller reads data of a first memory cell in a first read mode and reads data of a second memory cell in a second read mode. The first memory cell is, and the second memory cell is not, at an intersection location of a word line that is in a boundary area of the first and second groups of word lines and the memory pillar. The boundary area is adjacent to a location of the memory pillar where a width of the memory pillar discontinuously changes along the stacking direction.
    Type: Application
    Filed: December 26, 2019
    Publication date: September 24, 2020
    Inventors: Kazutaka TAKIZAWA, Yoshihisa KOJIMA, Masaaki NIIJIMA