Patents by Inventor Yoshihisa Kojima

Yoshihisa Kojima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory system including a non-volatile memory chip and method for performing a read operation on the non-volatile memory chip
    Patent number: 11099783
    Abstract: A memory system includes a non-volatile memory chip that includes a memory cell array, and a memory controller. The memory controller is configured to perform a read operation on the non-volatile memory chip by instructing the non-volatile memory chip to perform a sensing operation to read data stored in the memory cell array, estimating a time when the read data becomes ready to be transferred from the non-volatile memory chip to the memory controller, and instructing the non-volatile memory chip, after the estimated time, to perform a transfer operation to transfer the read data to the memory controller.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: August 24, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Marie Sia, Yoshihisa Kojima, Suguru Nishikawa, Riki Suzuki
  • SEMICONDUCTOR MEMORY MEDIUM AND MEMORY SYSTEM
    Publication number: 20210257027
    Abstract: According to one embodiment, the semiconductor memory medium includes a first memory cell, a first word line coupled to the first memory cell, and a row decoder coupled to the first word line. A write operation is executed multiple times on the first memory cell within a first period from after an execution of an erase operation to an execution of a next erase operation. The write operation includes at least one of program loops each including a program operation and a verify operation. In the verify operation, the row decoder applies a verify voltage to the first word line. The verify voltage is set in accordance with a number of executed write operations on the first memory cell within the first period.
    Type: Application
    Filed: September 11, 2020
    Publication date: August 19, 2021
    Applicant: Kioxia Corporation
    Inventors: Suguru NISHIKAWA, Takehiko AMAKI, Yoshihisa KOJIMA, Shunichi IGAHARA
  • Memory system
    Patent number: 11086718
    Abstract: A memory system includes a nonvolatile memory, a buffer, and a controller. The buffer can temporarily store a plurality of data bits to be written to the nonvolatile memory. The controller can write the plurality of data bits, read from the buffer, to the nonvolatile memory; write a plurality of intermediate parity bits to the buffer, but not to the nonvolatile memory, wherein each of the plurality of intermediate parity bits is associated with an error correction process on each of the plurality of data bits; and write, to the nonvolatile memory, an accumulated parity bit that is an integration of the plurality of intermediate parity bits.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: August 10, 2021
    Assignee: KIOXIA CORPORATION
    Inventors: Riki Suzuki, Toshikatsu Hida, Yoshihisa Kojima, Takehiko Amaki, Suguru Nishikawa
  • AIR CONDITIONER INTERFACE
    Publication number: 20210239349
    Abstract: An air conditioner interface is an interface to which an air conditioner, a manipulation terminal, and an external device are connected, the manipulation terminal being used by a user to manipulate the air conditioner, the external device having an air-conditioning function. The air conditioner interface includes a control unit that controls operation of the air conditioner and operation of the external device in accordance with an operating mode that is set to either a first operating mode to solely operate the air conditioner or a second operating mode to enable the air conditioner and the external device to operate simultaneously.
    Type: Application
    Filed: August 16, 2018
    Publication date: August 5, 2021
    Inventor: Yoshihisa KOJIMA
  • MEMORY SYSTEM
    Publication number: 20210241833
    Abstract: A memory system includes a non-volatile memory chip and a controller. The non-volatile memory chip is capable of determining an erase voltage according to a temperature of the non-volatile memory chip and a correction parameter. The controller is configured to update the correction parameter of the non-volatile memory chip according to temperature information related to the temperature of the non-volatile memory chip. The non-volatile memory chip determines the erase voltage according to the temperature of the non-volatile memory chip and the updated correction parameter received from the controller.
    Type: Application
    Filed: September 30, 2020
    Publication date: August 5, 2021
    Inventors: Kazutaka TAKIZAWA, Yoshihisa KOJIMA, Masaaki NIIJIMA
  • Nonvolatile memory including intermediate buffer and input/output buffer and memory system including the nonvolatile memory
    Patent number: 11068167
    Abstract: According to one embodiment, there is provided a nonvolatile memory including a memory cell array, an input/output buffer, one or more intermediate buffers, and a control circuit. The memory cell array includes a plurality of pages. Each of the one or more intermediate buffers is electrically connected between the memory cell array and the input/output buffer. The control circuit is configured to store, in a first intermediate buffer, data read through sensing operation from a first page out of the plurality of pages in accordance with a first command that includes a sensing operation instruction and designation of the first intermediate buffer among the one or more intermediate buffers.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: July 20, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Yoshihisa Kojima, Masanobu Shirakawa, Kiyotaka Iwasaki
  • Memory system and nonvolatile memory
    Patent number: 11069413
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller that controls operation of the nonvolatile memory. The nonvolatile memory is configured to receive, from the memory controller, a first command for execution of at least one of an erase operation and a program operation; in response to receiving a second command from the memory controller during execution of a first operation requested by the first command, execute a second operation for suspending the first operation before the first operation reaches a given section; and in response to receiving a third command from the memory controller during the execution of the first operation, suspend the first operation after the given section.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: July 20, 2021
    Assignee: Kioxia Corporation
    Inventors: Suguru Nishikawa, Riki Suzuki, Yoshihisa Kojima
  • MEMORY SYSTEM
    Publication number: 20210183877
    Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes blocks each containing memory cells. The controller is configured to instruct the semiconductor memory to execute a first operation and a second operation. In the first operation and the second operation, the semiconductor memory selects at least one of the blocks, and applies at least one voltage to all memory cells contained in said selected blocks. A number of blocks to which said voltage is applied per unit time in the second operation is larger than that in the first operation.
    Type: Application
    Filed: February 23, 2021
    Publication date: June 17, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Takehiko AMAKI, Yoshihisa KOJIMA, Toshikatsu HIDA, Marie Grace Izabelle Angeles SIA, Riki SUZUKI, Shohei ASAMI
  • Nonvolatile memory and memory system
    Patent number: 11004523
    Abstract: According to one embodiment, a nonvolatile memory includes: a memory cell array including memory cells; and a controller configured to execute a first refresh process on receiving a first command. The first refresh process includes reprogramming at least one second memory cell among first memory cells to which data has been programmed in a first group. In executing the first refresh process, the controller is configured to: select the second memory cell by verifying with a first voltage using a first amount in a case where the second memory cell has been programmed using the first voltage; and select the second memory cell by verifying with a second voltage using a second amount in a case where the second memory cell has been programmed using the second voltage.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: May 11, 2021
    Assignee: Toshiba Memory Coiporation
    Inventors: Riki Suzuki, Masanobu Shirakawa, Yoshihisa Kojima, Marie Takada, Tsukasa Tokutomi
  • Memory system
    Patent number: 11003356
    Abstract: A memory system includes a nonvolatile memory having memory blocks; and a controller configured to receive a request for writing user data from a host; select at least a first block having a first percentage of valid data among the memory blocks, determine a second percentage different from the first percentage on the basis of at least the first percentage of the valid data in the first block, determine a first ratio between a write amount of the user data in accordance with the request from the host and a write amount of the valid data in at least the first block on the basis of the second percentage determined, and write the user data and the valid data in the first block into the nonvolatile memory on the basis of the first ratio.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: May 11, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Tatsuya Zettsu, Yoshihisa Kojima
  • MEMORY SYSTEM
    Publication number: 20210124529
    Abstract: A memory system includes a memory device having a memory cell array, and a controller. The memory cell array includes a plurality of first units and at least one second unit. The second unit includes the plurality of first units. The controller counts a first number of times of read operation for each of the plurality of first units, and, in response to the first number of times for one first unit among the plurality of first units reaching a first value, updates a second number of times for the second unit that includes the one first unit. In response to the second number of times reaching a second value, the controller determines whether to rewrite data stored in at least one of the first units included in the second unit.
    Type: Application
    Filed: August 25, 2020
    Publication date: April 29, 2021
    Applicant: Kioxia Corporation
    Inventors: Suguru NISHIKAWA, Yoshihisa KOJIMA, Takehiko AMAKI
  • MEMORY SYSTEM, CONTROL METHOD THEREOF, AND PROGRAM
    Publication number: 20210110877
    Abstract: A memory system includes a nonvolatile memory configured to execute one of a plurality of read operations, including a first read operation and a second read operation, and a memory controller configured to issue a read command to the nonvolatile memory to cause the nonvolatile memory to execute one of the plurality of read operations. The memory controller is configured to receive a read request, estimate a reliability level of a result of a read operation to be executed by the nonvolatile memory to read data from a physical address specified in the read request, select one of the first and second read operations to be executed first in a read sequence corresponding to the read request by the nonvolatile memory based on the estimated reliability level, and instruct the nonvolatile memory to execute the selected read operation.
    Type: Application
    Filed: December 22, 2020
    Publication date: April 15, 2021
    Inventor: Yoshihisa KOJIMA
  • Memory system and non-volatile semiconductor memory
    Patent number: 10978165
    Abstract: According to one embodiment, a memory system includes a non-volatile semiconductor memory that includes a memory cell and a controller having a memory storing a write parameter used in a write operation to the memory cell. The controller instructs the non-volatile semiconductor memory to perform the write operation to the memory cell using the write parameter, receives, from the non-volatile semiconductor memory, a result of checking of the write parameter which is obtained in the write operation and updates the write parameter stored in the memory on the basis of the result of checking of the write parameter.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: April 13, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Suguru Nishikawa, Yoshihisa Kojima, Masanobu Shirakawa
  • Memory system
    Patent number: 10964712
    Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes blocks each containing memory cells. The controller is configured to instruct the semiconductor memory to execute a first operation and a second operation. In the first operation and the second operation, the semiconductor memory selects at least one of the blocks, and applies at least one voltage to all memory cells contained in said selected blocks. A number of blocks to which said voltage is applied per unit time in the second operation is larger than that in the first operation.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: March 30, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Takehiko Amaki, Yoshihisa Kojima, Toshikatsu Hida, Marie Grace Izabelle Angeles Sia, Riki Suzuki, Shohei Asami
  • MEMORY SYSTEM AND METHOD
    Publication number: 20210082528
    Abstract: According to one embodiment, a memory system includes a first memory and a memory controller. The first memory is nonvolatile and includes a plurality of memory cell transistors, each of which stores data corresponding to a threshold voltage. The memory controller causes the first memory to execute a read operation to acquire data corresponding to the threshold voltage from the plurality of memory cell transistors on the basis of a result of comparison between the threshold voltage and a read voltage. The memory controller selects a first candidate value from among a plurality of candidate values for the read voltage in accordance with a degree of stress that affects the threshold voltage; and causes the first memory to execute the read operation using the first candidate value as the read voltage.
    Type: Application
    Filed: March 12, 2020
    Publication date: March 18, 2021
    Applicant: Kioxia Corporation
    Inventors: Kazutaka TAKIZAWA, Yoshihisa KOJIMA, Sumio KURODA, Masaaki NIIJIMA
  • MEMORY SYSTEM
    Publication number: 20210081276
    Abstract: A memory system includes a nonvolatile memory, a buffer, and a controller. The buffer can temporarily store a plurality of data bits to be written to the nonvolatile memory. The controller can write the plurality of data bits, read from the buffer, to the nonvolatile memory; write a plurality of intermediate parity bits to the buffer, but not to the nonvolatile memory, wherein each of the plurality of intermediate parity bits is associated with an error correction process on each of the plurality of data bits; and write, to the nonvolatile memory, an accumulated parity bit that is an integration of the plurality of intermediate parity bits.
    Type: Application
    Filed: March 2, 2020
    Publication date: March 18, 2021
    Applicant: KIOXIA CORPORATION
    Inventors: Riki SUZUKI, Toshikatsu HIDA, Yoshihisa KOJIMA, Takehiko AMAKI, Suguru NISHIKAWA
  • MEMORY SYSTEM AND METHOD
    Publication number: 20210073119
    Abstract: According to one embodiment, a memory system includes a non-volatile memory including first and second block groups, and a controller that performs a first write operation for the first block group and the first or a second write operation for the second block group. A first or second number of bits is written into a memory cell in the first or the second write operation. The second number of bits is larger than the first number of bits. The controller allocates a block to a buffer as a write destination block in the first write operation based on a degree of wear-out of at least one block, and writes data from an external device into the buffer in the first write operation.
    Type: Application
    Filed: March 3, 2020
    Publication date: March 11, 2021
    Applicant: Kioxia Corporation
    Inventors: Takehiko AMAKI, Toshikatsu HIDA, Shunichi IGAHARA, Yoshihisa KOJIMA, Suguru NISHIKAWA
  • Storage device
    Patent number: 10915266
    Abstract: According to one embodiment, a storage device includes a first memory cell; a second memory cell; and a controller configured to, in response to receiving a first command set, execute a first erase operation which is included in an erase operation of data of the first memory cell, and suspend the first erase operation, and in response to receiving a second command set, execute a read operation or a write operation of the second memory cell and subsequently resume the suspended first erase operation.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: February 9, 2021
    Assignees: TOSHIBA MEMORY CORPORATION, TOSHIBA INFORMATION SYSTEMS (JAPAN) CORPORATION
    Inventors: Yusuke Ochi, Masanobu Shirakawa, Yoshihisa Kojima, Kiyotaka Iwasaki, Katsuhiko Ueki, Kouji Watanabe
  • Memory system
    Patent number: 10917118
    Abstract: According to one embodiment, a memory system includes a first volatile memory, a nonvolatile memory and a controller. The nonvolatile memory includes a plurality of chips. The controller generates a second error correcting code using data stored in the first volatile memory. The second error correcting code is a code for correcting data which cannot be corrected included in a first data group using a first error correcting code. The controller releases an area of the first volatile memory corresponding to the first data group written in the nonvolatile memory, before completion of writing of all of the data which are stored in the first volatile memory and includes in a codeword of the second error correcting code to the nonvolatile memory.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: February 9, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Erika Kaku, Yoshihisa Kojima
  • Memory system, control method thereof, and program
    Patent number: 10910073
    Abstract: A memory system includes a nonvolatile memory configured to execute one of a plurality of read operations, including a first read operation and a second read operation, and a memory controller configured to issue a read command to the nonvolatile memory to cause the nonvolatile memory to execute one of the plurality of read operations. The memory controller is configured to receive a read request, estimate a reliability level of a result of a read operation to be executed by the nonvolatile memory to read data from a physical address specified in the read request, select one of the first and second read operations to be executed first in a read sequence corresponding to the read request by the nonvolatile memory based on the estimated reliability level, and instruct the nonvolatile memory to execute the selected read operation.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: February 2, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Yoshihisa Kojima