Patents by Inventor Yoshihisa Kojima
Yoshihisa Kojima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220130462Abstract: According to one embodiment, the semiconductor memory medium includes a first memory cell, a first word line coupled to the first memory cell, and a row decoder coupled to the first word line. A write operation is executed multiple times on the first memory cell within a first period from after an execution of an erase operation to an execution of a next erase operation. The write operation includes at least one of program loops each including a program operation and a verify operation. In the verify operation, the row decoder applies a verify voltage to the first word line. The verify voltage is set in accordance with a number of executed write operations on the first memory cell within the first period.Type: ApplicationFiled: January 10, 2022Publication date: April 28, 2022Applicant: Kioxia CorporationInventors: Suguru NISHIKAWA, Takehiko AMAKI, Yoshihisa KOJIMA, Shunichi IGAHARA
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Publication number: 20220115070Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes: first memory cells, first word lines, a first row decoder, and a driver circuit. The first row decoder includes first transistors capable of coupling the first word lines to first signal lines, and a first block decoder supplying a first block selection signal to the first transistors. When the controller issues a data read command, the first block decoder asserts the first block selection signal to allow the first transistors to transfer a first voltage to a selected first word line, and a second voltage to unselected other first word lines. After data is read, the first block decoder continues asserting the first block selection signal, and the driver circuit transfers a third voltage.Type: ApplicationFiled: December 20, 2021Publication date: April 14, 2022Applicant: KIOXIA CORPORATIONInventors: Masanobu Shirakawa, Marie Takada, Tsukasa Tokutomi, Yoshihisa Kojima, Kiichi Tachi
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Publication number: 20220083264Abstract: A memory system includes a controller that transmits, to a memory chip, one first command set indicating a head of a third storage area being one of second storage areas, in a case where first data is read to a first buffer of the memory chip. The first data includes a plurality of first data segments having been stored in the second storage areas. The memory chip includes circuitry that outputs a second data segment and a third data segment to the controller in a period after the controller transmits the first command set to the memory chip before the controller transmits a second command set to the memory chip. The second data segment is a data segment having been stored in the third storage area. The third data segment is a data segment having been stored in a fourth storage area different from the third storage area.Type: ApplicationFiled: March 12, 2021Publication date: March 17, 2022Applicant: Kioxia CorporationInventors: Yoshihisa KOJIMA, Riki SUZUKI
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Publication number: 20220058085Abstract: A memory system includes a non-volatile memory and a controller that includes a toggle encoder configured to encode first data having a first bit length and a first number of toggles, into second data having a second bit length longer than the first bit length and a second number of toggles smaller than the first number of toggles, and transmit the second data to the non-volatile memory. The memory system may further include a toggle decoder configured to decode third data received from the non-volatile memory into fourth data, the third data having the second bit length and the second number of toggles and the fourth data having the first bit length and the first number of toggles.Type: ApplicationFiled: November 4, 2021Publication date: February 24, 2022Inventors: Shunichi IGAHARA, Yoshihisa KOJIMA, Takehiko AMAKI, Suguru NISHIKAWA
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Publication number: 20220044738Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The memory controller is configured: to store, in a buffer, a data set read from a cell unit, and an expected data set generated by an error correction on the data set; to count a number of first and second memory cells corresponding to a first and a second combination of data in the data set and the expected data set, respectively, among the memory cells in the cell unit; to calculate a shift amount of a read voltage used in a read operation from the cell unit, based on the number of the first and second memory cells; and to apply the shift amount to a next read operation from the first cell unit.Type: ApplicationFiled: October 27, 2021Publication date: February 10, 2022Applicant: Toshiba Memory CorporationInventors: Tsukasa TOKUTOMI, Masanobu SHIRAKAWA, Kengo KUROSE, Marie TAKADA, Ryo YAMAKI, Kiyotaka IWASAKI, Yoshihisa KOJIMA
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Patent number: 11244728Abstract: According to one embodiment, the semiconductor memory medium includes a first memory cell, a first word line coupled to the first memory cell, and a row decoder coupled to the first word line. A write operation is executed multiple times on the first memory cell within a first period from after an execution of an erase operation to an execution of a next erase operation. The write operation includes at least one of program loops each including a program operation and a verify operation. In the verify operation, the row decoder applies a verify voltage to the first word line. The verify voltage is set in accordance with a number of executed write operations on the first memory cell within the first period.Type: GrantFiled: September 11, 2020Date of Patent: February 8, 2022Assignee: Kioxia CorporationInventors: Suguru Nishikawa, Takehiko Amaki, Yoshihisa Kojima, Shunichi Igahara
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Patent number: 11238936Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes: first memory cells, first word lines, a first row decoder, and a driver circuit. The first row decoder includes first transistors capable of coupling the first word lines to first signal lines, and a first block decoder supplying a first block selection signal to the first transistors. When the controller issues a data read command, the first block decoder asserts the first block selection signal to allow the first transistors to transfer a first voltage to a selected first word line, and a second voltage to unselected other first word lines. After data is read, the first block decoder continues asserting the first block selection signal, and the driver circuit transfers a third voltage.Type: GrantFiled: September 8, 2020Date of Patent: February 1, 2022Assignee: KIOXIA CORPORATIONInventors: Masanobu Shirakawa, Marie Takada, Tsukasa Tokutomi, Yoshihisa Kojima, Kiichi Tachi
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Patent number: 11231874Abstract: A memory system includes a nonvolatile memory including a plurality of blocks, in each of which a plurality of memory cells is arranged between bit lines and a source line, and a memory controller configured to control an operation of the nonvolatile memory. The memory controller is configured to issue a warming command to the nonvolatile memory when a temperature of the nonvolatile memory is lower than a first temperature, and the nonvolatile memory, in response to the warming command, causes current to flow through at least one bit line connected to memory cells of a first block.Type: GrantFiled: February 20, 2019Date of Patent: January 25, 2022Assignee: TOSHIBA MEMORY CORPORATIONInventors: Suguru Nishikawa, Masanobu Shirakawa, Yoshihisa Kojima, Takehiko Amaki
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Patent number: 11216337Abstract: A memory system includes a nonvolatile memory, a memory controller included in a first package, and a memory interface circuit included in a second package that is different from the first package. The memory controller includes an encoder for performing encoding for error correction. The memory controller is configured to encode first data into second data using the encoder, and program the second data into a location in the nonvolatile memory. The memory interface circuit is interposed between the memory and the memory controller. The memory interface circuit includes a decoder for performing decoding for error correction. The memory interface circuit is configured to read third data from a first location in the nonvolatile memory, diagnose the third data by decoding the third data using the decoder, and convey a result of the diagnosis to the memory controller.Type: GrantFiled: March 30, 2020Date of Patent: January 4, 2022Assignee: TOSHIBA MEMORY CORPORATIONInventors: Takashi Ide, Yoshihisa Kojima
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Patent number: 11199974Abstract: A semiconductor storage device comprises a nonvolatile semiconductor memory with memory regions, threads, and a controller. Each thread includes a buffer region in which write data from a host are stored before the write data are written to one of the memory regions, and the buffer region of each thread is different from buffer regions of the other threads. The controller receives stream data from the host, each stream data being associated with one of multiple stream identifications, allocates each stream identification to one of the threads according to priority levels assigned to the stream identifications, such that a stream identification assigned a highest priority level is allocated to a thread to which none of other stream identifications are allocated, and writes each stream data stored in the buffer regions to one of the memory regions according to stream identification of the stream data.Type: GrantFiled: July 13, 2020Date of Patent: December 14, 2021Assignee: KIOXIA CORPORATIONInventors: Motohiro Matsuyama, Yoshihisa Kojima
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Publication number: 20210383877Abstract: A memory system includes a nonvolatile memory configured to execute one of a plurality of read operations, including a first read operation and a second read operation, and a memory controller configured to issue a read command to the nonvolatile memory to cause the nonvolatile memory to execute one of the plurality of read operations. The memory controller is configured to receive a read request, estimate a reliability level of a result of a read operation to be executed by the nonvolatile memory to read data from a physical address specified in the read request, select one of the first and second read operations to be executed first in a read sequence corresponding to the read request by the nonvolatile memory based on the estimated reliability level, and instruct the nonvolatile memory to execute the selected read operation.Type: ApplicationFiled: August 24, 2021Publication date: December 9, 2021Inventor: Yoshihisa KOJIMA
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Patent number: 11194656Abstract: A memory system includes a non-volatile memory and a controller that includes a toggle encoder configured to encode first data having a first bit length and a first number of toggles, into second data having a second bit length longer than the first bit length and a second number of toggles smaller than the first number of toggles, and transmit the second data to the non-volatile memory. The memory system may further include a toggle decoder configured to decode third data received from the non-volatile memory into fourth data, the third data having the second bit length and the second number of toggles and the fourth data having the first bit length and the first number of toggles.Type: GrantFiled: January 28, 2020Date of Patent: December 7, 2021Assignee: KIOXIA CORPORATIONInventors: Shunichi Igahara, Yoshihisa Kojima, Takehiko Amaki, Suguru Nishikawa
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Patent number: 11195585Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The memory controller is configured: to store, in a buffer, a data set read from a cell unit, and an expected data set generated by an error correction on the data set; to count a number of first and second memory cells corresponding to a first and a second combination of data in the data set and the expected data set, respectively, among the memory cells in the cell unit; to calculate a shift amount of a read voltage used in a read operation from the cell unit, based on the number of the first and second memory cells; and to apply the shift amount to a next read operation from the first cell unit.Type: GrantFiled: March 11, 2019Date of Patent: December 7, 2021Assignee: Toshiba Memory CorporationInventors: Tsukasa Tokutomi, Masanobu Shirakawa, Kengo Kurose, Marie Takada, Ryo Yamaki, Kiyotaka Iwasaki, Yoshihisa Kojima
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Publication number: 20210349664Abstract: A memory system includes a non-volatile memory chip that includes a memory cell array, and a memory controller. The memory controller is configured to perform a read operation on the non-volatile memory chip by instructing the non-volatile memory chip to perform a sensing operation to read data stored in the memory cell array, estimating a time when the read data becomes ready to be transferred from the non-volatile memory chip to the memory controller, and instructing the non-volatile memory chip, after the estimated time, to perform a transfer operation to transfer the read data to the memory controller.Type: ApplicationFiled: July 21, 2021Publication date: November 11, 2021Inventors: Marie SIA, Yoshihisa KOJIMA, Suguru NISHIKAWA, Riki SUZUKI
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Patent number: 11145374Abstract: A memory system includes a nonvolatile memory configured to execute one of a plurality of read operations, including a first read operation and a second read operation, and a memory controller configured to issue a read command to the nonvolatile memory to cause the nonvolatile memory to execute one of the plurality of read operations. The memory controller is configured to receive a read request, estimate a reliability level of a result of a read operation to be executed by the nonvolatile memory to read data from a physical address specified in the read request, select one of the first and second read operations to be executed first in a read sequence corresponding to the read request by the nonvolatile memory based on the estimated reliability level, and instruct the nonvolatile memory to execute the selected read operation.Type: GrantFiled: December 22, 2020Date of Patent: October 12, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventor: Yoshihisa Kojima
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Publication number: 20210295921Abstract: A memory system includes a non-volatile memory having a plurality of memory cells and a controller. The controller is configured to switch a mode for controlling an access operation to the non-volatile memory from a first mode to a second mode, in response to receiving from a host, a first command for instructing the controller to switch the mode from the first mode to the second mode. The access operation controlled according to the second mode improves data retention relative to the access operation controlled according to the first mode.Type: ApplicationFiled: February 25, 2021Publication date: September 23, 2021Inventors: Riki SUZUKI, Yoshihisa KOJIMA
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Patent number: 11127476Abstract: According to one embodiment, a memory system includes a first memory and a memory controller. The first memory is nonvolatile and includes a plurality of memory cell transistors, each of which stores data corresponding to a threshold voltage. The memory controller causes the first memory to execute a read operation to acquire data corresponding to the threshold voltage from the plurality of memory cell transistors on the basis of a result of comparison between the threshold voltage and a read voltage. The memory controller selects a first candidate value from among a plurality of candidate values for the read voltage in accordance with a degree of stress that affects the threshold voltage; and causes the first memory to execute the read operation using the first candidate value as the read voltage.Type: GrantFiled: March 12, 2020Date of Patent: September 21, 2021Assignee: Kioxia CorporationInventors: Kazutaka Takizawa, Yoshihisa Kojima, Sumio Kuroda, Masaaki Niijima
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Publication number: 20210286524Abstract: According to one embodiment, there is provided a nonvolatile memory including a memory cell array, as input/output buffer, one or more intermediate buffers, and a control circuit. The memory cell array includes a plurality of pages. Each of the one or more intermediate buffers is electrically connected between the memory cell array and the input/output buffer. The control circuit is configured to store, in a first intermediate buffer, data read through sensing operation from a first page out of the plurality of pages in accordance with a first command that includes a sensing operation instruction and designation of the first intermediate buffer among the one or more intermediate buffers.Type: ApplicationFiled: May 27, 2021Publication date: September 16, 2021Applicant: Toshiba Memory CorporationInventors: Yoshihisa KOJIMA, Masanobu SHIRAKAWA, Kiyotaka IWASAKI
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Publication number: 20210286671Abstract: According to one embodiment, a memory system includes a nonvolatile memory, a random access memory and a controller. When writing n?1 data portions of a first unit that are included in n?1 error correction code frames of a first size, respectively, in the nonvolatile memory, the controller generates a second error correction code that constitutes an error correction code frame of a second size together with the n?1 data portions of the first unit and a second data portion to be written into the nonvolatile memory by encoding the n?1 data portions of the first unit and the second data portion, and writes the second data portion and the second error correction code into the nonvolatile memory.Type: ApplicationFiled: March 11, 2021Publication date: September 16, 2021Applicant: Kioxia CorporationInventors: Takehiko AMAKI, Toshikatsu HIDA, Shunichi IGAHARA, Yoshihisa KOJIMA, Suguru NISHIKAWA
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Patent number: 11114170Abstract: A semiconductor memory device includes a memory cell array, an input/output circuit configured to output read data from the semiconductor memory device, a first data latch configured to latch data read from the memory cell array as the read data, a second data latch to which the read data is transferred from the first data latch and from which the read data is transferred to the input/output circuit, a signaling circuit configured to output a ready signal or a busy signal, and a control circuit configured to control the signaling circuit to output the busy signal while the read data is being latched in the first data latch during a read operation performed on the memory cell array and to output the ready signal while the read data latched in the first data latch is being transferred from the first latch to the second latch.Type: GrantFiled: May 28, 2020Date of Patent: September 7, 2021Assignee: KIOXIA CORPORATIONInventors: Takaya Handa, Yoshihisa Kojima, Kiyotaka Iwasaki