Patents by Inventor Yoshikazu Kojima

Yoshikazu Kojima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6054841
    Abstract: A charge/discharge control circuit is provided for an electric power source apparatus in which a service life is prolonged. A voltage dividing circuit, an overcharge voltage detection circuit, an overdischarge voltage detection circuit and a control circuit are connected in parallel to a secondary cell which is an electric power source, wherein the control circuit detects a condition of the secondary cell from the overcharge/overdischarge voltage detection circuits and outputs a signal Vs for controlling a power supply to an external equipment and a charge by an external power source and controls a switching element provided in series with the voltage dividing circuit and reduces a current which flows through the voltage dividing circuit.
    Type: Grant
    Filed: November 20, 1998
    Date of Patent: April 25, 2000
    Assignee: Seiko Instruments Inc.
    Inventors: Minoru Sudo, Takayuki Takashina, Yoshikazu Kojima, Sadashi Shimoda, Hiroshi Mukainakano
  • Patent number: 6046492
    Abstract: A semiconductor temperature sensor comprises independent current sources and bipolar transistors connected to form a Darlington circuit. The bipolar transistors have electrodes each connected to one of the current sources. An output voltage of the semiconductor temperature sensor is adjusted by trimming a current value of at least one of the current sources.
    Type: Grant
    Filed: September 12, 1996
    Date of Patent: April 4, 2000
    Assignee: Seiko Instruments Inc.
    Inventors: Satoshi Machida, Yukito Kawahara, Kentaro Kuhara, Toru Shimizu, Yoshikazu Kojima
  • Patent number: 6040200
    Abstract: A method of fabricating a light valve device comprises forming a substrate having stacked layers including a light-shielding thin film layer, an insulating film, and a single crystalline semiconductor thin film stacked in this order on a transparent support substrate. A light-shielding layer pattern is formed by selectively etching the stacked layers. Thereafter, a switching element is formed comprised of a transistor having a channel region formed in the single crystalline semiconductor thin film and a main gate electrode covering the channel region. The channel region is provided over the light-shielding pattern layer to prevent light incident from the transparent support substrate from illuminating the channel region to suppress a photo-induced leakage current in the channel region. A transparent electrode is formed and is electrically connected to the switching element.
    Type: Grant
    Filed: April 14, 1997
    Date of Patent: March 21, 2000
    Assignees: Agency of Industrial Science and Technology, Seiko Instruments Inc.
    Inventors: Yutaka Hayashi, Masaaki Kamiya, Yoshikazu Kojima, Hiroaki Takasu
  • Patent number: 6028338
    Abstract: A semiconductor integrated circuit device has a peripheral transistor having a strengthened ESD resistance for external connection. The peripheral transistor has a channel structure effective to release an electrostatic stress current more efficiently than an internal transistor of the semiconductor integrated circuit. In one embodiment, the peripheral transistor has a channel portion that is shorter than the channel portion of an internal transistor. In another embodiment, the peripheral transistor has a substrate contact, a ground line, and an additional resistor interconnection between them to efficiently release an electrostatic stress current. In another embodiment, the peripheral transistor has an asymmetric channel structure so that the distance between the source contact and the gate electrode is set shorter than the distance between the drain contact and the gate electrode.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: February 22, 2000
    Assignee: Seiko Instruments Inc.
    Inventors: Yutaka Saito, Jun Osanai, Yoshikazu Kojima, Masaaki Kamiya
  • Patent number: 6022792
    Abstract: To decrease the area of a chip, improve the manufacturing efficiency and decrease the cost in a semiconductor device such as a driver integrated circuit having a number of output pads, and an electronic circuit device such as electronic clock. There are disposed output pads superposed in two dimensions on driving transistors or logic circuits connected thereto, respectively. Further, not only aluminum interconnection but also bump electrodes or barrier metals are used for the interconnection of the semiconductor device. In a case where a semiconductor integrated circuit is electrically adhered on to a printed circuit board in a face down manner, a solder bump disposed on the semiconductor integrated circuit and the interconnection of the printed circuit board are directly connected to each other, thereby realizing the electrical connection. On this occasion, the bump electrode as the external connecting terminal of the semiconductor integrated circuit is laminated on the transistor.
    Type: Grant
    Filed: March 12, 1997
    Date of Patent: February 8, 2000
    Assignee: Seiko Instruments, Inc.
    Inventors: Kazutoshi Ishii, Naoto Inoue, Koushi Maemura, Shoji Nakanishi, Yoshikazu Kojima, Kiyoaki Kadoi, Takao Akiba, Yasuhiro Moya, Kentaro Kuhara
  • Patent number: 6013940
    Abstract: A resistor ladder network may be formed with a reduced space on a semiconductor substrate by patterning a plurality of layers of resistive polycrystalline silicon films spaced by insulating layers. Such a device includes a first insulating film formed on a semiconductor substrate, one or more serial-connected first resistors formed in a first polycrystalline silicon film provided on the semiconductor substrate via the first insulating film, a second insulating film provided on the first polycrystalline silicon film, one or more series-connected second resistors formed in a second polycrystalline silicon film provided apart from the first polycrystalline silicon film via the second insulating film, the second polycrystalline silicon film being connected to the first polycrystalline silicon film. A third insulating film is provided over the second polycrystalline silicon film, and metal wires provided on a surface of the second polycrystalline silicon film via contact holes formed in the third insulating film.
    Type: Grant
    Filed: August 18, 1995
    Date of Patent: January 11, 2000
    Assignee: Seiko Instruments Inc.
    Inventors: Hirofumi Harada, Jun Osanai, Yoshikazu Kojima, Yutaka Saitoh
  • Patent number: 5998974
    Abstract: A charge/discharge control circuit has a voltage detector for detecting a voltage level of a secondary cell, a switch connected in series with the secondary cell, and a control circuit connected in parallel with the voltage detector for receiving and processing an output signal of the voltage detector and controlling an impedance of the switch. The voltage detector, the switch and the control circuit are integrated in a single substrate. In a preferred embodiment, the switch comprises an external connection terminal and a second terminal connected to the secondary cell, a first IGFET connected between the first and second terminals, a second IGFET connectected between the first terminal and a substrate electrode of the first IGFET, and a third IGFET connected between the second terminal and the substrate electrode of the first IGFET.
    Type: Grant
    Filed: November 20, 1998
    Date of Patent: December 7, 1999
    Assignee: Seiko Instruments Inc.
    Inventors: Minoru Sudo, Takayuki Takashina, Yoshikazu Kojima, Sadashi Shimoda, Hiroshi Mukainakano
  • Patent number: 5982002
    Abstract: A miniaturized light valve with a surface area on the order of several centimeters may be successfully formed using a composite substrate and an opposing substrate which has thereon an electrode and which is bonded to the composite substrate at a predetermined gap therefrom. An electro-optical material, such as a liquid crystal compound, is confined within the gap. The composite substrate includes a single crystal layer of a semiconductor material provided on a lower level insulation layer. The single crystal layer is formed with a source region, a drain region, and a channel region of a MOS transistor, and a gate insulation film is provided on the single crystal layer in alignment with the channel region. Further, a gate electrode is provided on the gate insulation film. The composite substrate further includes a pixel electrode on the upper major surface of an insulation layer deposited over the MOS transistor and in contact with the drain region. The single crystal semiconductor thin film is limited to 0.
    Type: Grant
    Filed: January 27, 1993
    Date of Patent: November 9, 1999
    Assignee: Seiko Instruments Inc.
    Inventors: Hiroaki Takasu, Yoshikazu Kojima, Kunihiro Takahashi
  • Patent number: 5982150
    Abstract: A charge/discharge control circuit is provided for an electric power source apparatus in which a service life is prolonged. A voltage dividing circuit, an overcharge voltage detection circuit, an overdischarge voltage detection circuit and a control circuit are connected in parallel to a secondary cell which is an electric power source, wherein the control circuit detects a condition of the secondary cell from the overcharge/overdischarge voltage detection circuits and outputs a signal Vs for controlling a power supply to an external equipment and a charge by an external power source and controls a switching element provided in series with the voltage dividing circuit and reduces a current which flows through the voltage dividing circuit.
    Type: Grant
    Filed: November 20, 1998
    Date of Patent: November 9, 1999
    Assignee: Seiko Instruments Inc.
    Inventors: Minoru Sudo, Takayuki Takashina, Yoshikazu Kojima, Sadashi Shimoda, Hiroshi Mukainakano
  • Patent number: 5982461
    Abstract: A light valve device has a drive substrate integrated with a drive electrode. A transistor is connected to the drive electrode and a driving circuit energizes the drive electrode through the transistor. An opposed substrate is provided opposed to the drive electrode, and an electrooptical material layer is disposed between the drive substrate and the opposed substrate. The drive substrate has a structure comprising a substrate layer and a semiconductor single crystal thin film layer. The semiconductor single crystal thin film layer is made by thinning a semiconductor single crystal wafer which has been bonded to the substrate layer. The light valve device has a small size and high pixel density and can be formed using miniaturization technology. The light valve can be used for a small size, high resolution video projector and a color matrix display device.
    Type: Grant
    Filed: February 14, 1992
    Date of Patent: November 9, 1999
    Inventors: Yutaka Hayashi, Masaaki Kamiya, Yoshikazu Kojima, Hiroaki Takasu
  • Patent number: 5971836
    Abstract: A grinding machine comprises a grinding member having a thickness greater than 10 mm and an outer contact surface extending in a thickness direction of the grinding member for contacting a surface of a workpiece. The grinding member is supported by a first rotational shaft for rotation about a first rotational axis. A first moving mechanism reciprocates the first rotational shaft along a first displacement axis. The workpiece is supported by a second rotational shaft for rotation about a second rotational axis perpendicular to the first displacement axis and the first rotational axis. A second moving mechanism moves at least one of the workpiece and the grinding member along a second displacement axis to bring the outer contact surface of the grinding member into linear contact with the surface of the workpiece to grind the workpiece. The linear contact between the outer contact surface of the grinding member and the surface of the workpiece has a contact length greater than 10 mm.
    Type: Grant
    Filed: August 29, 1995
    Date of Patent: October 26, 1999
    Assignee: Seiko Seiki Kabushiki Kaisha
    Inventors: Toshiharu Kogure, Katsura Tomotaki, Yoshikazu Kojima, Jun Osanai
  • Patent number: 5965921
    Abstract: In an integrated circuit type semiconductor device consisting of MISFETs, high rated voltage characteristic is obtained in a gate insulation film structure of a thin film. Further, a reduction in the manufacturing cost of semiconductor devices including high-rated voltage and low rated voltage MISFETs. An intermediate gate electrode is provided which overlies a channel formation region and a gate region with the same gate insulation film being sandwiched therebetween. The gate region is provided on the surface of a substrate. The channel formation region has an impedance indirectly controllable via the intermediate gate electrode upon application of a voltage to the gate region. The intermediate gate electrode is provided with a voltage reset(set) means connected thereto for eliminating the occurrence of charge-up.
    Type: Grant
    Filed: July 17, 1996
    Date of Patent: October 12, 1999
    Assignee: Seiko Instruments Inc.
    Inventor: Yoshikazu Kojima
  • Patent number: 5950085
    Abstract: A method of manufacturing an electrically erasable semiconductor non-volatile memory device comprises forming a field insulating film on a surface of a semiconductor substrate having a first conductivity type. A gate insulating film is formed on the surface of the semiconductor substrate. Source and drain regions having a second conductivity type are formed in the surface of the semiconductor substrate in spaced-apart relationship with each other by introducing impurity ions having the second conductivity type into the semiconductor substrate with an acceleration energy sufficient to form a peak value of impurity concentration at a depth of more than approximately 500 .ANG. from the surface of the semiconductor substrate. The gate insulating film is then etched on the drain region to form a tunnel region having opposite sides connected to the field insulating film.
    Type: Grant
    Filed: March 22, 1996
    Date of Patent: September 7, 1999
    Assignee: Seiko Instruments Inc.
    Inventors: Yoshikazu Kojima, Tetsuya Maeda
  • Patent number: 5925574
    Abstract: A method of producing a bipolar transistor composed of collector, base and emitter regions disposed sequentially on a semiconductor substrate. According to the method, a semiconductor layer is deposited on the collector region, the semiconductor layer is cleaned to expose an active surface, an impurity source gas is applied to the exposed active surface while heating the substrate to form an impurity adsorption layer, the impurity is diffused into the semiconductor layer to form the base region, another semiconductor layer is deposited on the base region, this semiconductor layer is cleaned to expose an active surface, another impurity source gas is applied to the exposed active surface while heating the substrate to form another impurity adsorption layer, and impurity is diffused into the semiconductor layer to from the impurity adsorption layer to form the emitter region.
    Type: Grant
    Filed: April 10, 1992
    Date of Patent: July 20, 1999
    Assignee: Seiko Instruments Inc.
    Inventors: Kenji Aoki, Tadao Akamine, Yoshikazu Kojima
  • Patent number: 5926699
    Abstract: A method of fabricating a semiconductor device comprises the steps of sequentially forming a first gate electrode and an insulating film over a transparent support substrate, forming a through-hole in the insulating film, forming a semiconductor single crystal silicon thin film over the transparent support substrate by epitaxial growth in the through-hole of the insulating film, forming a transistor element having a channel region formed in the semiconductor single crystal silicon thin film, and forming a second gate electrode over and electrically insulated from the channel region of the transistor element.
    Type: Grant
    Filed: June 2, 1998
    Date of Patent: July 20, 1999
    Assignees: Agency of Industrial Science and Technology, Seiko Instruments Inc.
    Inventors: Yutaka Hayashi, Masaaki Kamiya, Yoshikazu Kojima, Hiroaki Takasu
  • Patent number: 5849612
    Abstract: A thin film field effect transistor has a three-layer structure including a polycrystalline semiconductor layer to be a channel region, a conductive layer to be a gate electrode and a insulating layer to be a gate insulating film between the channel region and the gate electrode. The roughness of an interface between the channel region and the gate insulating film is less than a few nm so that the current drivability of the transistor is improved.
    Type: Grant
    Filed: February 3, 1997
    Date of Patent: December 15, 1998
    Assignee: Seiko Instruments Inc.
    Inventors: Hiroshi Takahashi, Yoshikazu Kojima
  • Patent number: 5841265
    Abstract: A charge/discharge control circuit comprises two serially connected electric power sources and two overcharge/overdischarge detection circuits. A control circuit outputs a signal for controlling the charge/discharge of the electric power sources in accordance with signals from the two overcharge/overdischarge detection circuits. An intermediate voltage receiving circuit receives, in accordance with the signal from the control circuit, a voltage at a junction point between the two electric power sources and outputs a signal indicative of a relation of the relative voltage between the two electric power sources.
    Type: Grant
    Filed: March 12, 1997
    Date of Patent: November 24, 1998
    Assignee: Seiko Instruments Inc.
    Inventors: Minoru Sudo, Takayuki Takashina, Yoshikazu Kojima, Sadashi Shimoda, Hiroshi Mukainakano
  • Patent number: 5834809
    Abstract: A MIS transistor comprises a semiconductor substrate having a first conductivity type, a source region and a drain region disposed in the semiconductor substrate in spaced-apart relation from one another and having a second conductivity type, and an insulating film disposed on the surface of the semiconductor substrate. A gate electrode is disposed on the insulating film between the source region and the drain region. A diffused region having the first conductivity type is disposed in the semiconductor substrate and in contact with the source region. An oxide film is disposed on the diffused region.
    Type: Grant
    Filed: December 7, 1995
    Date of Patent: November 10, 1998
    Assignee: Seiko Instruments Inc.
    Inventors: Yuichi Kato, Yoshikazu Kojima
  • Patent number: 5825064
    Abstract: The semiconductor nonvolatile memory has integrated memory cells, each being operative to carry out writing and reading of information in random-access basis and having an electric charge storage structure effective to memorize the information in nonvolatile state. The information is temporarily written into each memory cell in volatile state, and thereafter the temporarily written information is written at one into the respective electric charge storage structure of each memory cell, thereby effecting quick writing of nonvolatile information into the respective memory cells of multi-bits.
    Type: Grant
    Filed: March 3, 1993
    Date of Patent: October 20, 1998
    Assignee: Agency of Industrial Science and Technology and Seiko Instruments Inc.
    Inventors: Yutaka Hayashi, Yoshikazu Kojima, Ryoji Takada, Masaaki Kamiya
  • Patent number: 5759878
    Abstract: A method of fabricating a semiconductor device comprises the steps of preparing a transparent support substrate, forming a first gate electrode comprising semiconductor single crystal silicon by epitaxial growth on the transparent support substrate, forming an insulating film over the first gate electrode, forming a through-hole in the insulating film to expose a portion of the first gate electrode, laterally and epitaxially growing a semiconductor single crystal silicon thin film over the transparent substrate by epitaxial growth in the through-hole of the insulating film, forming a transistor element having a channel region formed in the semiconductor single crystal silicon thin film, and forming a second gate electrode over and electrically insulated from the channel region.
    Type: Grant
    Filed: June 29, 1995
    Date of Patent: June 2, 1998
    Assignees: Agency of Industrial Science and Technology, Seiko Instruments Inc.
    Inventors: Yutaka Hayashi, Masaaki Kamiya, Yoshikazu Kojima, Hiroaki Takasu