Patents by Inventor Yoshikazu Tanabe
Yoshikazu Tanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7247921Abstract: A semiconductor apparatus includes a semiconductor substrate having a device region and a periphery region surrounding the device region; a semiconductor device provided in the device region of the semiconductor substrate; a first electrode pad provided on the semiconductor substrate; a second electrode pad provided on the semiconductor substrate; a strip-like, first conductivity type semiconductor pattern; and a strip-like, second conductivity type semiconductor pattern. The strip-like, first conductivity type semiconductor pattern extends in the periphery region of the semiconductor substrate, and the first electrode pad is electrically connected to one end of the first conductivity type semiconductor pattern. The strip-like, second conductivity type semiconductor pattern constitutes a p-n junction in conjunction with the first conductivity type semiconductor pattern. The first and second electrode pads are electrically connected to both ends of the second conductivity type semiconductor pattern.Type: GrantFiled: June 9, 2005Date of Patent: July 24, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Masayuki Sugiura, Yasuhiko Kuriyama, Toru Sugiyama, Yoshikazu Tanabe, Makoto Shibamiya
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Patent number: 7242016Abstract: A surface inspection apparatus and a method for inspecting the surface of a sample are capable of inspecting discriminatingly between scratches of various configuration and adhered foreign objects that occur on the surface of a work target when the work target (for example, an insulating film on a semiconductor substrate) is subjected to a polishing process such as CMP or a grinding process, in semiconductor manufacturing process or magnetic head manufacturing process. In the invention, the scratch and foreign object that occur on the polished or ground surface of the sample is epi-illuminated and slant-illuminated by use of approximately same light flux, the difference between the scattered light intensity from the shallow scratch and from the foreign object is applied to thereby discriminate between the shallow scratch and the foreign object, and the directionality of the scattered light is detected to discriminate between the linear scratch and the foreign object.Type: GrantFiled: April 13, 2005Date of Patent: July 10, 2007Assignees: Hitachi, Ltd., Hitachi High-Technologies CorporationInventors: Ichiro Ishimaru, Minori Noguchi, Ichiro Moriyama, Yoshikazu Tanabe, Yasuo Yatsugake, Yukio Kenbou, Kenji Watanabe, Hirofumi Tsuchiyama
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Publication number: 20070121108Abstract: An apparatus for detecting defects, including: a first illumination optical unit which illuminates from a normal direction or in the vicinity of the normal direction; a second illumination optical unit which illuminates from a first elevation angle; a first detection optical unit which detects light reflected by the illumination of the first illumination optical unit or the second illumination optical unit with plural detectors; a second detection optical unit which detects light reflected by the illumination of the first illumination optical unit or the second illumination optical unit with plural detectors; wherein the plural detectors of the first detection optical unit and the plural detectors of the second detection optical unit are photomultipliers, and the signal processor processes the signals outputted from the photomultipliers and are adjusted to balance in sensitivities.Type: ApplicationFiled: January 25, 2007Publication date: May 31, 2007Inventors: Ichiro Ishimaru, Minori Noguchi, Ichiro Moriyama, Yoshikazu Tanabe, Yasuo Yatsugake, Yukio Kenbou, Kenji Watanabe, Hirofumi Tsuchiyama
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Patent number: 7122469Abstract: With a view to preventing the oxidation of a metal film at the time of light oxidation treatment after gate patterning and at the same time to making it possible to control the reproducibility of oxide film formation and homogeneity of oxide film thickness at gate side-wall end portions, in a gate processing step using a poly-metal, a gate electrode is formed by patterning a gate electrode material which has been deposited over a semiconductor wafer 1A having a gate oxide film formed thereon and has a poly-metal structure and then, the principal surface of the semiconductor wafer 1A heated to a predetermined temperature or vicinity thereof is supplied with a hydrogen gas which contains water at a low concentration, the water having been formed from hydrogen and oxygen by a catalytic action, to selectively oxidize the principal surface of the semiconductor wafer 1A, whereby the profile of the side-wall end portions of the gate electrode is improvedType: GrantFiled: August 4, 2005Date of Patent: October 17, 2006Assignee: Hitachi, Ltd.Inventors: Yoshikazu Tanabe, Isamu Asano, Makoto Yoshida, Naoki Yamamoto, Masayoshi Saito, Nobuyoshi Natsuaki
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Publication number: 20060175651Abstract: Formation of an WNX film 24 constituting a barrier layer of a gate electrode 7A having a polymetal structure is effected in an atmosphere containing a high concentration nitrogen gas, whereby release of N (nitrogen) from the WNX film 24 is suppressed in the heat treatment step after the formation of the gate electrode 7A.Type: ApplicationFiled: April 3, 2006Publication date: August 10, 2006Inventors: Naoki Yamamoto, Yoshikazu Tanabe, Hiroshige Kogayu, Takehiko Yoshida
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Patent number: 7084708Abstract: A high-frequency amplification device includes a high-frequency amplifier including input and output sections, a first capacitor including first and second electrodes, and a first insulation film interposed therebetween. The first electrode is connected to the output section via a first inductor, and the second electrode is grounded. The amplification device further comprises a second capacitor including third and fourth electrodes and a second insulation film interposed therebetween. The third electrode is formed of a material substantially identical to that of the first electrode, and the fourth electrode is formed of a material substantially identical to that of the second electrode. The second insulation film is formed of a material substantially identical to that of the first insulation film and has a thickness substantially identical to that of the first insulation film.Type: GrantFiled: July 12, 2004Date of Patent: August 1, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Masayuki Sugiura, Makoto Shibamiya, Yasuhiko Kuriyama, Toru Sugiyama, Yoshikazu Tanabe
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Patent number: 7053007Abstract: A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vicinity of a semiconductor wafer, and forming a thin oxide film serving as a gate insulating film of an MOS transistor and having a thickness of 5 nm or below on the main surface of the semiconductor wafer at an oxide film-growing rate sufficient to ensure fidelity in formation of an oxide film and uniformity in thickness of the oxide film.Type: GrantFiled: May 19, 2005Date of Patent: May 30, 2006Assignee: Renesas Technology Corp.Inventors: Yoshikazu Tanabe, Satoshi Sakai, Nobuyoshi Natsuaki
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Patent number: 7053459Abstract: Formation of an WNx film 24 constituting a barrier layer of a gate electrode 7A having a polymetal structure is effected in an atmosphere containing a high concentration nitrogen gas, whereby release of N (nitrogen) from the WNx film 24 is suppressed in the heat treatment step after the formation of the gate electrode 7A.Type: GrantFiled: October 31, 2001Date of Patent: May 30, 2006Assignee: Renesas Technology Corp.Inventors: Naoki Yamamoto, Yoshikazu Tanabe, Hiroshige Kogayu, Takehiko Yoshida
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Patent number: 7008880Abstract: A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vicinity of a semiconductor wafer, and forming a thin oxide film serving as a gate insulating film of an MOS transistor and having a thickness of 5 nm or below on the main surface of the semiconductor wafer at an oxide film-growing rate sufficient to ensure fidelity in formation of an oxide film and uniformity in thickness of the oxide film.Type: GrantFiled: February 10, 2004Date of Patent: March 7, 2006Assignee: Renesas Technology Corp.Inventors: Yoshikazu Tanabe, Satoshi Sakai, Nobuyoshi Natsuaki
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Patent number: 6987069Abstract: With a view to preventing the oxidation of a metal film at the time of light oxidation treatment after gate patterning and at the same time to making it possible to control the reproducibility of oxide film formation and homogeneity of oxide film thickness at gate side-wall end portions, in a gate processing step using a poly-metal, a gate electrode is formed by patterning a gate electrode material which has been deposited over a semiconductor wafer 1A having a gate oxide film formed thereon and has a poly-metal structure and then, the principal surface of the semiconductor wafer 1A heated to a predetermined temperature or vicinity thereof is supplied with a hydrogen gas which contains water at a low concentration, the water having been formed from hydrogen and oxygen by a catalytic action, to selectively oxidize the principal surface of the semiconductor wafer 1A, whereby the profile of the side-wall end portions of the gate electrode is improved.Type: GrantFiled: April 12, 2004Date of Patent: January 17, 2006Assignee: Hitachi, Ltd.Inventors: Yoshikazu Tanabe, Isamu Asano, Makoto Yoshida, Naoki Yamamoto, Masayoshi Saito, Nobuyoshi Natsuaki
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Publication number: 20050275076Abstract: A semiconductor apparatus comprising: a semiconductor substrate having a device region and a periphery region surrounding the device region; a semiconductor device provided in the device region of the semiconductor substrate; a first electrode pad provided on the semiconductor substrate; a second electrode pad provided on the semiconductor substrate; a strip-like, first conductivity type semiconductor pattern; and a strip-like, second conductivity type semiconductor pattern. The strip-like, first conductivity type semiconductor pattern extends in the periphery region of the semiconductor substrate, and the first electrode pad is electrically connected to one end of the first conductivity type semiconductor pattern. The strip-like, second conductivity type semiconductor pattern constitutes a p-n junction in conjunction with the first conductivity type semiconductor pattern. The first and second electrode pads are electrically connected to both ends of the second conductivity type semiconductor pattern.Type: ApplicationFiled: June 9, 2005Publication date: December 15, 2005Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Masayuki Sugiura, Yasuhiko Kuriyama, Toru Sugiyama, Yoshikazu Tanabe, Makoto Shibamiya
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Publication number: 20050266630Abstract: With a view to preventing the oxidation of a metal film at the time of light oxidation treatment after gate patterning and at the same time to making it possible to control the reproducibility of oxide film formation and homogeneity of oxide film thickness at gate side-wall end portions, in a gate processing step using a poly-metal, a gate electrode is formed by patterning a gate electrode material which has been deposited over a semiconductor wafer 1A having a gate oxide film formed thereon and has a poly-metal structure and then, the principal surface of the semiconductor wafer 1A heated to a predetermined temperature or vicinity thereof is supplied with a hydrogen gas which contains water at a low concentration, the water having been formed from hydrogen and oxygen by a catalytic action, to selectively oxidize the principal surface of the semiconductor wafer 1A, whereby the profile of the side-wall end portions of the gate electrode is improvedType: ApplicationFiled: August 4, 2005Publication date: December 1, 2005Inventors: Yoshikazu Tanabe, Isamu Asano, Makoto Yoshida, Naoki Yamamoto, Masayoshi Saito, Nobuyoshi Natsuaki
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Patent number: 6962880Abstract: A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vicinity of a semiconductor wafer, and forming a thin oxide film serving as a gate insulating film of an MOS transistor and having a thickness of 5 nm or below on the main surface of the semiconductor wafer at an oxide film-growing rate sufficient to ensure fidelity in formation of an oxide film and uniformity in thickness of the oxide film.Type: GrantFiled: February 10, 2004Date of Patent: November 8, 2005Assignee: Renesas Technology Corp.Inventors: Yoshikazu Tanabe, Satoshi Sakai, Nobuyoshi Natsuaki
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Patent number: 6962881Abstract: A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vicinity of a semiconductor wafer, and forming a thin oxide film serving as a gate insulating film of an MOS transistor and having a thickness of 5 nm or below on the main surface of the semiconductor wafer at an oxide film-growing rate sufficient to ensure fidelity in formation of an oxide film and uniformity in thickness of the oxide film.Type: GrantFiled: February 10, 2004Date of Patent: November 8, 2005Assignee: Renesas Technology Corp.Inventors: Yoshikazu Tanabe, Satoshi Sakai, Nobuyoshi Natsuaki
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Publication number: 20050236689Abstract: A high-frequency amplification device includes a high-frequency amplifier including input and output sections, a first capacitor including first and second electrodes, and a first insulation film interposed therebetween. The first electrode is connected to the output section via a first inductor, and the second electrode is grounded. The amplification device further comprises a second capacitor including third and fourth electrodes and a second insulation film interposed therebetween. The third electrode is formed of a material substantially identical to that of the first electrode, and the fourth electrode is formed of a material substantially identical to that of the second electrode. The second insulation film is formed of a material substantially identical to that of the first insulation film and has a thickness substantially identical to that of the first insulation film.Type: ApplicationFiled: July 12, 2004Publication date: October 27, 2005Applicant: Kabushiki Kaisha ToshibaInventors: Masayuki Sugiura, Makoto Shibamiya, Yasuhiko Kuriyama, Toru Sugiyama, Yoshikazu Tanabe
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Publication number: 20050227501Abstract: A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vicinity of a semiconductor wafer, and forming a thin oxide film serving as a gate insulating film of an MOS transistor and having a thickness of 5 nm or below on the main surface of the semiconductor wafer at an oxide film-growing rate sufficient to ensure fidelity in formation of an oxide film and uniformity in thickness of the oxide film.Type: ApplicationFiled: May 19, 2005Publication date: October 13, 2005Inventors: Yoshikazu Tanabe, Satoshi Sakai, Nobuyoshi Natsuaki
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Publication number: 20050208731Abstract: A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vicinity of a semiconductor wafer, and forming a thin oxide film serving as a gate insulating film of an MOS transistor and having a thickness of 5 nm or below on the main surface of the semiconductor wafer at an oxide film-growing rate sufficient to ensure fidelity in formation of an oxide film and uniformity in thickness of the oxide film.Type: ApplicationFiled: May 19, 2005Publication date: September 22, 2005Inventors: Yoshikazu Tanabe, Satoshi Sakai, Nobuyoshi Natsuaki
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Patent number: 6940157Abstract: A high frequency semiconductor module, includes: a semiconductor chip having top and bottom surfaces; a semiconductor element merged in the semiconductor chip; a ground pad of the semiconductor element disposed on the top surface; a metal layer configured to connect to the ground pad and extend to sidewalls of the semiconductor chip; a ground metal arranged on a surface of a mounting substrate; and a conductive material formed on the ground, configured to connect the metal layer and the ground metal.Type: GrantFiled: August 2, 2004Date of Patent: September 6, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Toru Sugiyama, Kouhei Morizuka, Masayuki Sugiura, Yasuhiko Kuriyama, Yoshikazu Tanabe
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Patent number: 6936550Abstract: A manufacturing method for a semiconductor integrated circuit device comprises forming, over a gate insulating film which has been formed over the main surface of a single crystal silicon substrate to have an effective film thickness less than 5 nm in terms of SiO2, a W film as a gate electrode material, and heat treating the silicon substrate in a water-vapor- and hydrogen-containing gas atmosphere having a water vapor/hydrogen partial pressure ratio set at a ratio permitting oxidation of silicon without substantial oxidation of the W film, whereby defects of the gate insulating film right under the W film are repaired. In this way, in a MISFET having a metal gate electrode formed over a ultra-thin gate insulating film having an effective film thickness less than 5 nm in terms of SiO2, defects of the gate insulating film can be repaired without oxidizing the metal gate electrode.Type: GrantFiled: January 21, 2004Date of Patent: August 30, 2005Assignee: Hitachi, Ltd.Inventors: Naoki Yamamoto, Yoshikazu Tanabe
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Publication number: 20050185172Abstract: A surface inspection apparatus and a method for inspecting the surface of a sample are capable of inspecting discriminatingly between scratches of various configuration and adhered foreign objects that occur on the surface of a work target when the work target (for example, an insulating film on a semiconductor substrate) is subjected to a polishing process such as CMP or a grinding process, in semiconductor manufacturing process or magnetic head manufacturing process. In the invention, the scratch and foreign object that occur on the polished or ground surface of the sample is epi-illuminated and slant-illuminated by use of approximately same light flux, the difference between the scattered light intensity from the shallow scratch and from the foreign object is applied to thereby discriminate between the shallow scratch and the foreign object, and the directionality of the scattered light is detected to discriminate between the linear scratch and the foreign object.Type: ApplicationFiled: April 13, 2005Publication date: August 25, 2005Inventors: Ichiro Ishimaru, Minori Noguchi, Ichiro Moriyama, Yoshikazu Tanabe, Yasuo Yatsugake, Yukio Kenbou, Kenji Watanabe, Hirofumi Tsuchiyama