Patents by Inventor Yoshikazu Tanabe

Yoshikazu Tanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6894302
    Abstract: The invention provides a surface inspection apparatus and a method for inspecting the surface of a sample that are capable of inspecting discriminatingly between the scratch of various configuration and the adhered foreign object that occur on the surface of a work target when the work target (for example, an insulating film on a semiconductor substrate) is subjected to polishing process such as CMP or grinding process in semiconductor manufacturing process or magnetic head manufacturing process.
    Type: Grant
    Filed: February 26, 2001
    Date of Patent: May 17, 2005
    Assignees: Hitachi, Ltd., Hitachi High-Tech Electronics Engineering Co., Ltd.
    Inventors: Ichiro Ishimaru, Minori Noguchi, Ichiro Moriyama, Yoshikazu Tanabe, Yasuo Yatsugake, Yukio Kenbou, Kenji Watanabe, Hirofumi Tsuchiyama
  • Patent number: 6855642
    Abstract: A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vicinity of a semiconductor wafer, and forming a thin oxide film serving as a gate insulating film of an MOS transistor and having a thickness of 5 nm or below on the main surface of the semiconductor wafer at an oxide film-growing rate sufficient to ensure fidelity in formation of an oxide film and uniformity in thickness of the oxide film.
    Type: Grant
    Filed: April 28, 2003
    Date of Patent: February 15, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Yoshikazu Tanabe, Satoshi Sakai, Nobuyoshi Natsuaki
  • Publication number: 20050006742
    Abstract: A high frequency semiconductor module, includes: a semiconductor chip having top and bottom surfaces; a semiconductor element merged in the semiconductor chip; a ground pad of the semiconductor element disposed on the top surface; a metal layer configured to connect to the ground pad and extend to sidewalls of the semiconductor chip; a ground metal arranged on a surface of a mounting substrate; and a conductive material formed on the ground, configured to connect the metal layer and the ground metal.
    Type: Application
    Filed: August 2, 2004
    Publication date: January 13, 2005
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Toru Sugiyama, Kouhei Morizuka, Masayuki Sugiura, Yasuhiko Kuriyama, Yoshikazu Tanabe
  • Publication number: 20040259339
    Abstract: In order to provide a light oxidation process technique for use in a CMOS LSI employing a polymetal gate structure and a dual gate structure, so that both oxidation of a refractory metal film constituting a part of a gate electrode and diffusion of boron contained in a p-type polycrystalline silicon film constituting a part of the gate electrode can be prevented, a mixed gas containing a hydrogen gas and steam synthesized from an oxygen gas and a hydrogen gas is supplied to a major surface of a semiconductor wafer A1, and a heat treatment for improving a profile of a gate insulating film that has been cut by etching under an edge part of the gate electrode is conducted under a low thermal load condition in that the refractor metal film is substantially not oxidized, and boron contained in a p-type polycrystalline silicon film constituting a part of the gate electrode is not diffused to the semiconductor substrate through the gate oxide film.
    Type: Application
    Filed: July 22, 2004
    Publication date: December 23, 2004
    Inventors: Yoshikazu Tanabe, Naoki Yamamoto, Shinichiro Mitani, Yuko Hanaoka
  • Publication number: 20040198067
    Abstract: With a view to preventing the oxidation of a metal film at the time of light oxidation treatment after gate patterning and at the same time to making it possible to control the reproducibility of oxide film formation and homogeneity of oxide film thickness at gate side-wall end portions, in a gate processing step using a poly-metal, a gate electrode is formed by patterning a gate electrode material which has been deposited over a semiconductor wafer 1A having a gate oxide film formed thereon and has a poly-metal structure and then, the principal surface of the semiconductor wafer 1A heated to a predetermined temperature or vicinity thereof is supplied with a hydrogen gas which contains water at a low concentration, the water having been formed from hydrogen and oxygen by a catalytic action, to selectively oxidize the principal surface of the semiconductor wafer 1A, whereby the profile of the side-wall end portions of the gate electrode is improved.
    Type: Application
    Filed: April 12, 2004
    Publication date: October 7, 2004
    Inventors: Yoshikazu Tanabe, Isamu Asano, Makoto Yoshida, Naoki Yamamoto, Masayoshi Saito, Nobuyoshi Natsuaki
  • Patent number: 6790694
    Abstract: A high frequency semiconductor module, includes: a semiconductor chip having top and bottom surfaces; a semiconductor element merged in the semiconductor chip; a ground pad of the semiconductor element disposed on the top surface; a metal layer configured to connect to the ground pad and extend to sidewalls of the semiconductor chip; a ground metal arranged on a surface of a mounting substrate; and a conductive material formed on the ground, configured to connect the metal layer and the ground metal.
    Type: Grant
    Filed: October 28, 2002
    Date of Patent: September 14, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toru Sugiyama, Kouhei Morizuka, Masayuki Sugiura, Yasuhiko Kuriyama, Yoshikazu Tanabe
  • Patent number: 6784116
    Abstract: With a view to preventing the oxidation of a metal film at the time of light oxidation treatment after gate patterning and at the same time to making it possible to control the reproducibility of oxide film formation and homogeneity of oxide film thickness at gate side-wall end portions, in a gate processing step using a poly-metal, a gate electrode is formed by patterning a gate electrode material which has been deposited over a semiconductor wafer 1A having a gate oxide film formed thereon and has a poly-metal structure and then, the principal surface of the semiconductor wafer 1A heated to a predetermined temperature or vicinity thereof is supplied with a hydrogen gas which contains water at a low concentration, the water having been formed from hydrogen and oxygen by a catalytic action, to selectively oxidize the principal surface of the semiconductor wafer 1A, whereby the profile of the side-wall end portions of the gate electrode is improved.
    Type: Grant
    Filed: January 31, 2003
    Date of Patent: August 31, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Yoshikazu Tanabe, Isamu Asano, Makoto Yoshida, Naoki Yamamoto, Masayoshi Saito, Nobuyoshi Natsuaki
  • Patent number: 6784038
    Abstract: In order to provide a light oxidation process technique for use in a CMOS LSI employing a polymetal gate structure and a dual gate structure, so that both oxidation of a refractory metal film constituting a part of a gate electrode and diffusion of boron contained in a p-type polycrystalline silicon film constituting a part of the gate electrode can be prevented, a mixed gas containing a hydrogen gas and steam synthesized from an oxygen gas and a hydrogen gas is supplied to a major surface of a semiconductor wafer A1, and a heat treatment for improving a profile of a gate insulating film that has been cut by etching under an edge part of the gate electrode is conducted under a low thermal load condition in that the refractor metal film is substantially not oxidized, and boron contained in a p-type polycrystalline silicon film constituting a part of the gate electrode is not diffused to the semiconductor substrate through the gate oxide film.
    Type: Grant
    Filed: August 15, 2001
    Date of Patent: August 31, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Yoshikazu Tanabe, Naoki Yamamoto, Shinichiro Mitani, Yuko Hanaoka
  • Publication number: 20040161945
    Abstract: A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vicinity of a semiconductor wafer, and forming a thin oxide film serving as a gate insulating film of an MOS transistor and having a thickness of 5 nm or below on the main surface of the semiconductor wafer at an oxide film-growing rate sufficient to ensure fidelity in formation of an oxide film and uniformity in thickness of the oxide film.
    Type: Application
    Filed: February 10, 2004
    Publication date: August 19, 2004
    Inventors: Yoshikazu Tanabe, Satoshi Sakai, Nobuyoshi Natsuaki
  • Publication number: 20040157468
    Abstract: A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vicinity of a semiconductor wafer, and forming a thin oxide film serving as a gate insulating film of an MOS transistor and having a thickness of 5 nm or below on the main surface of the semiconductor wafer at an oxide film-growing rate sufficient to ensure fidelity in formation of an oxide film and uniformity in thickness of the oxide film.
    Type: Application
    Filed: February 10, 2004
    Publication date: August 12, 2004
    Inventors: Yoshikazu Tanabe, Satoshi Sakai, Nobuyoshi Natsuaki
  • Publication number: 20040157467
    Abstract: A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vicinity of a semiconductor wafer, and forming a thin oxide film serving as a gate insulating film of an MOS transistor and having a thickness of 5 nm or below on the main surface of the semiconductor wafer at an oxide film-growing rate sufficient to ensure fidelity in formation of an oxide film and uniformity in thickness of the oxide film.
    Type: Application
    Filed: February 10, 2004
    Publication date: August 12, 2004
    Inventors: Yoshikazu Tanabe, Satoshi Sakai, Nobuyoshi Natsuaki
  • Publication number: 20040152340
    Abstract: Described is a manufacturing method for a semiconductor integrated circuit device which comprises forming, over a gate insulating film which has been formed over the main surface of a single crystal silicon substrate to have an effective film thickness less than 5 nm in terms of SiO2, a W film as a gate electrode material, and heat treating the silicon substrate in a water-vapor- and hydrogen-containing gas atmosphere having a water vapor/hydrogen partial pressure ratio set at a ratio permitting oxidation of silicon without substantial oxidation of the W film, whereby defects of the gate insulating film rightly under the W film are repaired. According to the present invention, in a MISFET having a metal gate electrode formed over a ultra-thin gate insulating film having an effective film thickness less than 5 nm in terms of SiO2, defects of the gate insulating film can be repaired without oxidizing the metal gate electrode.
    Type: Application
    Filed: January 21, 2004
    Publication date: August 5, 2004
    Inventors: Naoki Yamamoto, Yoshikazu Tanabe
  • Publication number: 20040112172
    Abstract: A sintered alloy that enables the reducing of coefficient of friction and the sealing of pores on a surface thereof and a method of manufacturing the same. A sintered alloy body includes a resin film layer and pores. The pores define a porosity ranging from 2 to 35 volume %, each having an inlet portion and an inside portion, defining a pore inlet diameter and a pore inside diameter respectively. The pore inlet diameter ranges from 10 to 200 &mgr;m, and an average ratio of the pore inlet diameter to the pore inside diameter is at least. Solid lubricant is dispersed in the resin film layer. After forming the layer 3, it is pressed against the sintered alloy body. Thus, the layer enters into the pores to closely contact them, thereby sealing the pores, reducing the coefficient of friction due to the solid lubricant.
    Type: Application
    Filed: September 10, 2003
    Publication date: June 17, 2004
    Applicants: MITSUBISHI MATERIALS CORPORATION, Nihon Parkerizing Co., Ltd.
    Inventors: Teruo Shimizu, Tsuneo Maruyama, Yoshikazu Tanabe, Atsunori Kodama, Motoki Higuchi
  • Patent number: 6737341
    Abstract: A manufacturing method for a semiconductor intergraded circuit device comprises forming, over a gate insulating film which has been formed over a gate insulating film which has been formed over the main surface of a single crystal silicon substrate to have an effective film thinkness less than 5 nm in terms of SiO2, a W film as a gate electrode material, and heat treating the silicon substrate in a water-vapor- and hydrogen-containing gas atmosphere having a water vapor/hydrogen partial pressure ratio set at a ratio permitting oxidation of silicon without substantial oxidation of the W film, whereby defects of the gate insulating film right under the W film are repaired. In this way, in a MISFET having a metal gate electrode formed over a ultra-thin gate insulating film having an effective film thinkness less than 5 nm in term of SiO2, defectes of the gate insulating film can be repaired without oxidizing the metal gate electrode.
    Type: Grant
    Filed: May 25, 2000
    Date of Patent: May 18, 2004
    Assignee: Renesas Technology Corporation
    Inventors: Naoki Yamamoto, Yoshikazu Tanabe
  • Patent number: 6733732
    Abstract: A reactor comprising a body made of a heat-resistant material and having an inlet and an outlet for water/moisture gas, having a gas-diffusing member provided in an internal space of the body, and having a platinum coating on an internal wall surface of the body. Hydrogen and oxygen fed from the inlet are diffused by the gas-diffusing member and then come into contact with the platinum coating to enhance reactivity, thereby producing water. A temperature of the reactor is held to be below an ignition temperature of hydrogen or a hydrogen-containing gas. The platinum-coated catalyst layer on the internal wall of the reactor body is formed by treating the surface of the internal wall of the body, cleaning the treated surface, forming a barrier coating of a nonmetallic material of an oxide or nitride on the wall surface, and forming the platinum coating on the barrier coating.
    Type: Grant
    Filed: February 15, 2001
    Date of Patent: May 11, 2004
    Assignees: Fujikin Incorporated
    Inventors: Tadahiro Ohmi, Koji Kawada, Yoshikazu Tanabe, Takahisa Nitta, Nobukazu Ikeda, Akihiro Morimoto, Keiji Hirao, Hiroshi Morokoshi, Yukio Minami
  • Patent number: 6723665
    Abstract: In a gas-phase treating process of a semiconductor wafer using hydrogen, there is provided a technique for safely eliminating the hydrogen in an exhaust gas discharged from a gas-phase treating apparatus. The profile at the end portions of the side walls of gate electrodes of a poly-metal structure is improved by forming the gate electrodes over a semiconductor wafer IA having a gate oxide film and then by supplying the semiconductor wafer 1A with a hydrogen gas containing a low concentration of water, as generated from hydrogen and oxygen by catalytic action, to oxidize the principal face of the semiconductor wafer 1A selectively. After this, the hydrogen in the exhaust gas, as discharged from an oxidizing furnace, is completely converted into water by causing it to react with oxygen by a catalytic method.
    Type: Grant
    Filed: April 2, 2003
    Date of Patent: April 20, 2004
    Assignees: Renesas Technology Corp., Hitachi Tokyo Electronics Co., Ltd.
    Inventors: Yoshikazu Tanabe, Toshiaki Nagahama, Nobuyoshi Natsuaki, Yasuhiko Nakatsuka
  • Publication number: 20040051153
    Abstract: Formation of an WNx film 24 constituting a barrier layer of a gate electrode 7A having a polymetal structure is effected in an atmosphere containing a high concentration nitrogen gas, whereby release of N (nitrogen) from the WNx film 24 is suppressed in the heat treatment step after the formation of the gate electrode 7A.
    Type: Application
    Filed: August 20, 2003
    Publication date: March 18, 2004
    Inventors: Naoki Yamamoto, Yoshikazu Tanabe, Hiroshige Kogayu, Takehiko Yoshida
  • Publication number: 20040036167
    Abstract: A high frequency semiconductor module, includes: a semiconductor chip having top and bottom surfaces; a semiconductor element merged in the semiconductor chip; a ground pad of the semiconductor element disposed on the top surface; a metal layer configured to connect to the ground pad and extend to sidewalls of the semiconductor chip; a ground metal arranged on a surface of a mounting substrate; and a conductive material formed on the ground, configured to connect the metal layer and the ground metal.
    Type: Application
    Filed: October 28, 2002
    Publication date: February 26, 2004
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Toru Sugiyama, Kouhei Morizuka, Masayuki Sugiura, Yasuhiko Kuriyama, Yoshikazu Tanabe
  • Publication number: 20030219995
    Abstract: A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vicinity of a semiconductor wafer, and forming a thin oxide film serving as a gate insulating film of an MOS transistor and having a thickness of 5 nm or below on the main surface of the semiconductor wafer at an oxide film-growing rate sufficient to ensure fidelity in formation of an oxide film and uniformity in thickness of the oxide film
    Type: Application
    Filed: April 28, 2003
    Publication date: November 27, 2003
    Inventors: Yoshikazu Tanabe, Satoshi Sakai, Nobuyoshi Natsuaki
  • Publication number: 20030203646
    Abstract: In a gas-phase treating process of a semiconductor wafer using hydrogen, there is provided a technique for safely eliminating the hydrogen in an exhaust gas discharged from a gas-phase treating apparatus. The profile at the end portions of the side walls of gate electrodes of a poly-metal structure is improved by forming the gate electrodes over a semiconductor wafer IA having a gate oxide film and then by supplying the semiconductor wafer 1A with a hydrogen gas containing a low concentration of water, as generated from hydrogen and oxygen by catalytic action, to oxidize the principal face of the semiconductor wafer 1A selectively. After this, the hydrogen in the exhaust gas, as discharged from an oxidizing furnace, is completely converted into water by causing it to react with oxygen by a catalytic method.
    Type: Application
    Filed: April 2, 2003
    Publication date: October 30, 2003
    Inventors: Yoshikazu Tanabe, Toshiaki Nagahama, Nobuyoshi Natsuaki, Yasuhiko Nakatsuka