Abstract: An A/D conversion circuit includes: a reference signal generation section that includes an integrator circuit having a first constant current source and generates a reference signal that changes in accordance with a constant current output by the first constant current source; a comparison section that executes a comparison process between an analog signal and the reference signal and terminates the comparison process; a clock generation section that includes a delay section having delay units for delaying an input signal for a predetermined time and outputting delayed input signals in accordance with a constant current output by a second constant current source, and outputs a lower phase signal based on the signals output from the delay units; a latch section that latches the lower phase signal at a timing related to the termination of the comparison process; and a count section that counts a clock based on the lower phase signal.

Abstract: An imaging element includes: a plurality of pixels configured to receive light from outside and generate and output an imaging signal depending on an amount of the light received; a first transfer line connected to the pixel; a second transfer line; a column selection switch configured to select one pixel column and output the imaging signal to the second transfer line; a column source follower including a gate to which the imaging signal transferred by the first transfer line is input, a drain end being connected to a power supply voltage, and a source end being connected to the column selection switch; a constant current source configured to drive the column source follower and read out the imaging signal to the second transfer line; and a current generating unit configured to flow a predetermined current to the source end side of the column source follower.

Abstract: An imaging apparatus includes a clock generation unit that generates a plurality of phase signals having phases different from one another, a signal transmission unit provided to correspond to the plurality of phase signals and having a plurality of signal transmission circuits, and a latch unit having a plurality of latch circuits that latches the phase signals transmitted by the signal transmission unit at a timing of an end of a comparison process performed by a comparison unit. A configuration of the signal transmission circuit that transmits a first phase signal is substantially the same as a configuration of the signal transmission circuit that transmits a second phase signal different from the first phase signal. A configuration of the latch circuit that latches the first phase signal is substantially the same as a configuration of the latch circuit that latches the second phase signal.

Abstract: An imaging device includes: an imaging section in which a plurality of unit pixels having a photoelectric conversion element are arranged in the form of a matrix; a reference signal generating section configured to generate a reference signal that increases or decreases with a passage of time; a comparison section that includes a differential amplifier including a first input terminal electrically connected to the reference signal generating section and a second input terminal electrically connected to the unit pixels and configured to compare voltages of the first input terminal and the second input terminal and is arranged for each column or for a plurality of columns of a pixel array of the imaging section; and a measurement section configured to measure a comparison time from when the comparison section starts comparison until the comparison ends and generate data corresponding to the comparison time.

Abstract: A solid-state imaging apparatus includes a plurality of photoelectric conversion sections configured to generate a signal charge according to an amount of an incident light and disposed in a matrix, a first accumulation section configured to accumulate the signal charge, a first transfer section configured to transfer the signal charge from the photoelectric conversion sections to the first accumulation section, a second accumulation section configured to accumulate the signal charge accumulated in the first accumulation section, a second transfer section configured to transfer the signal charge accumulated in the first accumulation section to the second accumulation section, a reset section configured to reset the signal charge accumulated in the second accumulation section, an output section configured to output a signal according to the signal charge accumulated in the second accumulation section, and first and second control sections configured to control each section for every row or column.

Abstract: An AD conversion circuit and a solid-state imaging apparatus reduce the occurrence of errors in encoding a lower phase signal while securing a degree of freedom of selection of a count clock. A detection circuit performs an operation of detecting logic states of m (m is a natural number of 2 or more) lower phase signals in a signal group that a plurality of lower phase signals latched by the latch unit is arranged, while selecting the m lower phase signals in a predetermined order so that the order thereof becomes the same as the order of the signal group and outputs a state detection signal at the time of detecting that the logic states of the m lower phase signals are in a predetermined logic state in the detection operation. The predetermined order is defined depending on a predetermined signal and an encoding method.

Abstract: An AD conversion circuit may include: a reference signal generation unit; a comparison unit; a clock generation unit; a latch unit; a counting unit; and an encoding unit including a detection circuit and an encoding circuit, the detection circuit performing a first detection operation of detecting logic states of n lower phase signals in a signal group that a plurality of lower phase signals latched in the latch unit are arranged in the same order as those of the signal group when the plurality of lower phase signals output from the clock generation unit are arranged to be the signal group the detection circuit outputting a state detection signal when the logic state of the n lower phase signals is detected to be a predetermined logic state in the first detection operation, the encoding circuit performing encoding based on the state detection signal output from the detection circuit.

Abstract: An imaging apparatus includes a clock generation unit that generates a plurality of phase signals having phases different from one another, a signal transmission unit provided to correspond to the plurality of phase signals and having a plurality of signal transmission circuits, and a latch unit having a plurality of latch circuits that latches the phase signals transmitted by the signal transmission unit at a timing of an end of a comparison process performed by a comparison unit. A configuration of the signal transmission circuit that transmits a first phase signal is substantially the same as a configuration of the signal transmission circuit that transmits a second phase signal different from the first phase signal. A configuration of the latch circuit that latches the first phase signal is substantially the same as a configuration of the latch circuit that latches the second phase signal.

Abstract: In an imaging device, one end of a capacitive element is connected to a second input terminal to which a reference signal Ramp is applied, and the other end of the capacitive element is connected to a voltage source during a reset operation and to a voltage source after the reset operation through a switching element. As a result, the voltage of the second input terminal is changed such that a voltage difference between the first input terminal and the second input terminal becomes a voltage guaranteeing a comparison operation after the reset operation.

Abstract: An imaging apparatus capable of reducing deterioration of AD conversion accuracy is provided, wherein, when performing the AD conversion on a pixel signal corresponding to a reset level, a latch control unit causes a latch circuit of a latch unit to enter an enabled state (third timing) at a first timing according to a comparison start in a comparing unit, and then causes the latch circuit of the latch unit to execute latching at a fourth timing at which a predetermined time has lapsed from a second timing according to a comparison end in the comparing unit. Further, when performing the AD conversion on the pixel signal corresponding to the signal level, the latch control unit causes the latch circuit of the latch unit to enter the enabled state at the second timing according to the comparison end in the comparing unit.

Abstract: An A/D conversion circuit includes a reference signal generation unit, a comparison unit, a delay circuit, a latch unit, an arithmetic circuit, a lower counter, and an upper counter including a second binary counter performing counting using the count clock based on one of the output signals constituting the first lower phase signal, performs counting to acquire a first upper count value, inverts values of respective bits constituting the first upper count value, performs counting using the count clock based on of the output signals constituting the second lower phase signal, and performs counting based on the second upper count clock to acquire a second upper count value, and having a data protection function for protecting an upper count value held by the second binary counter at a time of count clock switching, wherein digital data corresponding to a difference between the first and second analog signals is acquired.

Abstract: A time detection circuit may include: a delay unit configured to have a plurality of delay units, each of which delays and outputs an input signal, and start an operation at a first timing relating to an input of a first pulse; a latch unit configured to latch logic states of the plurality of delay units; a count unit configured to perform a count operation based on a clock output from one of the plurality of delay units; a count latch unit configured to latch a state of the count unit; and a latch control unit configured to enable the latch unit at a second timing relating to an input of a second pulse and cause the latch unit and the count latch unit to execute a latch at a third timing at which a predetermined time has elapsed from the second timing.

Abstract: An imaging device and an endoscopic device can be further miniaturized. A vertical selection unit simultaneously resets charge accumulation units of a plurality of pixels, and then a horizontal selection unit sequentially selects a plurality of first pixel signals corresponding to voltages of the charge accumulation units of the plurality of pixels and inputs the first pixel signals to an output unit. Further, a vertical selection unit simultaneously transfers the signal charges generated by the charge generation units in the plurality of pixels to the charge accumulation units, and then a horizontal selection unit sequentially selects a plurality of second pixel signals corresponding to the voltages of the charge accumulation units of the plurality of pixels and inputs the second pixel signals to the output unit.

Abstract: A ramp section generates a reference signal. A comparison section compares an analog signal to the reference signal, and terminates a comparison process at a timing at which the reference signal has satisfied a predetermined condition for the analog signal. A main count section performs a count operation and outputs a count value. A latch section latches a second count value at a second timing related to the end of the comparison process corresponding to a second analog signal after latching a first count value at a first timing related to the end of the comparison process corresponding to a first analog signal. A column count section sequentially counts values of bits constituting the second count value retained in the latch section after an initial value has been set on the basis of values of bits constituting the first count value retained in the latch section.

Abstract: In an A/D converter, a ramp unit generates a reference signal that increases or decreases over time. A comparison unit starts a comparison process of comparing an analog signal to the reference signal at a timing related to input of the analog signal and ends the comparison process at a timing at which the reference signal satisfies a predetermined condition with respect to the analog signal. A VCO includes a plurality of delay units having the same configuration and starts a transition process at a timing related to the start of the comparison process. A count unit counts a clock from the VCO. A low-order latch unit latches a low-order logic state, which is a logic state of the plurality of delay units, at a first timing related to the end of the comparison process. A high-order latch unit latches a high-order logic state.

Abstract: An AD conversion circuit may include: a reference signal generation unit generating a reference signal increasing or decreasing with passage of time; a comparison unit including a first comparison circuit and a second comparison circuit comparing an analog signal to be subjected to an AD conversion with the reference signal; a clock generation unit including a delay circuit in which a plurality of delay units are connected to one another, and outputting a first lower phase signal and a second lower phase signal based on clock signals output from each of the plurality of delay units; a latch unit including a first latch circuit latching a logical state of the first lower phase signal and a second latch circuit latching a logical state of the second lower phase signal; and a counting unit performing counting based on the second lower phase signal output from the clock generation unit.

Abstract: A reference signal generating circuit, an AD conversion circuit, and an imaging device are provided. A clock generating unit includes a delay section including delay units, each of which delays an input signal and outputs a delayed signal, and outputs a low-order phase signal based on a signal output from the delay section. A high-order current source cell unit includes high-order current source cells, each of which generates the same constant current. A low-order current source cell unit includes low-order current source cells weighted to generate constant currents having current values that differ by a predetermined proportion of a current value of the constant current generated by the high-order current source cell. Selection of the high-order current source cell is performed based on a clock obtained by dividing a clock based on the low-order phase signal.

Abstract: An image pickup device may include an image pickup unit in which unit pixels having photoelectric conversion elements are arranged, the unit pixels outputting pixel signals, a reference signal generation unit, a comparison unit that includes a differential amplifier unit and a reset unit, the differential amplifier unit comparing a voltage of the first input terminal to a voltage of the second input terminal, a measurement unit that measures a comparison time of the comparison unit from a comparison start to a comparison end, and a change unit that changes the voltage of the first input terminal so that a voltage difference between the first input terminal and the second input terminal is set to a voltage at which a comparison operation by the comparison unit is ensured after a reset operation by the reset unit.

Abstract: A clock generation circuit includes first and second logic circuits and a switch circuit. The first logic circuit has a first circuit threshold value lower than a circuit threshold value of a front-stage circuit, receives an input clock output from the front-stage circuit, and outputs a first output signal in accordance with a logic state of the input clock and the first circuit threshold value. The second logic circuit has a second circuit threshold value higher than the circuit threshold value of the front-stage circuit, receives the input clock output from the front-stage circuit, and outputs a second output signal in accordance with the logic state of the input clock and the second circuit threshold value. The switch circuit receives the first and second output signals and outputs, as an output clock, one of first and second voltages corresponding to different logic states.

Abstract: An image pickup device may include an image pickup unit in which a plurality of pixels are arranged, the plurality of pixels outputting a first and second pixel signals, and an analog-to-digital (AD) conversion circuit that outputs a digital difference signal. The AD conversion circuit may include a delay circuit that has a plurality of delay devices, the delay circuit outputting a first and second lower phase signals, a latch unit that latches the first and second lower phase signals, a lower counting unit that generates a first and second lower count signals, the lower counting unit generating and outputting a lower difference signal, and a higher counting unit that generates a higher difference signal, subtracts a predetermined number from the higher difference signal, or adds the predetermined number to the higher difference signal, and outputs the higher difference signal after subtraction or addition processing.