Abstract: A ramp section generates a reference signal. A comparison section compares an analog signal to the reference signal, and terminates a comparison process at a timing at which the reference signal has satisfied a predetermined condition for the analog signal. A main count section performs a count operation and outputs a count value. A latch section latches a second count value at a second timing related to the end of the comparison process corresponding to a second analog signal after latching a first count value at a first timing related to the end of the comparison process corresponding to a first analog signal. A column count section sequentially counts values of bits constituting the second count value retained in the latch section after an initial value has been set on the basis of values of bits constituting the first count value retained in the latch section.

Abstract: A clock generating circuit in which a plurality of stages of inverting circuits are connected, a start signal that causes start of clock generation and an output signal from the inverting circuit of a predetermined stage are input to one of the inverting circuits, an element having impedance that changes in accordance with a magnitude of an object analog signal that is an object of conversion to a digital signal is provided between the adjacent inverting circuits, generates a clock of a frequency in accordance with the magnitude of the object analog signal. A counter counts the number of clocks generated by the clock generating circuit and outputs a count value.

Abstract: An analog-to-digital converter may include an annular delay circuit that includes a plurality of delay units connected in an annular shape, each of the plurality of delay units delaying a pulse current that is input to each of the plurality of delay units, a current source that outputs an electric current, in accordance with an input analog signal, to selected delay units, which is selected from among the plurality of delay units, and a digital signal generation unit that generates a digital signal in accordance with a number of circulations per predetermined period of time of the pulse current circulating around the annular delay circuit.

Abstract: In an A/D converter, a ramp unit generates a reference signal that increases or decreases over time. A comparison unit starts a comparison process of comparing an analog signal to the reference signal at a timing related to input of the analog signal and ends the comparison process at a timing at which the reference signal satisfies a predetermined condition with respect to the analog signal. A VCO includes a plurality of delay units having the same configuration and starts a transition process at a timing related to the start of the comparison process. A count unit counts a clock from the VCO. A low-order latch unit latches a low-order logic state, which is a logic state of the plurality of delay units, at a first timing related to the end of the comparison process. A high-order latch unit latches a high-order logic state.

Abstract: An A/D conversion circuit includes a reference signal generation unit, a comparison unit, a delay circuit, a latch unit, an arithmetic circuit, a lower counter, and an upper counter including a second binary counter performing counting using the count clock based on one of the output signals constituting the first lower phase signal, performs counting to acquire a first upper count value, inverts values of respective bits constituting the first upper count value, performs counting using the count clock based on of the output signals constituting the second lower phase signal, and performs counting based on the second upper count clock to acquire a second upper count value, and having a data protection function for protecting an upper count value held by the second binary counter at a time of count clock switching, wherein digital data corresponding to a difference between the first and second analog signals is acquired.

Abstract: An image pickup device may include an image pickup unit in which unit pixels having photoelectric conversion elements are arranged, the unit pixels outputting pixel signals, a reference signal generation unit, a comparison unit that includes a differential amplifier unit and a reset unit, the differential amplifier unit comparing a voltage of the first input terminal to a voltage of the second input terminal, a measurement unit that measures a comparison time of the comparison unit from a comparison start to a comparison end, and a change unit that changes the voltage of the first input terminal so that a voltage difference between the first input terminal and the second input terminal is set to a voltage at which a comparison operation by the comparison unit is ensured after a reset operation by the reset unit.

Abstract: A solid state image pickup device may include a pixel unit that includes a plurality of pixels; a pulse delay unit that includes a plurality of delay elements, each of the plurality of delay elements including a power supply terminal; a stop control unit; a stop signal delay unit; a lower bit latch unit; a counter unit; a first upper bit latch unit; a second upper bit latch unit; and a correcting unit that compares an output signal of the first upper bit latch unit with an output signal of the second upper bit latch unit, and corrects a count value, which is a count result of the counter unit, based on a comparison result and an output signal of the lower bit latch unit.

Abstract: An image pickup device may include an image pickup unit in which a plurality of pixels are arranged, the plurality of pixels outputting a first and second pixel signals, and an analog-to-digital (AD) conversion circuit that outputs a digital difference signal. The AD conversion circuit may include a delay circuit that has a plurality of delay devices, the delay circuit outputting a first and second lower phase signals, a latch unit that latches the first and second lower phase signals, a lower counting unit that generates a first and second lower count signals, the lower counting unit generating and outputting a lower difference signal, and a higher counting unit that generates a higher difference signal, subtracts a predetermined number from the higher difference signal, or adds the predetermined number to the higher difference signal, and outputs the higher difference signal after subtraction or addition processing.

Abstract: Disclosed is a time AD converter which is provided with an annular delay circuit, a digital signal generation unit, and an annular delay circuit control unit. The annular delay circuit has n delay units (where n is a natural number equal to or larger than 2). The digital signal generation unit generates a digital signal corresponding to an analog signal by using an output of the annular delay circuit. The annular delay circuit control unit controls a current which is input to the n delay units in accordance with an external environmental signal.

Abstract: A frequency converting unit 101 includes a connection circuit for connecting a plurality of inverting circuits through which a delay time between an input signal and an output signal is changed according to a magnitude of the signal output by the image pickup unit, and one or a plurality of switch elements which are connected between an output terminal of the inverting circuit and an input terminal of another inverting circuit not adjacent to the inverting circuit, and generates a clock signal having a frequency according to the connection circuit. The control unit 20 controls the switch elements included in the frequency converting unit 101 to open and close. The count unit 103 counts the clock signal generated by the frequency converting unit.

Abstract: A solid-state image pickup device may include: an image pickup unit in which a plurality of pixels are arranged in a matrix; a sample-and-hold unit having a switch element and a capacitance element; a frequency conversion unit in which a plurality of stages of inverting circuits are connected, the pixel signal is supplied to the first power supply terminal, and a start signal for starting clock generation and an output signal from the inverting circuit of a predetermined stage are input to one of the inverting circuits; a counting unit that counts the clock output from the frequency conversion unit; and a buffer circuit provided between a first terminal of the capacitance element connected to the switch element and the first power supply terminal, wherein a second terminal of the capacitance element is connected to the second power supply terminal.

Abstract: A solid-state image pickup apparatus includes: an image pickup portion in which are arranged a plurality of pixels with a photo-electric conversion element, the pixels which generate and output a signal in accordance with the intensity of an incident electromagnetic wave; a frequency conversion portion that includes a link circuit in which a plurality of inversion circuits with a first terminal and a second terminal are linked in a ring, each of the inversion circuits having a varying delay time from an input signal to an output signal based on the voltage difference between the voltage supplied to the first terminal and the voltage supplied to the second terminal, and the frequency conversion portion which generate clock pulses at a frequency based on the voltage difference; a count portion which counts the clock pulses generated by the frequency conversion portion; and a transistor including: a third terminal to which is input a predetermined voltage; a fourth terminal connected to the first terminals; and

Abstract: Provided are a data selection circuit, a data transmission circuit, a ramp wave generation circuit, and a solid-state imaging device. A delay section delays signals input to delay units of n (n is a natural number equal to or more than 3) stages that are connected to each other and have the same configuration and outputs delayed signals from the delay units. A delay control section controls a delay amount of the delay units. An output section performs a logical operation on signals output from i-th and j-th (i and j are natural numbers that are different from each other and equal to or more than 1 and equal to or less than n) delay units to generate a signal and outputs the signal to a k-th (k is a natural number equal to or more than 1 and equal to or less than m) first data selection pulse input terminal of a functional circuit having m (m is a natural number equal to or more than 2) first data selection pulse input terminals.

Abstract: A solid-state imaging apparatus including: an imaging section having pixels arranged into a matrix; a conversion section for digitizing pixel signals; a block memory section formed of a first line memory corresponding to at least N lines (N being an integral number of 2 or more) for retaining the pixel signals; and a drive control section for controlling so as to read out and cause to be retained at the block memory section pixel signals corresponding to M lines (M being an integral number between 2 and N inclusive) in a period shorter than period necessary for an external circuit to process pixel signals corresponding to 1 line, and then controlling so as to bring into halt condition at least one of imaging section and conversion section in a remaining period in the period necessary for external circuit to process pixel signals corresponding to M lines.

Abstract: An analog-to-digital converter may include an annular delay circuit that includes a plurality of delay units connected in an annular shape, each of the plurality of delay units delaying a pulse current that is input to each of the plurality of delay units, a current source that outputs an electric current, in accordance with an input analog signal, to selected delay units, which is selected from among the plurality of delay units, and a digital signal generation unit that generates a digital signal in accordance with a number of circulations per predetermined period of time of the pulse current circulating around the annular delay circuit.

Abstract: A solid-state imaging apparatus including: an image section having a plurality of pixel units arranged into a matrix, each pixel unit having at least one subunit consisting of an electric charge generation means for generating signal electric charges corresponding to the amount of incident electromagnetic wave and a signal transfer means for transferring signal electric charges generated by the electric charge generation means, an electric charge accumulation means for accumulating the transferred signal electric charges, a first reset means for resetting the electric charge accumulation means, an amplification means for amplifying a signal corresponding to signal electric charges accumulated at the electric charge accumulation means, and a select means for selectively outputting the amplified signal to a vertical signal line; and a signal transfer assisting means for making a gradient of potential in the vicinity of the electric charge generation means toward the signal transfer means to be greater at the ti

Abstract: A data processing method may include counting one of a plurality of clock signals with a first mode, counting clock signals based on a predetermined number of the plurality of clock signals with the first mode, to output a first clock signal every time a counter value becomes a first predetermined value, counting the first clock signal with the first mode, counting one of the clock signals with a second mode while the counted value is considered as a first initial value, counting clock signals based on the predetermined number of the plurality of clock signals with the second mode, to output a second clock signal every time the counter value becomes a second predetermined value while the counted value is considered as a second initial value, counting the second clock signal with the second mode, and outputting the counter values with the second mode as difference data between a first data signal and a second data signal.

Abstract: A clock generating circuit in which a plurality of stages of inverting circuits are connected, a start signal that causes start of clock generation and an output signal from the inverting circuit of a predetermined stage are input to one of the inverting circuits, an element having impedance that changes in accordance with a magnitude of an object analog signal that is an object of conversion to a digital signal is provided between the adjacent inverting circuits, generates a clock of a frequency in accordance with the magnitude of the object analog signal. A counter counts the number of clocks generated by the clock generating circuit and outputs a count value.

Abstract: An A/D conversion circuit includes: a pulse transit circuit into which either a power supply or current source and also a pulse signal is input, and through which the pulse signal transits; a transit position detection section that detects a transit position of the pulse signal within the pulse transit circuit, and outputs data in accordance with the transit position; and a digital data creation section that, based on the data output by the transit position detection section, creates digital data that corresponds to the size of the power supply or current source. The pulse transit circuit is formed by a plurality of inverter circuits that are joined together in series, and the plurality of inverter circuits are formed by identical logical elements in which delay times between input signals and output signals change in accordance with the size of the power supply or current source.

Abstract: A pixel portion of an image pick-up device having a pixel portion of pixels arranged in matrix converting a subject image to an electric signal, and a scanning unit of sub-scanning circuits outputting a video signal, a first scanning circuit selecting a pixel position in a first matrix direction and a second scanning circuit selecting a pixel position in a second direction intersecting the first direction. One of the first and second scanning circuits shares the signal lines. The image pick-up device includes a scanning control circuit controlling the first and second scanning circuits. The pixel area structures of the pickup device are uniform, the wirings are uniform, and the vertical and horizontal driving systems and an output system are uniform. Thus, pixel signals outputted from two output systems have no property differences and image quality is improved.