Abstract: The present invention provides a warp-knit slide fastener in which a fastener element row can be easily knitted into and attached stably and firmly on a fastener tape, and fastener elements of the fastener element row are not separated from each other due to pushing up of a fastener face.The successive fastener element row is knitted, simultaneously with knitting of the fastener tape, into a fastener element attaching portion at longitudinally side edge portion of the fastener tape, and is fixed by two wales or more of fixing chain stitch yarns. Respective needle loops of the respective fixing chain stitch yarns push respective element leg portions of the successive fastener element row from above toward a foundation structure. Respective sinker loop groups form a part of the foundation structure on which the successive fastener element line is disposed. Warp in-laid yarns are warp inserted through at least a part of sinker loops of the sinker loop groups while being intermingled.

Abstract: A semiconductor memory device comprises two memory cell arrays (1a, 1b) in which a block divisional operation is performed. Two spare rows (2a, 2b) are provided corresponding to the two memory cell arrays (1a, 1b). Spare row decoders (5a, 5b) are provided for selecting the spare rows (2a, 2b), respectively. One spare row decoder selecting signal generation circuit (18) used in common by the spare row decoders (5a, 5b) is provided. The spare row decoder selecting signal generation circuit (18) can be previously set so as to generate a spare row decoder selecting signal (SRE) when a defective row exists in either of the memory cell arrays (1a, 1b) and the defective row is selected by row decoder groups (4a, 4b). Each of the spare row decoders (5a, 5b) is activated in response to the spare row decoder selecting signal (SRE) and a block control signal.

Abstract: A multiplicity of knitting needles and one or more knitting needles are slid vertically along first and second needle beds, respectively, which are disposed in a back-to-back relationship with and spaced a predetermined distance from each other. The second needle bed extends along only one end portion of the first needle bed. And at the same time, a predetermined number of knitting yarn guides are swung and shogged. During that time, a monofilament bending means disposed near one end of the first needle bed reciprocates along the upper space between the first and second needle beds at an underlapping position to continuously form individual fastener elements by bending the monofilament and to knit the formed fastener elements successively in a warp-knit fastener tape by the back-to-back needles in the first and second needle beds simultaneously with the knitting of the tape.

Abstract: A necessary number of knitting needles are slid at a predetermined timing along a multiplicity of parallel sliding grooves of a single needle bed, and a predetermined number of knitting yarn guides take lapping movements to form desired stitches of the knitting yarns while a monofilament bending means between one end of the needle bed and the yarn guides is operated at a predetermined timing for reciprocating along a predetermined number of knitting yarns at an underlapping position. During this reciprocating movement, a head-portion-holding member is moved between a holding position for holding a head portion of each fastener element from an inside thereof and a non-holding position, in synchronism with the bending of a monofilament.

Abstract: Each of divided bit line pairs is selectively connected to a sub-input/output line pair through transfer gates. A register is connected to the sub-input/output line pair. Data is transferred through the sub-input/output line pair between the register and a selected bit line pair. A sense amplifier is connected to each of the bit line pairs. Sense amplifiers are independently driven by separate sense amplifier activating signals. Therefore, even if data is transferred to the selected bit line pair from the register, fluctuations in potential on the bit line pair caused in such a case does not affect a sense amplifier activating signal connected to a non-selected bit line pair. As a result, data stored in the non-selected memory cell is prevented from being destroyed.

Abstract: A semiconductor memory device operable for reading and writing in a normal mode and in a test mode is divided into memory cell sections each having blocks of memory cells. Data bus lines are connected to the respective blocks, and switches interconnect data bus lines connected to blocks of the different sections. The switch are made conductive during reading and writing in the normal mode and during writing in the test mode, and nonconductive during reading in the test mode. Input data are applied onto the data bus lines connected one of the blocks for writing in the blocks of the sections simultaneously during writing in the normal mode and in the test mode. In the normal mode, data are read out of the blocks of the sections through the data bus lines connected to the above-mentioned one of the blocks. In the test mode, the data are read out of the blocks of the sections through the data bus lines connected to the respective blocks.

Abstract: In a knit slide fastener in which a continuous fastener element row is knitted in a fastener element attaching marginal portion of each of fastener tapes simultaneously with the knitting of the fastener tape, the fastener element attaching marginal portion includes a plurality of parallel binding chain stitch yarns extending longitudinally of the marginal portion for holding the fastener element row to the marginal portion. One of the binding chain stitch yarns, which is adjacent to coupling heads of fastener elements, is larger in size than the remaining binding stitch yarns.

Abstract: A knit slide fastener stringer including a fastener tape knitted in a warp-knit ground structure and having along one longitudinal edge an element-attaching portion, and a continuous fastener element row knitted in and along the element-attaching portion of the fastener tape and secured by two or more wales of anchoring chain stitch yarns simultaneously with the knitting of the fastener tape. In this knit slide fastener stringer, successive needle loops of each of the two or more wales formed of the anchoring chain stitch yarns press the continuous fastener element row toward the warp-knit structure of said fastener tape from the upper side, and successive sinker loops constitute part of the ground structure. And a number of warp-inlaid yarns are each laid in and interlaced with at least part of the successive sinker loops. The result is that the ground structure of the element-attaching marginal portion is kept in accurate size to prevent the coupled fastener element rows from locally splitting.

Abstract: A knit slide fastener stringer comprising: a fastener tape knit in a warp-knit ground structure and having along one longitudinal edge an element-attaching marginal portion, and a continuous fastener element row knitted in and along the element-attaching marginal portion of the fastener tape and secured by anchoring chain stitch yarns of at least two wales simultaneously with the knitting of the fastener tape. In the slide fastener stringer, an additional anchoring chain stitch yarn independent from the anchoring chain stitch yarns is disposed between the anchoring chain stitch yarns near the coupling head portions and successive coupling head portions, extending warpwise over the fastener element row. And a connecting yarn extending weftwise substantially diagonally in gaps between adjacent fastener elements from the upper side to the lower side connects the additional anchoring chain stitch yarn with the ground structure of the fastener tape.

Abstract: A warp-knit tape has through its entire width tricot-stitch yarns formed of multifilament yarns and single-cord-stitch knitting yarns formed of textured yarns. A fastener-element-attaching portion of the warp-knit tape includes chain-stitch knitting yarns formed of multifilament yarns and warp in-laid yarns formed of multifilament yarns, with an outer one of the chain-stitch knitting yarns being thick. An outer one of the tricot-stitch knitting yarns and an outer one of the single-cord-stitch yarns in the web portion are thick to reinforce the edge. Thus, the resulting fastener-element-attaching portion is non-stretchable, while the resulting web portion is stretchable.

Abstract: In a knit slide fastener in which a continuous fastener element row is knitted in a fastener element attaching portion of each fastener tape simultaneously with the knitting of the fastener tape, a plurality of laid-in weft yarns are knitted in the warp-knit structure of the fastener element attaching portion so as to turn alternately in every course and to be interlaced with knit loops of a chain stitch extending along the outermost edge of the fastener element attaching portion, and the fastener element row is secured to the ground structure of the attaching portion by two binding chain stitches.

Abstract: A cathode material for a lithium ion secondary battery comprises a compound of the formulaLi.sub.1-X-a A.sub.X Ni.sub.1-Y-b B.sub.Y O.sub.2.wherein:A is an alkaline earth metal component selected from the group consisting of (1) at least two of magnesium, calcium, strontium and barium, (2) strontium alone and (3) barium alone;B is at least one transition metal element other than Ni;X is the total number of moles of A and if A consists of more than one alkaline earth metal element, then X is the total number of moles of all alkaline earth metal elements;Y is the total number of moles of B and if B consists of more than one transition metal element, then Y is the total number of moles of all transition metal elements; andX, Y, a and b satisfy the respective equations:0<X.ltoreq.0.100<Y.ltoreq.0.30-0.10.ltoreq.a.ltoreq.0.10-0.15.ltoreq.b.ltoreq.0.15.

Abstract: A semiconductor memory device operable for reading and writing in a normal mode and in a test mode is divided into memory cell sections each having blocks of memory cells. Data bus lines are connected to the respective blocks, and switches interconnect data bus lines connected to blocks of the different sections. The switch are made conductive during reading and writing in the normal mode and during writing in the test mode, and nonconductive during reading in the test mode. Input data are applied onto the data bus lines connected one of the blocks for writing in the blocks of the sections simultaneously during writing in the normal mode and in the test mode. In the normal mode, data are read out of the blocks of the sections through the data bus lines connected to the above-mentioned one of the blocks. In the test mode, the data are read out of the blocks of the sections through the data bus lines connected to the respective blocks.

Abstract: A knit slide fastener comprises: a warp-knit fastener tape having along one longitudinal edge a fastener-element-mounting marginal portion; and a row of continuous fastener elements knitted in the fastener-element-mounting marginal portion simultaneously with the knitting of the warp-knit fastener tape; the fastener-element-mounting marginal portion including anchoring chain stitches knitted of a plurality of parallel knitting yarns for pressing down successive legs of the continuous fastener elements, and a plurality of anchoring weft inlaid yarns laid in weftwise in a zigzag pattern and between the parallel knitting yarns of the anchoring chain stitches, the anchoring weft inlaid yarns being interlaced with the chain stitches.

Abstract: A semiconductor memory device comprises a DRAM memory cell array comprising a plurality of dynamic type memory cells arranged in a plurality of rows and columns, and an SRAM memory cell array comprising static type memory cells arranged in a plurality of rows and columns. The DRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns. The SRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns, corresponding to the plurality of blocks in the DRAM memory cell array. The SRAM memory cell array is used as a cache memory. At the time of cache hit, data is accessed to the SRAM memory cell array. At the time of cache miss, data is accessed to the DRAM memory cell array. On this occasion, data corresponding to one row in each of the blocks in the DRAM memory cell array is transferred to one row in the corresponding block in the SRAM memory cell array.

Abstract: In a warp-knit tape for a slide fastener, an element-mounting edge portion comprises a reinforcing core, a double-face chain stitches knitted of two yarns on opposite sides of the core, a weft inlaid structure in which a plurality of weft yarns extending between and laid in the two chain stitches symmetrically on the front and back sides, and part of a ground knit structure of a tape web portion. The chain stitches are knitted alternately with the front and back sides of the element-mounting edge portin, and the symmetrical weft yarns are laid respectively in the front and back sides of the element-mounting edge portion. The web portion has a single-face knit structure knitted by the knitting needles on only one of the front and back sides. The resulting element-mounting edge portion has a substantially rectangular cross section.

Abstract: A slide fastener tape woven or knitted so as to form a coupling element attaching edge portion, a tape body portion and a tape sewing portion arranged in order transversely of the tape, wherein the tape has a double-layer structure portion composed of a front cloth and a back cloth joined together by a connecting yarn with a predetermined gap therebetween extending transversely over a predetermined region of the tape, the connecting yarn being a synthetic resin monofilament or multifilament, the back cloth of the double-layer structure portion being a section formed of at least a mesh woven or knitted fabric.

Abstract: A semiconductor memory device of folded bit line structure provided with a cross portion in at least one portion of each of bit line pairs so that values of coupling capacitance with adjacent bit line pairs are equal to each other with respect to the paired bit lines.Preferably, the respective bit line pairs are equally divided into 4N and the cross parts are provided at dividing points so that bit line pairs having the cross parts at the same dividing points are arranged on alternate pairs of bit lines.Preferably, the cross parts are provided in regions for forming restore circuits or sense amplifiers.More preferably, a dummy word line for selecting dummy cells for providing reference potential is selected by the position of a selected word line.

Abstract: A knit slide fastener including a fastener tape composed of a warp-knit ground structure and having an element-supporting portion along one longitudinal edge thereof, and a row of continuous coupling elements knit into and along the element-supporting portion as the fastener tape is knit, wherein two threads are knit as binding chain stitches of a double-knit structure into the element-supporting portion, each of the binding chain-stitch threads having a series off upper needle loops binding legs of the row of continuous coupling elements, and a series of lower needle loops intertwined with needle loops of corresponding chain-stitch threads forming a part of the ground structure. With this arrangement, the element-supporting portion is made tight and has a fine knit structure which will insure attachment of the of coupling elements to the element-supporting portion with high dimensional stability.

Abstract: A cache DRAM (100) includes a DRAM memory array (11) accessed by a row address signal and a column address signal, an SRAM memory array (21) accessed by the column address signal, and an ECC circuit (30). The DRAM memory array (11) is divided into a plurality of blocks (B1 to B64), each including a plurality of columns. The SRAM memory array (21) includes 4 ways (W1 to W4). In determining a cache hit/cache miss, a column address signal is inputted. Consequently, the SRAM memory array (21) is accessed and data are read from each of the ways. When a cache hit occurs, one way is selected in response to an externally applied way address signal, and data from that way are outputted. When a cache miss occurs, the column address signal is latched and the row address signal is applied. The DRAM array (11) is accessed in accordance with the row address signal and the latched column address signal.