Patents by Inventor Yoshio Sakai
Yoshio Sakai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6721591Abstract: A plurality of electrodes for measuring electrocardiogarphic waveforms are attached on body surface positions that constitute a subset of the standard 12-lead system. The measured electrocardiogarphic waveforms of said subset of said standard 12-lead system are used to calculate the electrocardiogarphic waveforms of remaining leads in the said standard 12-lead system. The measured and calculated electrocardiographic waveforms are synthesized to form a standard 12-lead electrocardiogram. The invention is capable of monitoring the 12-lead electrocardiogram with a reduced number of electrodes, wherein a portion of waveforms are directly measured and used as primary information for diagnosing heart disease, and the other portion of waveforms are derived from the measured leads and are used as a secondary information for improving the accuracy of diagnosis.Type: GrantFiled: July 24, 2001Date of Patent: April 13, 2004Assignees: Nihon Kohden Corporation, Daming Wei of the University of Aizu Faculty HouseInventors: Daming Wei, Takeshi Kojima, Tadashi Nakayama, Yoshio Sakai
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Publication number: 20030205751Abstract: A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacity portions to be arranged very densely and a sufficiently large capacity to be maintained with very small cell areas. Since the storage capacity portions are formed even on the bit lines, the bit lines are shielded, so that the capacity decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacity portion so that a part of thereof has a form of a wall substantially vertical to the substrate in order to increase the capacity.Type: ApplicationFiled: June 11, 2003Publication date: November 6, 2003Applicant: Hitachi, Ltd.Inventors: Shinichiro Kimura, Naotaka Hashimoto, Yoshio Sakai, Tokuo Kure, Yoshifumi Kawamoto, Toru Kaga, Eiji Takeda
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Publication number: 20020045837Abstract: A plurality of electrodes for measuring electrocardiogarphic waveforms are attached on body surface positions that constitute a subset of the standard 12-lead system. The measured electrocardiogarphic waveforms of said subset of said standard 12-lead system are used to calculate the electrocardiogarphic waveforms of remaining leads in the said standard 12-lead system. The measured and calculated electrocardiographic waveforms are synthesized to form a standard 12-lead electrocardiogram. The invention is capable of monitoring the 12-lead electrocardiogram with reduced number of electrodes, wherein a portion of waveforms are directly measured and used as primary information for diagnosing heart disease, and the other portion of waveforms are derived from the measured leads and are used as a secondary information for improving the accuracy of diagnosis.Type: ApplicationFiled: July 24, 2001Publication date: April 18, 2002Applicant: NIHON KOHDEN CORPORATIONInventors: Daming Wei, Takeshi Kojima, Tadashi Nakayama, Yoshio Sakai
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Publication number: 20010008288Abstract: A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacity portions to be arranged very densely and a sufficiently large capacity to be maintained with very small cell areas. Since the storage capacity portions are formed even on the bit lines, the bit lines are shielded, so that the capacity decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacity portion so that a part of thereof has a form of a wall substantially vertical to the substrate in order to increase the capacity.Type: ApplicationFiled: December 18, 2000Publication date: July 19, 2001Applicant: Hitachi, Ltd.Inventors: Shinichiro Kimura, Naotaka Hashimoto, Yoshio Sakai, Tokuo Kure, Yoshifumi Kawamoto, Toru Kaga, Eiji Takeda
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Patent number: 5892190Abstract: Elevator group supervisory control method and system for group supervisory control of a plurality of elevators serving a plurality of floors. The method and apparatus of the invention permits the inputting of qualitative requests (guidance), from the user, concerning elevator operation into the group supervisory control system. Qualitative requests concerning elevator operation are set in the form of guidance (or request) targets. The thus set request targets are converted into control targets for the elevators. Actual group supervisory control is executed using the control targets.Type: GrantFiled: October 12, 1993Date of Patent: April 6, 1999Assignee: Hitachi, Ltd.Inventors: Yuzo Morita, Toshimitsu Tobita, Kiyoshi Nakamura, Atsuya Fujino, Soshiro Kuzunuki, Kotaro Hirasawa, Yoshio Sakai, Kenji Yoneda, Takaaki Ueshima, Yuji Toda, Hiromi Inaba
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Patent number: 5772602Abstract: A CPU 9 controls an air supplying/discharging device to set a pressure of air within a-cuff to 60 mmHg for 60 seconds before making a blood pressure measurement, detects pulse waves of the cuff pressure for such period of time, and calculates a degree of stability of the detected pulse waves. When a blood pressure measurement is made, the CPU reduces the cuff pressure by a step pressure reducing operation whose step duration corresponds to the calculated degree of stability.Type: GrantFiled: November 13, 1996Date of Patent: June 30, 1998Assignee: Nihon Kohden CorporationInventors: Yoshio Sakai, Toshichika Kaji
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Patent number: 5700705Abstract: The manufacture of a memory cell of the type employing a pair of cross-coupled CMOS inverters of a SRAM is disclosed in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETs. The manufacture of each load MISFET consists of forming source, drain and channel regions within the same polycrystalline silicon film, and a gate electrode consisting of a different layer conductive film, such as a polycrystalline film, than that of the drive MISFETs. The manufacture of the memory cell having such a stacked arrangement, facilitates the patterning of the source (drain) region and gate electrode of each load MISFET thereof to have an overlapping relationship with each other so as to increase the effective capacitance associated with each of the memory cell storage nodes.Type: GrantFiled: June 6, 1995Date of Patent: December 23, 1997Assignee: Hitachi, Ltd.Inventors: Satoshi Meguro, Kiyofumi Uchibori, Norio Suzuki, Makoto Motoyoshi, Atsuyoshi Koike, Toshiaki Yamanaka, Yoshio Sakai, Toru Kaga, Naotaka Hashimoto, Takashi Hashimoto, Shigeru Honjou, Osamu Minato
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Patent number: 5699807Abstract: A pressure sensor gathers discrete data representing the pulse amplitude of a pulse wave signal when a cuff pressure is increased and decreased. A RAM stores the discrete data of the pulse amplitude. A CPU processes the discrete data by using a spline function, to thereby generate the data representative of a smooth continuous line passing by points of the pulse amplitude of the discrete data. This process reduces a variation of the pulse amplitude of a pulse wave signal, to thereby minimize a variation of the blood pressure values. An inflection point of the smooth continuous line is used as a diastolic blood pressure value.Type: GrantFiled: July 26, 1995Date of Patent: December 23, 1997Assignee: Nihon Kohden CorporationInventors: Jun Motogi, Yoshio Sakai, Sunao Takeda
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Patent number: 5646423Abstract: A memory cell of the type a pair of cross-coupled CMOS inverters of a SRAM is disclosed in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETS. Each load MISFET of a memory cell consists of a source, drain and channel region formed within the same polycrystalline silicon film, and a gate electrode consisting of a different layer conductive film than that of the drive MISFETs. In a memory cell having such a stacked arrangement, the source (drain) region and gate electrode of each load MISFET thereof are patterned to have an overlapping relationship with each other so as to increase the effective capacitance associated with each of the memory cell storage nodes.Type: GrantFiled: June 6, 1995Date of Patent: July 8, 1997Assignee: Hitachi, Ltd.Inventors: Satoshi Meguro, Kiyofumi Uchibori, Norio Suzuki, Makoto Motoyoshi, Atsuyoshi Koike, Toshiaki Yamanaka, Yoshio Sakai, Toru Kaga, Naotaka Hashimoto, Takashi Hashimoto, Shigeru Honjou, Osamu Minato
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Patent number: 5619055Abstract: A memory cell of the type employing a pair of cross-coupled CMOS inverters of a SRAM is disclosed in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETs. Each load MISFET of a memory cell consists of a source, drain and channel region formed of a semiconductor strip, such as a polycrystalline silicon film strip, and a gate electrode consisting of a different layer conductive film than that of the drive MISFETs. In a memory cell having such a stacked arrangement, the source region and gate electrode of each load MISFET thereof are patterned to have a widely overlapping relationship with each other to form a capacitor element thereacross such that an increase in the overall capacitance associated with each of the memory cell storage nodes is effected thereby decreasing occurrence of soft error.Type: GrantFiled: April 27, 1995Date of Patent: April 8, 1997Assignee: Hitachi, Ltd.Inventors: Satoshi Meguro, Kiyofumi Uchibori, Norio Suzuki, Makoto Motoyoshi, Atsuyoshi Koike, Toshiaki Yamanaka, Yoshio Sakai, Toru Kaga, Naotaka Hashimoto, Takashi Hashimoto, Shigeru Honjou, Osamu Minato
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Patent number: 5591998Abstract: A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacity portions to be arranged very densely and a sufficiently large capacity to be maintained with very small cell areas. Since the storage capacity portions are formed even on the bit lines, the bit lines are shielded, so that the capacity decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacity portion so that a part of thereof has a form of a wall substantially vertical to the substrate in order to increase the capacity.Type: GrantFiled: May 17, 1995Date of Patent: January 7, 1997Assignee: Hitachi, Ltd.Inventors: Shinichiro Kimura, Naotaka Hashimoto, Yoshio Sakai, Tokuo Kure, Yoshifumi Kawamoto, Toru Kaga, Eiji Takeda
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Patent number: 5584299Abstract: A CPU of a control unit receives a blood pressure pulse wave signal, through an AC amplifier and an A/D convertor. The CPU differentiates, for the smoothing of the waveform, the heart pulse wave signal every step of decreasing the pressure in the cuff, thereby detecting a descending zero-cross point m of the differential wave. Further, the CPU detects a slope peak point P' while tracing back from the descending zero-cross point m. The CPU determines the peak points of the pulse wave by using the heart pulse wave signal that is not differentiated. Thereafter, the CPU determines the base points of the pulse wave tracing back from the maximum-slope point, determines the peak value of the heart pulse wave signal in all the steps of decreasing the pressure in the cuff, and finally computes a systolic blood pressure and a diastolic blood pressure.Type: GrantFiled: July 26, 1995Date of Patent: December 17, 1996Assignee: Nihon Kohden CorporationInventors: Yoshio Sakai, Jun Motogi, Sunao Takeda
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Patent number: 5583358Abstract: A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacity portions to be arranged very densely and a sufficiently large capacity to be maintained with very small cell areas. Since the storage capacity portions are formed even on the bit lines, the bit lines are shielded, so that the capacity decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacity portion so that a part of thereof has a form of a wall substantially vertical to the substrate in order to increase the capacity.Type: GrantFiled: October 17, 1994Date of Patent: December 10, 1996Assignee: Hitachi, Ltd.Inventors: Shinichiro Kimura, Naotaka Hashimoto, Yoshio Sakai, Tokuo Kure, Yoshifumi Kawamoto, Toru Kaga, Eiji Takeda
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Patent number: 5483083Abstract: A memory cell of the type employing a pair of cross-coupled CMOS inverters of a SRAM is provided in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETs. Each load MISFET of a memory cell consists of a source, drain and channel region formed of a semiconductor strip, such as a polycrystalline silicon film strip, and a gate electrode consisting of a different layer conductive film than that of the drive MISFETs. A wiring line, formed as a separate conductive layer, is provided in the stacking arrangement of the drive and load MISFETs of a memory cell for applying a ground potential to source regions of the drive MISFETs thereof.Type: GrantFiled: March 9, 1993Date of Patent: January 9, 1996Assignee: Hitachi, Ltd.Inventors: Satoshi Meguro, Kiyofumi Uchibori, Norio Suzuki, Makoto Motoyoshi, Atsuyoshi Koike, Toshiaki Yamanaka, Yoshio Sakai, Toru Kaga, Naotaka Hashimoto, Takashi Hashimoto, Shigeru Honjou, Osamu Minato
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Patent number: 5409085Abstract: The present invention relates to a group control elevator system which has been adjusted to operate in response to a state of utilizing elevator cars. In a group control elevator system which carries out a control of allocating elevator cars to elevator car calls for serving many floors by using an evaluation function having a plurality of variable parameters, targets for elevator control performance are inputted, a traffic flow to which elevator car demand belongs is judged, variable parameters to be adjusted which have been set in advance for each combination of said targets and traffic flows are stored, stored variable parameters are adjusted, adjustment sequence of variable parameters to be adjusted is stored, and a plurality of variable parameters are sequentially adjusted according to the stored sequence. By the above arrangement, only desired parameters to be adjusted are selected and adjusted out of a plurality of variable parameters for desired targets and traffic flows.Type: GrantFiled: November 24, 1993Date of Patent: April 25, 1995Assignee: Hitachi, Ltd.Inventors: Atsuya Fujino, Toshimitsu Tobita, Hiromi Inaba, Kiyoshi Nakamura, Yoshio Sakai, Kenji Yoneda, Hiroaki Yamani
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Patent number: 5389749Abstract: An elevator system which is provided with power converters, electric motors supplied with power from the power converters, and a torque distributing section having functions for determining allocation of output power from the power converters on the basis of a required torque, by which an elevator is operated on the basis of functions selected in accordance with the operation mode. The system is able to save power in the elevator operation and also improve control functions and increase system capacity.Type: GrantFiled: June 24, 1992Date of Patent: February 14, 1995Assignees: Hitachi, Ltd., Hitachi Building Systems Engineering And Service Co., Ltd.Inventors: Sadao Hokari, Kiyoshi Nakamura, Hiromi Inaba, Yoshio Sakai, Hideaki Takahashi, Seikichi Masuda, Takei Ando, Toshiaki Kurosawa, Akihiro Nokita, Masahiro Konya
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Patent number: 5376104Abstract: In a defibrillator with an electrocardiographic monitor which monitors electrocardiographic signals induced at electrodes by means of a preamplifier and supplying the signals to an electrocardiographic signal processing circuit through high-pass filters, the dynamic range of a preamplifier is made wider in accordance with the amplitude of a polarization voltage which is developed when a defibrillator is operated. A high-pass filter is formed of a first high-pass filter which operates in a normal state and a second high-pass filter whose blocking frequency is higher than that of the first high-pass filter so that the polarization voltage is attenuated without erasing the electrocardiographic signals. The second high-pass filter is operated in synchronization with the operation of the defibrillator during a time period corresponding to the time period in which the polarization voltage is generated.Type: GrantFiled: February 2, 1993Date of Patent: December 27, 1994Assignee: Nihon Kohden CorporationInventors: Yoshio Sakai, Ikuhiro Tsumura, Nobutaka Kobayashi
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Patent number: 5374576Abstract: A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacity portions to be arranged very densely and a sufficiently large capacity to be maintained with very small cell areas. Since the storage capacity portions are formed even on the bit lines, the bit lines are shielded, so that the capacity decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacity portion so that a part of thereof has a form of a wall substantially vertical to the substrate in order to increase the capacity.Type: GrantFiled: June 3, 1993Date of Patent: December 20, 1994Assignee: Hitachi, Ltd.Inventors: Shinichiro Kimura, Naotaka Hashimoto, Yoshio Sakai, Tokuo Kure, Yoshifumi Kawamoto, Toru Kaga, Eiji Takeda
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Patent number: 5346977Abstract: A method of applying a skin-protective composition which comprises an acrylic copolymer which comprises(A) 40 to 85% by weight of an alkyl acrylate,(B) 5 to 50% by weight of an alkyl methacrylate, and(C) 10 to 30% by weight of a mono-ethylenically unsaturated monomer having a carboxyl group, and a medium, which can effectively block irritative materials and be easily removed from a skin.Type: GrantFiled: April 26, 1993Date of Patent: September 13, 1994Assignees: Shionogi & Co., Ltd., Nissin Chemical Industry Co., Ltd.Inventors: Yoshio Sakai, Izumi Saitoh
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Patent number: 5307903Abstract: Elevator group supervisory control method and system for group supervisory control of a plurality of elevators serving a plurality of floors. The method and apparatus of the invention permits the inputting of qualitative requests (guidance), from the user, concerning elevator operation into the group supervisory control system. Qualitative requests concerning elevator operation are set in the form of guidance (or request) targets. The thus set request, targets are converted into control targets for the elevators. Actual group supervisory control is executed using the control targets.Type: GrantFiled: January 26, 1989Date of Patent: May 3, 1994Assignee: Hitachi, Ltd.Inventors: Yuzo Morita, Toshimitsu Tobita, Kiyoshi Nakamura, Atsuya Fujino, Soshiro Kuzunuki, Kotaro Hirasawa, Yoshio Sakai, Kenji Yoneda, Takaaki Ueshima, Yuji Toda, Hiromi Inaba