Patents by Inventor Yoshiro Aoki

Yoshiro Aoki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7333079
    Abstract: In an active matrix organic EL display including a drive control element which has a first terminal connected to a first power supply terminal, a control terminal, and a second terminal which outputs a driving current having a magnitude corresponding to the voltage between the first terminal and the control terminal, a capacitor which has one electrode connected to the control terminal and can maintain the voltage between the first terminal and the control terminal constant, and an organic EL element connected between the second terminal and a second power supply terminal, a plurality of switches connected in series are used as switches between the second terminal and the control terminal to obtain a perfect nonconductive state, and the switch on the control terminal side is set in the nonconductive state earlier than the remaining switch, thereby decreasing the potential shift amount generated by the capacitance of the switches themselves.
    Type: Grant
    Filed: July 22, 2005
    Date of Patent: February 19, 2008
    Assignee: Toshiba Matsushita Display Technology Co., Ltd.
    Inventors: Makoto Shibusawa, Yoshiro Aoki, Hirondo Nakatogawa
  • Patent number: 7329947
    Abstract: When a two-division structure heat treatment jig for semiconductor substrate that includes a silicon first jig that comes into direct contact with a semiconductor substrate that is heat treated and supports the semiconductor substrate, and a second jig (holder) that holds the first jig and is mounted on a heat treatment boat is adopted as a heat treatment boat of a vertical heat treatment furnace, the stress concentrated during the heat treatment on a particular portion of the semiconductor substrate can be reduced; in the case of a semiconductor substrate large in the tare stress and having an outer shape of 300 mm being heat treated, or even in the case of the heat treatment being carried out under very high temperature conditions, the slips can be suppressed from occurring. The present invention can be widely applied as a stable heat treatment method of semiconductor substrates.
    Type: Grant
    Filed: January 5, 2004
    Date of Patent: February 12, 2008
    Assignee: Sumitomo Mitsubishi Silicon Corporation
    Inventors: Naoshi Adachi, Kazushi Yoshida, Yoshiro Aoki
  • Patent number: 7324351
    Abstract: Provided is a wiring board including an insulating substrate with a first region and a second region adjacent to each other on a major surface, signal line groups arrayed on the first region, and connection portions arranged on the second region in correspondence with the signal line groups, wherein each connection portion includes first to third terminal groups, a first wiring line group connecting the first terminal group to the corresponding signal line group, a second wiring line group connected to the second terminal group, and a third wiring group connected to the third terminal group, wherein the second and third wiring line groups are connected to each other between each adjacent connection portions, and all of the connection portions are the same in shapes of the first to third terminal groups and the first to third wiring line groups.
    Type: Grant
    Filed: July 6, 2005
    Date of Patent: January 29, 2008
    Assignee: Toshiba Matsushita Display Technology Co., Ltd.
    Inventor: Yoshiro Aoki
  • Patent number: 7286109
    Abstract: Buffer circuits are provided between outputs of a scanning line driver circuit and scanning lines. The buffer circuits each are configured to make rise or fall time of scanning signals at output sides of the buffer circuits substantially the same as or longer than those of the scanning signals at end terminals of the scanning lines when the scanning signals supplied to the scanning lines are rectangular in waveform.
    Type: Grant
    Filed: May 17, 2004
    Date of Patent: October 23, 2007
    Assignee: Toshiba Matsushita Display Technology Co., Ltd.
    Inventor: Yoshiro Aoki
  • Publication number: 20070238269
    Abstract: It is an object of the present invention to provide a method for manufacturing SIMOX wafer, wherein roughness Rms of a measurement area of 10 square micrometers in a surface of an SOI layer and roughness Rms of a measurement area of 10 square micrometers in an interface between the SOI layer and a BOX layer can be reduced respectively and a SIMOX obtained by the method. The method is to manufacture a SIMOX wafer comprising; a step of forming a first ion-implanted layer 12 containing highly concentrated oxygen within a wafer 11; a step of forming a second ion-implanted amorphous layer 13; and a high temperature heat treatment step of transforming the first and second ion-implanted layers into a BOX layer 15 by holding the wafer at a temperature between 1300° C.
    Type: Application
    Filed: April 3, 2007
    Publication date: October 11, 2007
    Inventors: Yoshiro Aoki, Riyuusuke Kasamatsu, Yukio Komatsu
  • Publication number: 20070224774
    Abstract: A SIMOX wafer is produced by implanting an oxygen ions into a surface of a Si substrate and then conducting a high-temperature annealing, in which an atmosphere in at least an end stage of the high-temperature annealing treatment is an Ar or N2 atmosphere containing an oxygen of more than 3 volume % but not more than 10 volume %.
    Type: Application
    Filed: March 27, 2007
    Publication date: September 27, 2007
    Applicant: SUMCO CORPORATION
    Inventors: Yoshio Murakami, Riyuusuke Kasamatsu, Yoshiro Aoki
  • Publication number: 20070196995
    Abstract: There is obtained an MLD-SIMOX wafer having a BOX layer with a thin film thickness that allows a reduction in SOI layer surface roughness and interface roughness of the BOX layer and the SOI layer and an improvement in breakdown voltage. In a method for manufacturing a SIMOX wafer comprising a step of forming a first ion-implanted layer in a silicon wafer; a step of forming a second ion-implanted layer that is in an amorphous state; and a high-temperature heat treatment state of maintaining the wafer in an atmosphere containing oxygen at a temperature that is not lower than 1300° C. but lower than a silicon melting point to change the first and the second ion-implanted layers into a BOX layer, the method is characterized in that a dose amount for the first ion-implanted layer is 1.25 to 1.5×1017 atoms/cm2, a dose amount for the second ion-implanted layer is 1.0×1014 to 1×1016 atoms/cm2, a step of preheating the wafer to a temperature that is not lower than 50° C. but lower than 200° C.
    Type: Application
    Filed: February 21, 2007
    Publication date: August 23, 2007
    Inventors: Yoshiro Aoki, Bong-Gyun Ko
  • Patent number: 7253069
    Abstract: A method for manufacturing a SOI wafer includes a step of heat-treating a wafer in a furnace to form an SOI wafer including a silicon support, an insulating layer containing oxide, and a superficial silicon layer arranged in that order and a step of unloading the SOI wafer from the furnace maintained at a temperature of 250° C. to 800° C. to transfer the SOI wafer to an atmosphere containing hydrogen or water. The steps are performed in that order.
    Type: Grant
    Filed: April 8, 2005
    Date of Patent: August 7, 2007
    Assignee: Sumitomo Mitsubishi Silicon Corporation
    Inventors: Yoshio Murakami, Toru Yamazaki, Yoshiro Aoki, Akihiko Endo
  • Publication number: 20070178680
    Abstract: A SIMOX wafer having a BOX layer with a thin film thickness is obtained without a reduction in productivity or deterioration in quality. In a method for manufacturing a SIMOX wafer comprising: a step of forming a first ion-implanted layer in a silicon wafer; a step of forming a second ion-implanted layer that is in an amorphous state; and a high-temperature heat treatment step of maintaining the wafer in an oxygen contained atmosphere at a temperature that is not lower than 1300° C. but less than a silicon melting point for 6 to 36 hours to change the first and the second ion-implanted layers into a BOX layer, a gas containing chlorine that is not less than 0.1 volume % but less than 1.0 volume % is mixed into an atmosphere during temperature elevation in the high-temperature heat treatment.
    Type: Application
    Filed: February 2, 2007
    Publication date: August 2, 2007
    Inventors: Yoshiro Aoki, Yukio Komatsu, Tetsuya Nakai, Seiichi Nakamura
  • Publication number: 20070160066
    Abstract: In a write period, a write current is caused to flow through a video signal line in a first state where a first control terminal and an output terminal of a drive control element, a second control terminal of a drive control element, and a video signal line are connected one another and a potential of a scan signal line is set at a first potential, and the potential of the scan signal line is shifted from the first potential to a second potential in a second state where the first and second control terminals, the output terminal, and the video signal line are disconnected from one another are sequentially executed. In a effective display period, a drive current is caused to flow through a display element while keeping the potential of the scan signal line at the second potential.
    Type: Application
    Filed: March 16, 2007
    Publication date: July 12, 2007
    Inventor: Yoshiro Aoki
  • Publication number: 20070128838
    Abstract: A method for producing an SOI substrate, comprising: implanting oxygen ions into a silicon substrate; heat treating the silicon substrate in an inert atmosphere containing oxygen; and forming a buried oxide film in the silicon substrate, wherein the inert gas contains argon and nitrogen.
    Type: Application
    Filed: January 30, 2007
    Publication date: June 7, 2007
    Inventor: Yoshiro Aoki
  • Publication number: 20070020949
    Abstract: One embodiment of this method for manufacturing a SIMOX wafer includes: while heating a silicon wafer, implanting oxygen ions so as to form a high oxygen concentration layer; implanting oxygen ions into the silicon wafer obtained by the forming of the high oxygen concentration layer so as to form an amorphous layer; and heat-treating the silicon wafer obtained by the forming of the amorphous layer so as to form a buried oxide layer, wherein in the forming of the amorphous layer, the implantation of oxygen ions is carried out after preheating the silicon wafer to a temperature lower than the heating temperature of the forming of the high oxygen concentration layer. Another embodiment of this method for manufacturing a SIMOX wafer includes: in the above forming of the high oxygen concentration layer, implanting oxygen ions while heating a silicon wafer at a temperature of 300° C.
    Type: Application
    Filed: June 20, 2006
    Publication date: January 25, 2007
    Inventors: Yoshiro Aoki, Riyuusuke Kasamatsu, Hideki Nishihata, Seiichi Nakamura
  • Publication number: 20060281233
    Abstract: This method for manufacturing a SIMOX wafer includes: heating a silicon wafer to 300° C. or more and implanting oxygen ions so as to form a high oxygen concentration layer within the silicon wafer; subjecting the silicon wafer to a cooling to less than 300° C. and an implanting of oxygen ions so as to form an amorphous layer; and subjecting the silicon wafer to a heat-treating in a mixed gas atmosphere containing oxygen so as to form a buried oxide layer. In the forming of the buried oxide layer, a starting temperature is less than 1350° C. and a maximum temperature is 1350° C. or more. This SIMOX wafer is manufactured by the above method and includes a BOX layer and a SOI layer on the BOX layer. The BOX layer has a thickness of 1300 ? or more and a breakdown voltage of 7 MV/cm or more, and the surface of the SOI layer and the interface between the SOI layer and the BOX layer have a roughness over a 10-?m square area of 4 ? rms or less.
    Type: Application
    Filed: June 8, 2006
    Publication date: December 14, 2006
    Inventors: Yoshiro Aoki, Yukio Komatsu, Tetsuya Nakai, Seiichi Nakamura
  • Publication number: 20060228492
    Abstract: In the method for manufacturing a SIMOX wafer, oxygen ions are implanted into a silicon wafer, then the silicon wafer is subjected to a prescribed heat treatment so as to form a buried oxide layer in the silicon wafer. The prescribed heat treatment includes: a step of ramping up a temperature of the silicon wafer in a low oxygen partial pressure gas atmosphere having an oxygen partial pressure ratio of less than 5%; either or both of a step of oxidizing the silicon wafer in a high oxygen partial pressure gas atmosphere having an oxygen partial pressure ratio of 5% or more and a step of annealing the silicon wafer in a low oxygen partial pressure gas atmosphere having an oxygen partial pressure ratio of less than 5%; and a step of ramping down the temperature of the silicon wafer in a low oxygen partial pressure gas atmosphere having an oxygen partial pressure ratio of less than 5%.
    Type: Application
    Filed: April 7, 2005
    Publication date: October 12, 2006
    Applicant: SUMCO CORPORATION
    Inventors: Yoshiro Aoki, Mitsuru Sudo, Tetsuya Nakai
  • Publication number: 20060221251
    Abstract: A display includes an insulating substrate, a video signal line placed on a main surface of the insulating substrate and including first and second ends, pixels connected to the video signal line, a video signal line driver to which the first end is connected, an inspection signal line placed near the second end and including third and fourth ends, the third end being located at an edge of the main surface, and an analog switch connected between the second and fourth ends.
    Type: Application
    Filed: March 27, 2006
    Publication date: October 5, 2006
    Inventors: Kazuyoshi Omata, Makoto Shibusawa, Yoshiro Aoki, Hiroshi Nakayama
  • Publication number: 20060221028
    Abstract: Each pixel includes a drive control element which includes a control terminal, a first terminal connected to a first power supply terminal, and a second terminal outputting a current having a magnitude corresponding to a voltage between the control terminal and the first terminal, a display element which includes a pixel electrode, a counter electrode connected to a second power supply terminal, and an active layer interposed between the pixel electrode and the counter electrode, a switch connected between the second terminal and the pixel electrode, a first capacitor connected between the control terminal and a constant-potential terminal, a second capacitor, a switch connected in series with the second capacitor between the control terminal and a video signal line, a switch connected between the second terminal and an electrode of the second capacitor, and a switch connected between the second terminal and another electrode of the second capacitor.
    Type: Application
    Filed: March 23, 2006
    Publication date: October 5, 2006
    Inventor: Yoshiro Aoki
  • Publication number: 20060221011
    Abstract: A display executes a first reset operation during a blanking period, and second and third reset operations and a write operation during each selection period. The first reset operation includes connecting a current source to a precharge circuit and writing a first reset signal into the precharge circuit. The second reset operation includes connecting the current source to a drive circuit of a pixel and writing a second reset signal into the drive circuit to set a potential of a video signal line at a first potential. The third reset operation includes disconnecting the video signal line from the current source and making the precharge circuit output a reset current to the video signal line for a given length of time to shift the potential of the video signal line from the first potential to a second potential.
    Type: Application
    Filed: March 23, 2006
    Publication date: October 5, 2006
    Inventor: Yoshiro Aoki
  • Publication number: 20060220577
    Abstract: A display sequentially executes first and second operations during a write period. The first operation includes making a first constant-current flow through a video signal line while connecting a first terminal of a drive control element to a power supply terminal connecting a second terminal and control terminal of the drive control element to the video signal line. The second operation includes making a second constant-current flow through the video signal line in a flow direction of the first constant-current while breaking a connection between the first terminal and the power supply terminal and/or a connection between the second terminal and the control terminal and connecting the control terminal to the video signal line. The display causes a difference between grayscale levels by changing a time period during which the second constant-current flows through the video signal line.
    Type: Application
    Filed: March 23, 2006
    Publication date: October 5, 2006
    Inventor: Yoshiro Aoki
  • Publication number: 20060202919
    Abstract: A display includes pixels arrange in a matrix. Each pixel includes a display element, a first drive current control circuit which is supplied with a first video signal and outputs a first drive current to the display element at magnitude corresponding to magnitude of the first video signal, and a second drive current control circuit which is supplied with a second video signal and outputs a second drive current to the display element at magnitude corresponding to magnitude of the second video signal. The display can set a ratio T1/T2 larger than 1, wherein T1 represents a time period over which the first drive current control circuit can output the first drive current to the display element, and T2 represents a time period over which the second drive current control circuit can output the second drive current to the display element.
    Type: Application
    Filed: January 30, 2006
    Publication date: September 14, 2006
    Inventors: Yoshiro Aoki, Hirondo Nakatogawa
  • Publication number: 20060066536
    Abstract: An active matrix display device comprises a plurality of pixels which are arranged in the form of a matrix on a substrate and each of which includes a display element and a pixel circuit which supplies the display element with a drive current, video signal lines arranged along the pixels, and a video signal driver which, after the supply of base currents to the video signal lines, supplies the pixels with gradation currents through the video signal lines. The pixel circuit includes a pixel switch which controls whether or not to select the pixel, stores the difference current between the gradation and base currents when the pixel is selected and outputs the stored difference current to the display element as the drive current when the pixel is nonselected.
    Type: Application
    Filed: November 10, 2005
    Publication date: March 30, 2006
    Inventors: Masuyuki Ota, Yoshiro Aoki