Abstract: Buffer circuits and analogue switches are disposed closer to a display region than video busses. A timing signal generator circuit provides the buffer circuits with a timing signal. The analogue switches supply video signals from the video busses to signal lines in the display region in response to the timing signal. Parasitic capacitance coupled to the video busses is reduced so that bandwidth characteristics of the busses can be improved and a good display can be also obtained.

Abstract: A flat-panel display device includes a display panel plate, a plurality of display pixels arrayed in a matrix on the display panel plate, a plurality of signal lines formed on the display panel plate along columns of the display pixels, a scanning line driving circuit formed on the display panel plate, for sequentially and periodically selecting rows of the display pixels to connect the display pixels of a selected row to the signal lines, and a signal line driver circuit formed on the display panel plate for driving the display pixels of a selected row via the signal lines.

Abstract: A timing signal generating circuit has a plurality of timing signal generating units disposed in series, each including three or more pieces of timing signal generating elements connected in parallel, and a connecting unit disposed in between the plurality of timing signal generating units. The connecting unit includes an arithmetic circuit which outputs relatively majority signal among outputs of the timing signal generating elements.In this circuit, if some of the timing signal generating elements output defective signals, normal signal is picked-up and output through majority operation of the arithmetic circuit without repairing.

Abstract: A first common line for supplying a positive phase picture signal and a second common line for supplying a negative phase picture signal are disclosed. A plurality of first switch devices are connected to the first common line. A plurality of second switch devices are connected to the second common line. Each of the first switch devices and each of the second switch devices are paired and connected to one signal line. A first operational amplifier is disclosed between each of the first switch devices and the signal line. The first operational amplifier operates in common with the first switch device group. A second operational amplifier is disclosed between each of the second switch devices and the signal line. The second operational amplifier operates in common with the second switch device group. A common control signal is input from a timing control circuit to the pair of each of the first switch devices and each of the second switch devices.

Abstract: An array substrate of an LCD device includes a glass substrate, an n.times.m number of pixel electrodes arrayed in a matrix form on the glass substrate, an n-number of scanning lines formed along rows of the pixel electrodes on the glass substrate, an m-number of signal lines formed along columns of the pixel electrodes on the glass substrate, switching elements formed on the glass substrate and located adjacent to intersections of the scanning lines and signal lines, each switching element supplying a video signal from the signal line to the pixel electrode in response to a scanning signal supplied from the scanning line, and a test supporting circuit for sensing potentials of the scanning lines.

Abstract: A liquid crystal display device of low power consumption is disclosed, which is suitable for use with a portable data processing apparatus, in particular.