Patents by Inventor Yoshiro Aoki
Yoshiro Aoki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7956335Abstract: A wafer holding assembly is provided that is capable of preventing the temperature difference generated between a wafer and a holding pin through beam irradiation. In one embodiment, the wafer holding assembly has a plurality of holding pins for holding a wafer in the ion implanting apparatus, the holding pin comprises a head contacting with an end face of the wafer to control motion of the wafer and a flange projecting from the head to place the wafer, and the head is provided with a canopy portion extending in a direction different from a side placing the wafer.Type: GrantFiled: July 10, 2009Date of Patent: June 7, 2011Assignee: Sumco CorporationInventor: Yoshiro Aoki
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Patent number: 7884000Abstract: A method for manufacturing SIMOX wafer, wherein roughness (Rms) of an SOI layer and roughness (Rms) of an interface between the SOI layer and a BOX layer can be reduced. The method includes forming a first ion-implanted layer containing highly concentrated oxygen within a wafer; forming a second ion-implanted amorphous layer; and a high temperature heat treatment, transforming the first and second ion-implanted layers into a BOX layer by holding the wafer at a temperature between 1300° C. or more and a temperature less than a silicon melting point in an atmosphere containing oxygen, wherein when a first dose amount in forming the first ion-implanted layer is set to 2×1017 to 3×1017 atoms/cm2, the first implantation energy set to 165 to 240 keV and a second dose amount in forming the second ion-implanted layer is set to 1x1014 to 1x1016 atoms/cm2.Type: GrantFiled: April 3, 2007Date of Patent: February 8, 2011Assignee: Sumco CorporationInventors: Yoshiro Aoki, Riyuusuke Kasamatsu, Yukio Komatsu
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Patent number: 7807545Abstract: A SIMOX wafer having a BOX layer with a thin film thickness is obtained without a reduction in productivity or deterioration in quality. In a method for manufacturing a SIMOX wafer comprising: a step of forming a first ion-implanted layer in a silicon wafer; a step of forming a second ion-implanted layer that is in an amorphous state; and a high-temperature heat treatment step of maintaining the wafer in an oxygen contained atmosphere at a temperature that is not lower than 1300° C. but less than a silicon melting point for 6 to 36 hours to change the first and the second ion-implanted layers into a BOX layer, a gas containing chlorine that is not less than 0.1 volume % but less than 1.0 volume % is mixed into an atmosphere during temperature elevation in the high-temperature heat treatment.Type: GrantFiled: February 2, 2007Date of Patent: October 5, 2010Assignee: Sumco CorporationInventors: Yoshiro Aoki, Yukio Komatsu, Tetsuya Nakai, Seiichi Nakamura
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Patent number: 7746299Abstract: A display includes pixels arrange in a matrix. Each pixel includes a display element, a first drive current control circuit which is supplied with a first video signal and outputs a first drive current to the display element at magnitude corresponding to magnitude of the first video signal, and a second drive current control circuit which is supplied with a second video signal and outputs a second drive current to the display element at magnitude corresponding to magnitude of the second video signal. The display can set a ratio T1/T2 larger than 1, wherein T1 represents a time period over which the first drive current control circuit can output the first drive current to the display element, and T2 represents a time period over which the second drive current control circuit can output the second drive current to the display element.Type: GrantFiled: January 30, 2006Date of Patent: June 29, 2010Assignee: Toshiba Matsushita Display Technology Co., Ltd.Inventors: Yoshiro Aoki, Hirondo Nakatogawa
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Patent number: 7727867Abstract: A MLD-SIMOX wafer is obtained by forming a first ion-implanted layer in a silicon wafer; forming a second ion-implanted layer that is in an amorphous state; and subjecting the wafer to a high-temperature heat treatment to maintain the wafer in an atmosphere containing oxygen at a temperature that is not lower than 1300° C. but lower than a silicon melting point to change the first and the second ion-implanted layers into a BOX layer, wherein the dose amount for the first ion-implanted layer is 1.25 to 1.5×1017 atoms/cm2, the dose amount for the second ion-implanted layer is 1.0×1014 to 1×1016 atoms/cm2, the wafer is preheated to a temperature of 50° C. to 200° C. before forming the second ion-implanted layer, and the second ion-implanted layer is formed in a state where it is continuously heated to a preheating temperature.Type: GrantFiled: February 21, 2007Date of Patent: June 1, 2010Assignee: Sumco CorporationInventors: Yoshiro Aoki, Bong-Gyun Ko
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Publication number: 20100022066Abstract: A method for producing a high-resistance SIMOX wafer wherein oxygen diffused inside of a wafer by the heat treatment at a high temperature in an oxidizing atmosphere can be reduced to suppress the occurrence of thermal donor. In one embodiment, a heating-rapid cooling treatment is conducted after the heat treatment at a high temperature in an oxidizing atmosphere to implant vacancies from a surface of a wafer into an interior thereof to thereby easily precipitate oxygen diffused inside the wafer during the heat treatment.Type: ApplicationFiled: July 16, 2009Publication date: January 28, 2010Applicant: SUMCO CORPORATIONInventors: Yoshiro Aoki, Naoshi Adachi
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Publication number: 20100012856Abstract: A wafer holding assembly is provided that is capable of preventing the temperature difference generated between a wafer and a holding pin through beam irradiation. In one embodiment, the wafer holding assembly has a plurality of holding pins for holding a wafer in the ion implanting apparatus, the holding pin comprises a head contacting with an end face of the wafer to control motion of the wafer and a flange projecting from the head to place the wafer, and the head is provided with a canopy portion extending in a direction different from a side placing the wafer.Type: ApplicationFiled: July 10, 2009Publication date: January 21, 2010Applicant: SUMCO CORPORATIONInventor: Yoshiro Aoki
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Publication number: 20100006779Abstract: This ion implantation apparatus is provided with a holding devise which holds the wafer, and which turns it along its circumference. In addition to holding the wafer at a prescribed position, the ion implantation apparatus subjects the wafer to ion implantation in regions where there is partial overlap of its circumference. The holding devise turns and inclines the wafer, and also holds the wafer by three or more holding pins. The side face of the holding pin has an inversely tapered shape, and the multiple holding pins include a first holding pin whose protrusion amount is relatively small, and a second holding pin whose protrusion amount is relatively large.Type: ApplicationFiled: July 2, 2009Publication date: January 14, 2010Applicant: SUMCO CORPORATIONInventor: Yoshiro AOKI
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Publication number: 20090321874Abstract: A small amount of oxygen is ion-implanted in a wafer surface layer, and then heat treatment is performed so as to form an incomplete implanted oxide film in the surface layer. Thereby, wafer cost is reduced; a pit is prevented from forming in a surface of an epitaxial film; and a slip is prevented from forming in an external peripheral portion of a wafer.Type: ApplicationFiled: June 12, 2009Publication date: December 31, 2009Applicant: SUMCO CORPORATIONInventors: Yoshiro AOKI, Naoshi ADACHI, Akihiko ENDO, Yoshihisa NONOGAKI
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Patent number: 7639215Abstract: A display executes a first reset operation during a blanking period, and second and third reset operations and a write operation during each selection period. The first reset operation includes connecting a current source to a precharge circuit and writing a first reset signal into the precharge circuit. The second reset operation includes connecting the current source to a drive circuit of a pixel and writing a second reset signal into the drive circuit to set a potential of a video signal line at a first potential. The third reset operation includes disconnecting the video signal line from the current source and making the precharge circuit output a reset current to the video signal line for a given length of time to shift the potential of the video signal line from the first potential to a second potential.Type: GrantFiled: March 23, 2006Date of Patent: December 29, 2009Assignee: Toshiba Matsushita Display Technology Co., Ltd.Inventor: Yoshiro Aoki
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Publication number: 20090314964Abstract: An ion-implanting apparatus comprising a holding unit that holds at least a semiconductor wafer and swings the wafer along a circular orbit, wherein an ion-beam is irradiated to a region that overlaps a part of the circular orbit; the holding unit comprises three or more holding pins that hold the wafer; the holding pins include a first type holding pin at least a portion of which being in contact with an edge of the wafer is made of a material selected from a thermo-setting resin and a photo-setting resin, and a second type holding pin at least a portion of which being in contact with the wafer is made of a material that contains graphite; and the first type holding pin of the plurality of holding pins is placed at a tail end position with respect to a direction of swinging the wafer.Type: ApplicationFiled: June 19, 2009Publication date: December 24, 2009Applicant: SUMCO CORPORATIONInventor: Yoshiro AOKI
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Publication number: 20090289888Abstract: Provided is a waveform processing circuit including: an amplitude expansion circuit configured to expand amplitude of an analog video signal; a voltage shifting circuit configured to shift a voltage of the analog video signal; and an impedance conversion circuit having an output impedance lower than that of the voltage shifting circuit.Type: ApplicationFiled: May 19, 2009Publication date: November 26, 2009Inventors: Yoshiro AOKI, Takanori TSUNASHIMA
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Publication number: 20090260570Abstract: In oxygen ion implantation equipment, a chamber has a bottom wall on one end face thereof and is open in the other end face thereof. A wafer holder rotatably holding a plurality of wafers on the same circumference of a circle is housed in the chamber. Inside a cap closing an opening of the chamber while making the chamber airtight with a sealing member, a coolant passage is formed near the sealing member. A plurality of lamp heaters are disposed so as to extend in the direction of the tangent to the circumference of the cap and align parallel to the direction of the radius of the cap, in such a way as to face one wafer held by the wafer holder.Type: ApplicationFiled: March 12, 2009Publication date: October 22, 2009Applicant: SUMCO CORPORATIONInventor: Yoshiro AOKI
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Patent number: 7573442Abstract: There is provided a display including pixels arranged in a matrix, each pixel including a voltage signal input terminal to which a voltage signal is supplied, a drive control element including a first terminal connected to a first power supply terminal, a control terminal, and a second terminal that outputs a current corresponding to a voltage between the first and second terminals, a capacitor connected between the voltage signal input terminal and the control terminal, a current signal input terminal to which a current signal is supplied, a first switch connected between the current signal input terminal and the control terminal, a second switch connected between the current signal input terminal and the second terminal, an output control switch whose input terminal is connected to the second terminal, and a display element connected between a second power supply terminal and an output terminal of the output control switch.Type: GrantFiled: June 6, 2005Date of Patent: August 11, 2009Assignee: Toshiba Matsushita Display Technology Co., Ltd.Inventor: Yoshiro Aoki
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Patent number: 7550371Abstract: A SIMOX wafer is produced by implanting an oxygen ions into a surface of a Si substrate and then conducting a high-temperature annealing, in which an atmosphere in at least an end stage of the high-temperature annealing treatment is an Ar or N2 atmosphere containing an oxygen of more than 3 volume % but not more than 10 volume %.Type: GrantFiled: March 27, 2007Date of Patent: June 23, 2009Assignee: SUMCO CorporationInventors: Yoshio Murakami, Riyuusuke Kasamatsu, Yoshiro Aoki
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Publication number: 20090152671Abstract: This method for manufacturing a SIMOX wafer includes: heating a silicon wafer to 300° C. or more and implanting oxygen ions so as to form a high oxygen concentration layer within the silicon wafer; subjecting the silicon wafer to a cooling to less than 300° C. and an implanting of oxygen ions so as to form an amorphous layer; and subjecting the silicon wafer to a heat-treating in a mixed gas atmosphere containing oxygen so as to form a buried oxide layer. In the forming of the buried oxide layer, a starting temperature is less than 1350° C. and a maximum temperature is 1350° C. or more. This SIMOX wafer is manufactured by the above method and includes a BOX layer and a SOI layer on the BOX layer. The BOX layer has a thickness of 1300 ? or more and a breakdown voltage of 7 MV/cm or more, and the surface of the SOI layer and the interface between the SOI layer and the BOX layer have a roughness over a 10-?m square area of 4 ? rms or less.Type: ApplicationFiled: February 19, 2009Publication date: June 18, 2009Applicant: Sumco CorporationInventors: Yoshiro Aoki, Yukio Komatsu, Tetsuya Nakai, Seiichi Nakamura
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Patent number: 7514343Abstract: This method for manufacturing a SIMOX wafer includes: heating a silicon wafer to 300° C. or more and implanting oxygen ions so as to form a high oxygen concentration layer within the silicon wafer; subjecting the silicon wafer to a cooling to less than 300° C. and an implanting of oxygen ions so as to form an amorphous layer; and subjecting the silicon wafer to a heat-treating in a mixed gas atmosphere containing oxygen so as to form a buried oxide layer. In the forming of the buried oxide layer, a starting temperature is less than 1350° C. and a maximum temperature is 1350° C. or more. This SIMOX wafer is manufactured by the above method and includes a BOX layer and a SOI layer on the BOX layer. The BOX layer has a thickness of 1300 ? or more and a breakdown voltage of 7 MV/cm or more, and the surface of the SOI layer and the interface between the SOI layer and the BOX layer have a roughness over a 10-?m square area of 4 ? rms or less.Type: GrantFiled: June 8, 2006Date of Patent: April 7, 2009Assignee: Sumco CorporationInventors: Yoshiro Aoki, Yukio Komatsu, Tetsuya Nakai, Seiichi Nakamura
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Patent number: 7410877Abstract: A method for manufacturing a SIMOX wafer includes: heating a silicon wafer, implanting oxygen ions so as to form a high oxygen concentration layer; implanting oxygen ions into the silicon wafer obtained by the forming of the high oxygen concentration layer to form an amorphous layer; and heat-treating the silicon wafer to form a buried oxide layer, wherein in the forming of the amorphous layer, the implantation of oxygen ions is carried out after preheating the silicon wafer to a temperature lower than the heating temperature of the forming of the high oxygen concentration layer. Alternatively, the method for manufacturing a SIMOX wafer includes: in the formation of the high oxygen concentration layer, implanting oxygen ions while heating a silicon wafer at a temperature of 300° C. or more; and in the formation of the amorphous layer, implanting oxygen ions after preheating the silicon wafer to a temperature of less than 300° C.Type: GrantFiled: June 20, 2006Date of Patent: August 12, 2008Assignee: Sumco CorporationInventors: Yoshiro Aoki, Riyuusuke Kasamatsu, Hideki Nishihata, Seiichi Nakamura
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Publication number: 20080122757Abstract: A plurality of pixel units are arranged in a matrix, each pixel unit including a display element and a pixel circuit which supplies a driving current to the display element. Each pixel circuit includes a first memory section which stores, in a write period of the pixel unit, a first driving current corresponding to a first signal current and then outputs the stored first driving current, and further stores a second driving current corresponding to a second signal current, and a second memory section which stores the first driving current output from the first memory section in the write period of the pixel unit. The pixel circuit outputs, in a light emission period of the pixel unit, a difference current between the second driving current stored in the first memory section and the first driving current stored in the second memory section to the display element as the driving current.Type: ApplicationFiled: November 26, 2007Publication date: May 29, 2008Inventors: Kazuyoshi Omata, Masuyuki Oota, Yoshiro Aoki
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Patent number: 7372440Abstract: An active matrix display device comprises a plurality of pixels which are arranged in the form of a matrix on a substrate and each of which includes a display element and a pixel circuit which supplies the display element with a drive current, video signal lines arranged along the pixels, and a video signal driver which, after the supply of base currents to the video signal lines, supplies the pixels with gradation currents through the video signal lines. The pixel circuit includes a pixel switch which controls whether or not to select the pixel, stores the difference current between the gradation and base currents when the pixel is selected and outputs the stored difference current to the display element as the drive current when the pixel is nonselected.Type: GrantFiled: November 10, 2005Date of Patent: May 13, 2008Assignee: Toshiba Matsushita Display Technology Co., Ltd.Inventors: Masuyuki Ota, Yoshiro Aoki