Patents by Inventor Yoshiro Aoki
Yoshiro Aoki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20050269961Abstract: In an active matrix organic EL display including a drive control element which has a first terminal connected to a first power supply terminal, a control terminal, and a second terminal which outputs a driving current having a magnitude corresponding to the voltage between the first terminal and the control terminal, a capacitor which has one electrode connected to the control terminal and can maintain the voltage between the first terminal and the control terminal constant, and an organic EL element connected between the second terminal and a second power supply terminal, a plurality of switches connected in series are used as switches between the second terminal and the control terminal to obtain a perfect nonconductive state, and the switch on the control terminal side is set in the nonconductive state earlier than the remaining switch, thereby decreasing the potential shift amount generated by the capacitance of the switches themselves.Type: ApplicationFiled: July 22, 2005Publication date: December 8, 2005Inventors: Makoto Shibusawa, Yoshiro Aoki, Hirondo Nakatogawa
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Patent number: 6972779Abstract: A liquid crystal display device comprises a plurality of display pixels PX each including sub-pixels weighted in a preset area ratio and a driving circuit which drives the display pixels. Particularly, the driving circuit is configured to determine the gradation of each display pixel PX by selectively combining the sub-pixels with driving periods weighted in a preset time ratio.Type: GrantFiled: September 30, 2002Date of Patent: December 6, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Tomonobu Motai, Yoshiro Aoki, Kazuo Nakamura
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Publication number: 20050241853Abstract: Provided is a wiring board including an insulating substrate with a first region and a second region adjacent to each other on a major surface, signal line groups arrayed on the first region, and connection portions arranged on the second region in correspondence with the signal line groups, wherein each connection portion includes first to third terminal groups, a first wiring line group connecting the first terminal group to the corresponding signal line group, a second wiring line group connected to the second terminal group, and a third wiring group connected to the third terminal group, wherein the second and third wiring line groups are connected to each other between each adjacent connection portions, and all of the connection portions are the same in shapes of the first to third terminal groups and the first to third wiring line groups.Type: ApplicationFiled: July 6, 2005Publication date: November 3, 2005Inventor: Yoshiro Aoki
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Publication number: 20050227462Abstract: A method for manufacturing a SOI wafer includes a step of heat-treating a wafer in a furnace to form an SOI wafer including a silicon support, an insulating layer containing oxide, and a superficial silicon layer arranged in that order and a step of unloading the SOI wafer from the furnace maintained at a temperature of 250° C. to 800° C. to transfer the SOI wafer to an atmosphere containing hydrogen or water. The steps are performed in that order.Type: ApplicationFiled: April 8, 2005Publication date: October 13, 2005Applicant: Sumitomo Mitsubishi Silicon CorporationInventors: Yoshio Murakami, Toru Yamazaki, Yoshiro Aoki, Akihiko Endo
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Publication number: 20050212732Abstract: There is provided a display including pixels arranged in a matrix, each pixel including a voltage signal input terminal to which a voltage signal is supplied, a drive control element including a first terminal connected to a first power supply terminal, a control terminal, and a second terminal that outputs a current corresponding to a voltage between the first and second terminals, a capacitor connected between the voltage signal input terminal and the control terminal, a current signal input terminal to which a current signal is supplied, a first switch connected between the current signal input terminal and the control terminal, a second switch connected between the current signal input terminal and the second terminal, an output control switch whose input terminal is connected to the second terminal, and a display element connected between a second power supply terminal and an output terminal of the output control switch.Type: ApplicationFiled: June 6, 2005Publication date: September 29, 2005Inventor: Yoshiro Aoki
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Publication number: 20050098877Abstract: When a two-division structure heat treatment jig for semiconductor substrate that includes a silicon first jig that comes into direct contact with a semiconductor substrate that is heat treated and supports the semiconductor substrate, and a second jig (holder) that holds the first jig and is mounted on a heat treatment boat is adopted as a heat treatment boat of a vertical heat treatment furnace, the stress concentrated during the heat treatment on a particular portion of the semiconductor substrate can be reduced; in the case of a semiconductor substrate large in the tare stress and having an outer shape of 300 mm being heat treated, or even in the case of the heat treatment being carried out under very high temperature conditions, the slips can be suppressed from occurring. The present invention can be widely applied as a stable heat treatment method of semiconductor substrates.Type: ApplicationFiled: January 5, 2004Publication date: May 12, 2005Inventors: Naoshi Adachi, Kazushi Yoshida, Yoshiro Aoki
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Publication number: 20050007307Abstract: Buffer circuits are provided between outputs of a scanning line driver circuit and scanning lines. The buffer circuits each are configured to make rise or fall time of scanning signals at output sides of the buffer circuits substantially the same as or longer than those of the scanning signals at end terminals of the scanning lines when the scanning signals supplied to the scanning lines are rectangular in waveform.Type: ApplicationFiled: May 17, 2004Publication date: January 13, 2005Applicant: Toshiba Matsushita Display Technology Co., Ltd.Inventor: Yoshiro Aoki
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Patent number: 6828726Abstract: An organic EL display device comprises an organic EL element PX in which a self light-emitting layer is held between an anode and a cathode, and a pixel switch SW′ for pixels formed of the organic EL element PX. Particularly, the pixel switch SW′ includes a source electrode and a drain electrode which is formed together with the anode on an interlayer insulating film so as to reflect the light laterally emitted from the self light-emitting layer.Type: GrantFiled: October 19, 2001Date of Patent: December 7, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Hiroyuki Sakurai, Michiya Kobayashi, Norihiko Kamiura, Yoshiro Aoki
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Patent number: 6788281Abstract: A circuit panel includes an array substrate in which a scanning line is formed as a capacitive load and first and second scanning line drivers connected to the scanning line in order to commonly drive the scanning line. Each of the first and second scanning line drivers includes first and second switching circuits connected in series between first and second power terminals to selectively output one of the potentials of the first and second power source terminals as a control signal, and an output buffer for setting the potential of the scanning line in accordance with the control signal. The driving abilities of the first and second switching circuits are uneven.Type: GrantFiled: May 30, 2001Date of Patent: September 7, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Kotaro Ando, Yoshiro Aoki
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Patent number: 6639575Abstract: There is provided a driving circuit including active matrix type liquid crystal display capable of decreasing the electric power consumption of CMOS buffers contained in a scanning line driving circuit and picture signal line driving circuit. The liquid crystal display has an active matrix type liquid crystal display elements comprising switching elements connected to a plurality of scanning lines and a plurality of picture signal lines perpendicular to the scanning lines. The liquid crystal display includes a digital circuit wherein at least one of a scanning line driving circuit for applying a scanning pulse to the switching elements via the scanning lines and a picture signal line driving circuit for applying a picture signal to the picture signal lines comprises one stage of CMOS buffer or a plurality of CMOS buffers connected in multi stages, the CMOS transistor or each of the CMOS transistors including an N-type thin-film transistor and P-type thin-film transistor which are formed on the same substrate.Type: GrantFiled: March 17, 2000Date of Patent: October 28, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Takanori Tsunashima, Yoshiro Aoki, Kazuo Nakamura, Hajime Sato
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Patent number: 6603456Abstract: A differential voltage between the threshold voltage of an amplitude amplifying logic circuit 20 and a reference voltage V1 is stored in a capacitor C1. When an input signal IS is input to the amplitude amplifying logic circuit 20, it is input after adding to the voltage of the input signal IS the voltage stored in the capacitor C1. In this manner, any difference between the threshold voltage V1 of the amplitude amplifying logic circuit 20 and the reference voltage can be absorbed. Therefore, a signal amplifier circuit can operate normally even when the threshold voltage of the amplitude amplifying logic circuit 20 in the signal amplifier circuit varies.Type: GrantFiled: November 4, 1999Date of Patent: August 5, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Yoshiro Aoki, Masao Karue
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Publication number: 20030063109Abstract: A liquid crystal display device comprises a plurality of display pixels PX each including sub-pixels weighted in a preset area ratio and a driving circuit which drives the display pixels. Particularly, the driving circuit is configured to determine the gradation of each display pixel PX by selectively combining the sub-pixels with driving periods weighted in a preset time ratio.Type: ApplicationFiled: September 30, 2002Publication date: April 3, 2003Inventors: Tomonobu Motai, Yoshiro Aoki, Kazuo Nakamura
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Publication number: 20020089471Abstract: With regard to a display device having an SRAM incorporated in a pixel, a technology is disclosed, which is capable of reducing manufacturing costs by simplifying a constitution of a driver. A write voltage equivalent to white or black represented by a tone level of a normal display area is converted into a write voltage corresponding to a brightest white display or a darkest black display in the pixel, and is held in the SRAM of each pixel. In the case of normal display, display is carried out with the write voltage represented by the tone level of the normal display area. In the case of static image display, display is carried out with the write voltage corresponding to the brightest white display or the darkest black display in the pixel, the write voltage being held in the SRAM. Since the normal display and the static image display can be carried out with a write voltage supplied from one driver, the constitution of the driver can be simplified.Type: ApplicationFiled: January 3, 2002Publication date: July 11, 2002Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroyoshi Murata, Nobuo Yamasaki, Masakatsu Kitani, Yoshiro Aoki
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Patent number: 6414668Abstract: Arrangement of connection points of sampling switches to video bus lines within a signal line drive circuit 200 is improved such that connection points of video buses (SVn1 to SVn6) supplied with positive-polarity video signals relative to a predetermined reference potential and video buses (SVp1 to SVp6) supplied with negative-polarity video signals to analog switches (SWn11 to SWn22 and SWp11 to SWp22) make substantially symmetric patterns in the extending direction of the video buses. Since the sum of lengths of connection wirings belonging to a switch pair and their total resistance value becomes substantially equal in all switch pairs, the effective vales of shift amounts in signal line potentials are substantially flattened. Therefore, here is provided a drive circuit built-in liquid crystal display device realizing a good imaging quality removing noise such as stripe-shaped imaging defects which may occur when video signals are supplied to analog switches through a plurality of video buses.Type: GrantFiled: January 21, 1999Date of Patent: July 2, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Masao Karube, Kazuo Nakamura, Masaki Miyatake, Hoko Hirai, Akihiko Saitoh, Yoshiro Aoki
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Publication number: 20020050964Abstract: Arrangement of connection points of sampling switches to video bus lines within a signal line drive circuit 200 is improved such that connection points of video buses (SVn1 to SVn6) supplied with positive-polarity video signals relative to a predetermined reference potential and video buses (SVp1 to SVp6) supplied with negative-polarity video signals to analog switches (SWn11 to SWn22 and SWp11 to SWp22) make substantially symmetric patterns in the extending direction of the video buses. Since the sum of lengths of connection wirings belonging to a switch pair and their total resistance value becomes substantially equal in all switch pairs, the effective vales of shift amounts in signal line potentials are substantially flattened. Therefore, here is provided a drive circuit built-in liquid crystal display device realizing a good imaging quality removing noise such as stripe-shaped imaging defects which may occur when video signals are supplied to analog switches through a plurality of video buses.Type: ApplicationFiled: January 21, 1999Publication date: May 2, 2002Inventors: MASAO KARUBE, KAZUO NAKAMURA, MASAKI MIYATAKE, HOKO HIRAI, AKIHIKO SAITOH, YOSHIRO AOKI
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Publication number: 20020047838Abstract: An array substrate of an LCD device includes a glass substrate, an n×m number of pixel electrodes arrayed in a matrix form on the glass substrate, an n-number of scanning lines formed along rows of the pixel electrodes on the glass substrate, an m-number of signal lines formed along columns of the pixel electrodes on the glass substrate, switching elements formed on the glass substrate and located adjacent to intersections of the scanning lines and signal lines, each switching element supplying a video signal from the signal line to the pixel electrode in response to a scanning signal supplied from the scanning line, and a test supporting circuit for sensing potentials of the scanning lines.Type: ApplicationFiled: January 26, 1998Publication date: April 25, 2002Inventors: YOSHIRO AOKI, YOUICHI MASUDA
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Publication number: 20020047514Abstract: An organic EL display device comprises an organic EL element PX in which a self light-emitting layer is held between an anode and a cathode, and a pixel switch SW′ for pixels formed of the organic EL element PX. Particularly, the pixel switch SW′ includes a source electrode and a drain electrode which is formed together with the anode on an interlayer insulating film so as to reflect the light laterally emitted from the self light-emitting layer.Type: ApplicationFiled: October 19, 2001Publication date: April 25, 2002Inventors: Hiroyuki Sakurai, Michiya Kobayashi, Norihiko Kamiura, Yoshiro Aoki
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Publication number: 20020000965Abstract: A circuit panel includes an array substrate in which a scanning line is formed as a capacitive load and first and second scanning line drivers connected to the scanning line in order to commonly drive the scanning line. Each of the first and second scanning line drivers includes first and second switching circuits connected in series between first and second power terminals to selectively output one of the potentials of the first and second power source terminals as a control signal, and an output buffer for setting the potential of the scanning line in accordance with the control signal. The driving abilities of the first and second switching circuits are uneven.Type: ApplicationFiled: May 30, 2001Publication date: January 3, 2002Inventors: Kotaro Ando, Yoshiro Aoki
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Patent number: 6333661Abstract: An insulated-gate transistor signal input device includes an insulating substrate, a first clock line formed on the insulating substrate to receive a clock signal externally supplied, a clock buffer formed on the insulating substrate to process the clock signal supplied from the first clock line, a second clock line formed on the insulating substrate to input a signal obtained from the clock buffer to a shift register serving as a load circuit formed on the insulating substrate. The insulated-gate transistor signal input device further includes a first protection diode circuit connected to the first clock line to remove electrostatic charge from the first clock line, and a second protection diode circuit connected to the second clock line to remove electrostatic charge from the second clock line.Type: GrantFiled: September 24, 1999Date of Patent: December 25, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Kotaro Ando, Yoshiro Aoki, Masaki Miyatake
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Patent number: 6268894Abstract: A liquid crystal display apparatus having a plurality of pixel cells is disclosed, each of which comprising a scanning line and a signal line disposed on an insulation substrate in such a manner that the scanning line intersects with the signal line, a switching device disposed at the intersection of the scanning line and the signal line, a display pixel electrode electrically connected to the switching device, an opposite electrode disposed opposite to the display pixel electrode through a liquid crystal layer, and an auxiliary capacitor line disposed in a space between two adjacent display pixel electrodes in parallel with the scanning line and capacitively coupled with the display pixel electrode so as to form an auxiliary capacitor, wherein the scanning line overlaps with the display pixel electrode.Type: GrantFiled: May 31, 1996Date of Patent: July 31, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Yoshiro Aoki, Hajime Sato