Patents by Inventor Yoshiro Hirose

Yoshiro Hirose has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10755921
    Abstract: A method of manufacturing a semiconductor device, includes forming a film on a substrate by performing a cycle a predetermined number of times. The cycle includes non-simultaneously performing (a) supplying a precursor containing a first element to the substrate, (b) supplying a plasma-excited nitrogen gas to the substrate after the act (a), (c) supplying a reactant containing a second element to the substrate after the act (b), and (d) supplying a plasma-excited nitrogen gas to the substrate after the act (c). A gas purge of a space where the substrate is located and vacuumization of the space without gas supply are not performed between the act (a) and the act (b) and between the act (c) and the act (d).
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: August 25, 2020
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Yoshitomo Hashimoto, Yoshiro Hirose, Tatsuru Matsuoka
  • Patent number: 10734786
    Abstract: The present embodiment relates to a semiconductor light emitting element having a structure that enables removal of zero-order light from output light of an S-iPM laser. The semiconductor light emitting element includes an active layer, a pair of cladding layers, and a phase modulation layer. The phase modulation layer has a base layer and a plurality of modified refractive index regions each of which is individually arranged at a specific position. One of the pair of cladding layers includes a distributed Bragg reflector layer which has a transmission characteristic with respect to a specific optical image outputted along an inclined direction with respect to a light emission surface and has a reflection characteristic with respect to the zero-order light outputted along a normal direction of the light emission surface.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: August 4, 2020
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Kazuyoshi Hirose, Yoshitaka Kurosaka, Takahiro Sugiyama, Yuu Takiguchi, Yoshiro Nomoto
  • Publication number: 20200243325
    Abstract: A film where a first layer and a second layer are laminated is formed on a substrate by performing: forming the first layer by performing a first cycle a predetermined number of times, the first cycle including non-simultaneously performing: supplying a source to the substrate, and supplying a reactant to the substrate, under a first temperature at which neither the source nor the reactant is thermally decomposed when the source and the reactant are present alone, respectively; and forming the second layer by performing a second cycle a predetermined number of times, the second cycle including non-simultaneously performing: supplying the source to the substrate, and supplying the reactant to the substrate, under a second temperature at which neither the source nor the reactant is thermally decomposed when the source and the reactant are present alone, respectively, the second temperature being different from the first temperature.
    Type: Application
    Filed: April 10, 2020
    Publication date: July 30, 2020
    Applicant: KOKUSAI ELECTRIC CORPORATION
    Inventors: Tsukasa KAMAKURA, Takaaki NODA, Yoshiro HIROSE
  • Publication number: 20200243324
    Abstract: A film where a first layer and a second layer are laminated is formed on a substrate by performing: forming the first layer by performing a first cycle a predetermined number of times, the first cycle including non-simultaneously performing: supplying a source to the substrate, and supplying a reactant to the substrate, under a first temperature at which neither the source nor the reactant is thermally decomposed when the source and the reactant are present alone, respectively; and forming the second layer by performing a second cycle a predetermined number of times, the second cycle including non-simultaneously performing: supplying the source to the substrate, and supplying the reactant to the substrate, under a second temperature at which neither the source nor the reactant is thermally decomposed when the source and the reactant are present alone, respectively, the second temperature being different from the first temperature.
    Type: Application
    Filed: April 10, 2020
    Publication date: July 30, 2020
    Applicant: KOKUSAI ELECTRIC CORPORATION
    Inventors: Tsukasa KAMAKURA, Takaaki NODA, Yoshiro HIROSE
  • Publication number: 20200209653
    Abstract: The present embodiment relates to a light-emitting device that enables reduction in attenuation or diffraction effect caused by a semiconductor light-emitting device with respect to modulated light outputted from a spatial light modulator, and the light-emitting device includes the semiconductor light-emitting device that outputs light from a light output surface and the reflection type spatial light modulator that modulates the light. The spatial light modulator includes a light input/output surface having the area larger than the area of a light input surface of the semiconductor light-emitting device, modulates light taken through a region facing the light output surface of the semiconductor light-emitting device in the light input/output surface, and outputs the modulated light from another region of the light input/output surface to a space other than the light input surface of the semiconductor light-emitting device.
    Type: Application
    Filed: June 13, 2018
    Publication date: July 2, 2020
    Applicant: HAMAMATSU PHOTONICS K.K.
    Inventors: Yuu TAKIGUCHI, Kazuyoshi HIROSE, Yoshitaka KUROSAKA, Takahiro SUGIYAMA, Yoshiro NOMOTO, Soh UENOYAMA
  • Patent number: 10700495
    Abstract: The present embodiment relates to a semiconductor light emitting element having a structure that enables removal of zero-order light from output light of an S-iPM laser. The semiconductor light emitting element includes an active layer, a pair of cladding layers, and a phase modulation layer. The phase modulation layer has a base layer and a plurality of modified refractive index regions each of which is individually arranged at a specific position. One of the pair of cladding layers includes a distributed Bragg reflector layer which has a transmission characteristic with respect to a specific optical image outputted along an inclined direction with respect to a light emission surface and has a reflection characteristic with respect to the zero-order light outputted along a normal direction of the light emission surface.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: June 30, 2020
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Kazuyoshi Hirose, Yoshitaka Kurosaka, Takahiro Sugiyama, Yuu Takiguchi, Yoshiro Nomoto
  • Publication number: 20200115227
    Abstract: Described herein is a technique capable of forming a sacrificial film with a high wet etching rate to obtain a wet etching selectivity with respect to a movable electrode when manufacturing a cantilever structure sensor using MEMS (Micro-Electro-Mechanical Systems) technology. According to one aspect of the technique of the present disclosure, there is provided a method of manufacturing a semiconductor device including: (a) loading a substrate including a control electrode, a pedestal and a counter electrode formed thereon into a process chamber; and (b) forming a sacrificial film containing impurities on the control electrode, the pedestal and the counter electrode by supplying a first process gas in a non-plasma state containing the impurities and silicon to the process chamber through a first gas supply pipe together with supplying a second process gas in a plasma state containing oxygen to the process chamber through a second gas supply pipe.
    Type: Application
    Filed: September 17, 2019
    Publication date: April 16, 2020
    Applicant: KOKUSAI ELECTRIC CORPORATION
    Inventors: Naofumi OHASHI, Yoshiro HIROSE
  • Patent number: 10613253
    Abstract: A metasurface is capable of modulating input light including a wavelength in a range of 880 nm to 40 ?m. The metasurface includes: a GaAs substrate including a light input surface into which input light is input and a light output surface facing the light input surface; an interlayer having a lower refractive index than GaAs and disposed on the light output surface side of the GaAs substrate; and a plurality of V-shaped antenna elements disposed on a side of the interlayer which is opposite to the GaAs substrate side and including a first arm and a second arm continuous with one end of the first arm.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: April 7, 2020
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Yoshiro Nomoto, Yoshitaka Kurosaka, Kazuyoshi Hirose, Takahiro Sugiyama, Soh Uenoyama
  • Publication number: 20200106240
    Abstract: The present embodiment relates to a semiconductor light-emitting element or the like including a structure for suppressing deterioration in the quality of an optical image caused by an electrode blocking a part of light outputted from a phase modulation layer. The semiconductor light-emitting element includes a phase modulation layer having a basic layer and a plurality of modified refractive index regions, and the phase modulation layer includes a first region at least partially overlapping the electrode along a lamination direction and a second region other than the first region. Among the plurality of modified refractive index regions, only one or more modified refractive index regions in the second region are disposed so as to contribute to formation of an optical image.
    Type: Application
    Filed: December 2, 2019
    Publication date: April 2, 2020
    Applicant: HAMAMATSU PHOTONICS K.K.
    Inventors: Yuu TAKIGUCHI, Kazuyoshi HIROSE, Yoshitaka KUROSAKA, Takahiro SUGIYAMA, Yoshiro NOMOTO, Soh UENOYAMA
  • Patent number: 10607833
    Abstract: There is provided a method of manufacturing a semiconductor device, including forming a film on a substrate by performing a cycle a predetermined number of times, the cycle including non-simultaneously performing supplying a precursor gas to the substrate; and supplying a first oxygen-containing gas to the substrate. Further, the act of supplying the precursor gas includes a time period in which the precursor gas and a second oxygen-containing gas are simultaneously supplied to the substrate.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: March 31, 2020
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Katsuyoshi Harada, Takashi Ozaki, Masato Terasaki, Risa Yamakoshi, Satoshi Shimamoto, Jiro Yugami, Yoshiro Hirose
  • Publication number: 20200095120
    Abstract: Described herein is a technique capable of forming a sacrificial film with a high wet etching rate so as to obtain a wet etching selectivity with respect to a movable electrode when manufacturing a cantilever structure sensor. According to one aspect of the technique of the present disclosure, there is provided a method of manufacturing a semiconductor device including: (a) placing a substrate with a sacrificial film containing impurities on a substrate support in a process chamber, wherein the sacrificial film is formed so as to cover a control electrode, a pedestal and a counter electrode formed on the substrate; (b) heating the substrate; and (c) modifying the sacrificial film into a modified sacrificial film by supplying an oxygen-containing gas in a plasma state to the substrate to desorb the impurities from the sacrificial film after (b).
    Type: Application
    Filed: September 4, 2019
    Publication date: March 26, 2020
    Inventors: Naofumi OHASHI, Yoshiro HIROSE
  • Patent number: 10600642
    Abstract: There is provided a technique which includes: forming a film containing at least Si, O and N on a substrate in a process chamber by performing a cycle a predetermined number of times, the cycle including non-simultaneously performing: forming a first layer by supplying a precursor gas containing at least a Si—N bond and a Si—Cl bond and a first catalyst gas to the substrate; exhausting the precursor gas and the first catalyst gas in the process chamber through an exhaust system; forming a second layer by supplying an oxidizing gas and a second catalyst gas to the substrate to modify the first layer; and exhausting the oxidizing gas and the second catalyst gas in the process chamber through the exhaust system.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: March 24, 2020
    Assignee: Kokusai Electric Corporation
    Inventors: Yoshiro Hirose, Yoshitomo Hashimoto
  • Patent number: 10497561
    Abstract: There is provided a method for manufacturing a semiconductor device, including: providing a substrate with an oxide film formed on a surface thereof; pre-processing a surface of the oxide film; and forming a nitride film containing carbon on the surface of the oxide film which has been pre-processed, by performing a cycle a predetermined number of times, the cycle including non-simultaneously performing: supplying a precursor gas to the substrate; supplying a carbon-containing gas to the substrate; and supplying a nitrogen-containing gas to the substrate, or by performing a cycle a predetermined number of times, the cycle including non-simultaneously performing: supplying a precursor gas to the substrate; and supplying a gas containing carbon and nitrogen to the substrate, or by performing a cycle a predetermined number of times, the cycle including non-simultaneously performing: supplying a precursor gas containing carbon to the substrate; and supplying a nitrogen-containing gas to the substrate.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: December 3, 2019
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Yoshinobu Nakamura, Kiyohiko Maeda, Yoshiro Hirose, Ryota Horiike, Yoshitomo Hashimoto
  • Publication number: 20190356113
    Abstract: In a semiconductor light emitting element provided with an active layer 4, a pair of cladding layers 2, 7 between which the active layer 4 is interposed, and a phase modulation layer 6 optically coupled to the active layer 4, the phase modulation layer 6 includes a base layer 6A and a plurality of different refractive index regions 6B having different refractive indices from the base layer 6A. When an XYZ orthogonal coordinate system having a thickness direction of the phase modulation layer 6 as a Z-axis direction is set and a square lattice of a virtual lattice constant a is set in an XY plane, each of the different refractive index regions 6B is disposed so that a centroid position G thereof is shifted from a lattice point position in a virtual square lattice by a distance r, and the distance r is 0<r?0.3a.
    Type: Application
    Filed: June 25, 2019
    Publication date: November 21, 2019
    Applicant: HAMAMATSU PHOTONICS K.K.
    Inventors: Yoshitaka KUROSAKA, Yuu Takiguchi, Takahiro Sugiyama, Kazuyoshi Hirose, Yoshiro Nomoto
  • Publication number: 20190312412
    Abstract: The present embodiment relates to a light emitting device having a structure capable of removing zero order light from output light of an S-iPM laser. The light emitting device includes a semiconductor light emitting element and a light shielding member. The semiconductor light emitting element includes an active layer, a pair of cladding layers, and a phase modulation layer. The phase modulation layer has a basic layer and a plurality of modified refractive index regions, each of which is individually disposed at a specific position. The light shielding member has a function of passing through a specific optical image output along an inclined direction and shielding zero order light output along a normal direction of a light emitting surface.
    Type: Application
    Filed: June 7, 2019
    Publication date: October 10, 2019
    Applicant: HAMAMATSU PHOTONICS K.K.
    Inventors: Yoshitaka KUROSAKA, Kazuyoshi HIROSE, Takahiro SUGIYAMA, Yuu TAKIGUCHI, Yoshiro NOMOTO
  • Publication number: 20190312410
    Abstract: A semiconductor light-emitting module according to the present embodiment includes a plurality of semiconductor light-emitting elements each outputting light of a desired beam projection pattern; and a support substrate holding the plurality of semiconductor light-emitting elements. Each of the plurality of semiconductor light-emitting elements includes a phase modulation layer configured to form a target beam projection pattern in a target beam projection region. The plurality of semiconductor light-emitting elements include first and second semiconductor light-emitting elements that are different in terms of at least any of a beam projection direction, the target beam projection pattern, and a light emission wavelength.
    Type: Application
    Filed: June 5, 2019
    Publication date: October 10, 2019
    Applicant: HAMAMATSU PHOTONICS K.K.
    Inventors: Takahiro SUGIYAMA, Yuu TAKIGUCHI, Yoshitaka KUROSAKA, Kazuyoshi HIROSE, Yoshiro NOMOTO, Soh UENOYAMA
  • Publication number: 20190288483
    Abstract: The present embodiment relates to a single semiconductor light-emitting element including a plurality of light-emitting portions each of which is capable of generating light of a desired beam projection pattern and a method for manufacturing the semiconductor light-emitting element. In the semiconductor light-emitting element, an active layer and a phase modulation layer are formed on a common substrate layer, and the phase modulation layer includes at least a plurality of phase modulation regions arranged along the common substrate layer. The plurality of phase modulation regions are obtained by separating the phase modulation layer into a plurality of places after manufacturing the phase modulation layer, and as a result, the semiconductor light-emitting element provided with a plurality of light-emitting portions that have been accurately aligned can be obtained through a simple manufacturing process as compared with the related art.
    Type: Application
    Filed: June 6, 2019
    Publication date: September 19, 2019
    Applicant: HAMAMATSU PHOTONICS K.K.
    Inventors: Takahiro SUGIYAMA, Yuu TAKIGUCHI, Yoshitaka KUROSAKA, Kazuyoshi HIROSE, Yoshiro NOMOTO, Soh UENOYAMA
  • Patent number: 10389088
    Abstract: In a semiconductor light emitting element provided with an active layer 4, a pair of cladding layers 2, 7 between which the active layer 4 is interposed, and a phase modulation layer 6 optically coupled to the active layer 4, the phase modulation layer 6 includes a base layer 6A and a plurality of different refractive index regions 6B having different refractive indices from the base layer 6A. When an XYZ orthogonal coordinate system having a thickness direction of the phase modulation layer 6 as a Z-axis direction is set and a square lattice of a virtual lattice constant a is set in an XY plane, each of the different refractive index regions 6B is disposed so that a centroid position G thereof is shifted from a lattice point position in a virtual square lattice by a distance r, and the distance r is 0<r?0.3a.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: August 20, 2019
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Yoshitaka Kurosaka, Yuu Takiguchi, Takahiro Sugiyama, Kazuyoshi Hirose, Yoshiro Nomoto
  • Publication number: 20190252856
    Abstract: The present embodiment relates to a semiconductor light emitting element having a structure that enables removal of zero-order light from output light of an S-iPM laser. The semiconductor light emitting element includes an active layer, a pair of cladding layers, and a phase modulation layer. The phase modulation layer has a base layer and a plurality of modified refractive index regions each of which is individually arranged at a specific position. One of the pair of cladding layers includes a distributed Bragg reflector layer which has a transmission characteristic with respect to a specific optical image outputted along an inclined direction with respect to a light emission surface and has a reflection characteristic with respect to the zero-order light outputted along a normal direction of the light emission surface.
    Type: Application
    Filed: March 5, 2019
    Publication date: August 15, 2019
    Applicant: HAMAMATSU PHOTONICS K.K.
    Inventors: Kazuyoshi HIROSE, Yoshitaka KUROSAKA, Takahiro SUGIYAMA, Yuu TAKIGUCHI, Yoshiro NOMOTO
  • Patent number: 10340134
    Abstract: A method includes forming a film on a substrate by performing a cycle n times (where n is an integer equal to or greater than 1), the cycle including alternately performing: performing a set m times (where m is an integer equal to or greater than 1), the set including supplying a precursor to the substrate and supplying a borazine compound to the substrate; and supplying an oxidizing agent to the substrate.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: July 2, 2019
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Yoshiro Hirose, Atsushi Sano, Katsuyoshi Harada