Patents by Inventor Yoshiro Riho
Yoshiro Riho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11914874Abstract: Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several sets of latencies (e.g., read, write, or write recovery latencies), and the memory device or system may apply a set of latencies depending on which features of the memory device are enabled. For example, control circuitry may be configured to enable one or more features during operations on a memory array, and the control circuitry may apply a set of latency values based on a number or type of features that are enabled. The sets of latency values may depend, for example, on whether various control features (e.g., dynamic voltage frequency scaling) are enabled, and a device may operate within certain frequency ranges irrespective of other characteristics (e.g., mode register values) or latencies applied.Type: GrantFiled: August 2, 2021Date of Patent: February 27, 2024Inventors: Dean D. Gans, Yoshiro Riho, Shunichi Saito, Osamu Nagashima
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Publication number: 20230343376Abstract: According to one or more embodiments, an apparatus comprising a plurality of dice latches, dice latch control logic, and a plurality of data input logic is provided. The dice latches are coupled in parallel and latch respective data. The dice latch control logic receives a load control signal and a reset control signal, provides a reset signal and further provides first and second load signals to the dice latches. The reset signal is based on the reset control signal. The first and second load signals are based on the load control signal and the reset control signal. The data input logic each are coupled to a respective one of the dice latches. Each of the data input logic receives a precharge control signal and respective input data and further provides data and complementary data to the respective one of the dice latches.Type: ApplicationFiled: June 15, 2023Publication date: October 26, 2023Applicant: MICRON TECHNOLOGY, INC.Inventors: Yoshiro Riho, Hiroshi Akamatsu, Jian Long, Kevin G. Werhane, Liang Liu, Yoshinori Fujiwara
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Patent number: 11727967Abstract: Apparatuses and methods including dice latches in a semiconductor device are disclosed. Example dice latches have a circuit arrangement that include a reduced number of circuits, such as transistors, and provides a compact layout. Operation of example dice latches and other dice latches may be controlled by separately provided control signals for loading and latching of data, and in some examples, for a reset operation. Example layouts include circuit elements aligned along a direction with at least one other circuit element offset from the other aligned circuit elements.Type: GrantFiled: January 13, 2022Date of Patent: August 15, 2023Assignee: Micron Technology, Inc.Inventors: Yoshiro Riho, Hiroshi Akamatsu, Jian Long, Kevin G. Werhane, Liang Liu, Yoshinori Fujiwara
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Publication number: 20230223059Abstract: Apparatuses and methods including dice latches in a semiconductor device are disclosed. Example dice latches have a circuit arrangement that include a reduced number of circuits, such as transistors, and provides a compact layout. Operation of example dice latches and other dice latches may be controlled by separately provided control signals for loading and latching of data, and in some examples, for a reset operation. Example layouts include circuit elements aligned along a direction with at least one other circuit element offset from the other aligned circuit elements.Type: ApplicationFiled: January 13, 2022Publication date: July 13, 2023Applicant: MICRON TECHNOLOGY, INC.Inventors: Yoshiro Riho, Hiroshi Akamatsu, Jian Long, Kevin G. Werhane, Liang Liu, Yoshinori Fujiwara
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Patent number: 11335393Abstract: Disclosed herein is an apparatus that includes a memory cell array including a plurality of memory cells, a first counter circuit configured to periodically update a count value during a first operation mode, a burst clock generator configured to successively generate a burst pulse predetermined times when the count value indicates a predetermined value, and a row address control circuit configured to perform a refresh operation on the memory cell array in response to the burst pulse.Type: GrantFiled: February 10, 2021Date of Patent: May 17, 2022Assignee: Micron Technology, Inc.Inventors: Yoshiro Riho, Yoshinori Matsui, Kiyohiro Furutani, Takahiko Fukiage, Ki-Jun Nam, John D. Porter
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Patent number: 11314591Abstract: Apparatuses and methods for error correction coding and data bus inversion for semiconductor memories are described. An example apparatus includes an I/O circuit configured to receive first data and first ECC data associated with the first data, a memory array, and a control circuit. The control circuit is coupled between the/O circuit and the memory array. The control circuit is configured to execute first ECC-decoding to produce corrected first data and corrected first ECC data responsive, at least in part, to the first data and the first ECC data. The control circuit is further configured to store both the corrected first data and the corrected first ECC data into the memory array.Type: GrantFiled: September 10, 2020Date of Patent: April 26, 2022Assignee: Micron Technology, Inc.Inventors: Yoshiro Riho, Atsushi Shimizu, Sang-Kyun Park, Jongtae Kwak
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Publication number: 20210357137Abstract: Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several sets of latencies (e.g., read, write, or write recovery latencies), and the memory device or system may apply a set of latencies depending on which features of the memory device are enabled. For example, control circuitry may be configured to enable one or more features during operations on a memory array, and the control circuitry may apply a set of latency values based on a number or type of features that are enabled. The sets of latency values may depend, for example, on whether various control features (e.g., dynamic voltage frequency scaling) are enabled, and a device may operate within certain frequency ranges irrespective of other characteristics (e.g., mode register values) or latencies applied.Type: ApplicationFiled: August 2, 2021Publication date: November 18, 2021Inventors: Dean D. Gans, Yoshiro Riho, Shunichi Saito, Osamu Nagashima
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Patent number: 11150821Abstract: Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several sets of latencies (e.g., read, write, or write recovery latencies), and the memory device or system may apply a set of latencies depending on which features of the memory device are enabled. For example, control circuitry may be configured to enable one or more features during operations on a memory array, and the control circuitry may apply a set of latency values based on a number or type of features that are enabled. The sets of latency values may depend, for example, on whether various control features (e.g., dynamic voltage frequency scaling) are enabled, and a device may operate within certain frequency ranges irrespective of other characteristics (e.g., mode register values) or latencies applied.Type: GrantFiled: August 16, 2019Date of Patent: October 19, 2021Assignee: Micron Technology, Inc.Inventors: Dean D. Gans, Yoshiro Riho, Shunichi Saito, Osamu Nagashima
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Publication number: 20210166753Abstract: Disclosed herein is an apparatus that includes a memory cell array including a plurality of memory cells, a first counter circuit configured to periodically update a count value during a first operation mode, a burst clock generator configured to successively generate a burst pulse predetermined times When the count value indicates a predetermined value, and a row address control circuit configured to perform a refresh operation on the memory cell array in response to the burst pulse.Type: ApplicationFiled: February 10, 2021Publication date: June 3, 2021Applicant: MICRON TECHNOLOGY, INC.Inventors: Yoshiro Riho, Yoshinori Matsui, Kiyohiro Furutani, Takahiko Fukiage, Ki-Jun Nam, John D. Porter
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Patent number: 10976945Abstract: Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several sets of latencies (e.g., read, write, or write recovery latencies), and the memory device or system may apply a set of latencies depending on which features of the memory device are enabled. For example, control circuitry may be configured to enable one or more features during operations on a memory array, and the control circuitry may apply a set of latency values based on a number or type of features that are enabled. The sets of latency values may depend, for example, on whether various control features (e.g., dynamic voltage frequency scaling) are enabled, and a device may operate within certain frequency ranges irrespective of other characteristics (e.g., mode register values) or latencies applied.Type: GrantFiled: July 27, 2018Date of Patent: April 13, 2021Assignee: Micron Technology, Inc.Inventors: Dean D. Gans, Yoshiro Riho, Shunichi Saito, Osamu Nagashima
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Patent number: 10923171Abstract: Disclosed herein is an apparatus that includes a memory cell array including a plurality of memory cells, a first counter circuit configured to periodically update a count value during a first operation mode, a burst clock generator configured to successively generate a burst pulse predetermined times when the count value indicates a predetermined value, and a row address control circuit configured to perform a refresh operation on the memory cell array in response to the burst pulse.Type: GrantFiled: October 17, 2018Date of Patent: February 16, 2021Assignee: Micron Technology, Inc.Inventors: Yoshiro Riho, Yoshinori Matsui, Kiyohiro Furutani, Takahiko Fukiage, Ki-Jun Nam, John D. Porter
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Publication number: 20200409786Abstract: Apparatuses and methods for error correction coding and data bus inversion for semiconductor memories are described. An example apparatus includes an I/O circuit configured to receive first data and first ECC data associated with the first data, a memory array, and a control circuit. The control circuit is coupled between the/O circuit and the memory array. The control circuit is configured to execute first ECC-decoding to produce corrected first data and corrected first ECC data responsive, at least in part, to the first data and the first ECC data. The control circuit is further configured to store both the corrected first data and the corrected first ECC data into the memory array.Type: ApplicationFiled: September 10, 2020Publication date: December 31, 2020Applicant: Micron Technology, Inc.Inventors: Yoshiro Riho, Atsushi Shimizu, Sang-Kyun Park, Jongtae Kwak
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Patent number: 10795759Abstract: Apparatuses and methods for error correction coding and data bus inversion for semiconductor memories are described. An example apparatus includes an I/O circuit configured to receive first data and first ECC data associated with the first data, a memory array, and a control circuit. The control circuit is coupled between the I/O circuit and the memory array. The control circuit is configured to execute first ECC-decoding to produce corrected first data and corrected first ECC data responsive, at least in part, to the first data and the first ECC data. The control circuit is further configured to store both the corrected first data and the corrected first ECC data into the memory array.Type: GrantFiled: September 10, 2018Date of Patent: October 6, 2020Assignee: Micron Technology, Inc.Inventors: Yoshiro Riho, Atsushi Shimizu, Sang-Kyun Park, Jongtae Kwak
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Publication number: 20200126611Abstract: Disclosed herein is an apparatus that includes a memory cell array including a plurality of memory cells, a first counter circuit configured to periodically update a count value during a first operation mode, a burst clock generator configured to successively generate a burst pulse predetermined times when the count value indicates a predetermined value, and a row address control circuit configured to perform a refresh operation on the memory cell array in response to the burst pulse.Type: ApplicationFiled: October 17, 2018Publication date: April 23, 2020Applicant: MICRON TECHNOLOGY, INC.Inventors: Yoshiro Riho, Yoshinori Matsui, Kiyohiro Furutani, Takahiko Fukiage, Ki-Jun Nam, John D. Porter
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Publication number: 20200081769Abstract: Apparatuses and methods for error correction coding and data bus inversion for semiconductor memories are described. An example apparatus includes an I/O circuit configured to receive first data and first ECC data associated with the first data, a memory array, and a control circuit. The control circuit is coupled between the I/O circuit and the memory array. The control circuit is configured to execute first ECC-decoding to produce corrected first data and corrected first ECC data responsive, at least in part, to the first data and the first ECC data. The control circuit is further configured to store both the corrected first data and the corrected first ECC data into the memory array.Type: ApplicationFiled: September 10, 2018Publication date: March 12, 2020Applicant: Micron Technology, Inc.Inventors: Yoshiro Riho, Atsushi Shimizu, Sang-Kyun Park, Jongtae Kwak
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Publication number: 20190369894Abstract: Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several sets of latencies (e.g., read, write, or write recovery latencies), and the memory device or system may apply a set of latencies depending on which features of the memory device are enabled. For example, control circuitry may be configured to enable one or more features during operations on a memory array, and the control circuitry may apply a set of latency values based on a number or type of features that are enabled. The sets of latency values may depend, for example, on whether various control features (e.g., dynamic voltage frequency scaling) are enabled, and a device may operate within certain frequency ranges irrespective of other characteristics (e.g., mode register values) or latencies applied.Type: ApplicationFiled: August 16, 2019Publication date: December 5, 2019Inventors: Dean D. Gans, Yoshiro Riho, Shunichi Saito, Osamu Nagashima
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Patent number: 10481819Abstract: Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several sets of latencies (e.g., read, write, or write recovery latencies), and the memory device or system may apply a set of latencies depending on which features of the memory device are enabled. For example, control circuitry may be configured to enable one or more features during operations on a memory array, and the control circuitry may apply a set of latency values based on a number or type of features that are enabled. The sets of latency values may depend, for example, on whether various control features (e.g., dynamic voltage frequency scaling) are enabled, and a device may operate within certain frequency ranges irrespective of other characteristics (e.g., mode register values) or latencies applied.Type: GrantFiled: October 30, 2017Date of Patent: November 19, 2019Assignee: Micron Technology, Inc.Inventors: Dean D. Gans, Yoshiro Riho, Shunichi Saito, Osamu Nagashima
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Publication number: 20190129637Abstract: Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several sets of latencies (e.g., read, write, or write recovery latencies), and the memory device or system may apply a set of latencies depending on which features of the memory device are enabled. For example, control circuitry may be configured to enable one or more features during operations on a memory array, and the control circuitry may apply a set of latency values based on a number or type of features that are enabled. The sets of latency values may depend, for example, on whether various control features (e.g., dynamic voltage frequency scaling) are enabled, and a device may operate within certain frequency ranges irrespective of other characteristics (e.g., mode register values) or latencies applied.Type: ApplicationFiled: July 27, 2018Publication date: May 2, 2019Inventors: Dean D. Gans, Yoshiro Riho, Shunichi Saito, Osamu Nagashima
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Patent number: RE47840Abstract: A method of testing a semiconductor device includes providing a first wafer that includes a first surface, a second surface that is allocated at an opposite side of the first surface, a first electrode penetrating the first wafer from the first surface to the second surface, and a pad formed on the first surface and coupled electrically with the first electrode, providing a second wafer that includes a second electrode penetrating the second wafer, stacking the first wafer onto the second wafer to connect the first electrode with the second electrode such that the second surface of the first wafer faces the second wafer, probing a needle to the pad, and supplying, in such a state that the first wafer is stacked on the second wafer, a test signal to the first electrode to input the test signal into the second wafer via the first electrode and the second electrode.Type: GrantFiled: August 6, 2015Date of Patent: February 4, 2020Assignee: LONGITUDE LICENSING LIMITEDInventor: Yoshiro Riho
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Patent number: RE49390Abstract: A method of testing a semiconductor device includes providing a first wafer that includes a first surface, a second surface that is allocated at an opposite side of the first surface, a first electrode penetrating the first wafer from the first surface to the second surface, and a pad formed on the first surface and coupled electrically with the first electrode, providing a second wafer that includes a second electrode penetrating the second wafer, stacking the first wafer onto the second wafer to connect the first electrode with the second electrode such that the second surface of the first wafer faces the second wafer, probing a needle to the pad, and supplying, in such a state that the first wafer is stacked on the second wafer, a test signal to the first electrode to input the test signal into the second wafer via the first electrode and the second electrode.Type: GrantFiled: February 3, 2020Date of Patent: January 24, 2023Assignee: LONGITUDE LICENSING LIMITEDInventor: Yoshiro Riho