Abstract: A device includes first to N-th (N is an integer of 2 or more) semiconductor chips stacked. These semiconductor chips have substantially the same configuration, and each includes an identification flag memory circuit including first to N-th memory units and a plurality of through electrodes connected to the identification flag memory circuit. Each of the through electrodes is connected to or masked with respect to the corresponding one of the through electrodes of the underlying semiconductor chip, such that an identification flag is stored in n-th (n indicates 1, 2, . . . , and N) memory units of the n-th semiconductor chips sequentially in the stacking order in response to a clock signal input in common to the first to N-th semiconductor chips, and the storage of the identification flag in the N-th memory unit of the N-th semiconductor chip can be detected from the lower side of the first semiconductor chip.

Abstract: In a semiconductor device of a stacked structure type having a control chip and a plurality of controlled chips, wherein the control chip allocates different I/O sets to the respective controlled chips and processes the I/O sets within the same access cycle, the controlled chip close to the control chip and positioned to a lower position in the stacked structure has I/O penetrating through substrate vias connected to penetrating through interconnections. The penetrating through interconnections are extended to an upper one of the controlled chips that not use the penetrating through interconnections and, as a result, all of the penetrating through interconnections have the same lengths as each other.

Abstract: A semiconductor memory device includes a plurality of banks, each of which is constituted of a plurality of memory cell arrays that are aligned in series in the longitudinal direction, wherein each memory cell array includes a plurality of memory cells, and wherein memory cell arrays of banks are collectively aggregated into a plurality of blocks, each of which includes memory cell arrays aligned in the perpendicular direction, in connection with a plurality of DQ pads. DQ pads are arranged in proximity to blocks. Substantially the same distance is set between memory cells and DQ pads so as to reduce dispersions in access times with respect to all DQ pads, thus achieving high-speed access in the semiconductor memory device. The wiring region of IO lines is reduced in the center area of the chip.

Abstract: A semiconductor device includes a column decoder that generates a column selecting signal that selects any of a plurality of bit line pairs to which memory cells are connected according to a column address that is input; a bit line selecting switch that connects by the column selecting signal any of a plurality of bit line pairs and a data I/O line pair that outputs data that has been read from a memory cell to the outside; a data amplifier that amplifies a voltage differential of a data I/O line pair and outputs data that has been read to an output buffer; a data I/O line switch that is provided in the data I/O lines; an I/O line precharge circuit that precharges a data I/O line pair that is not on the side of the data amplifier; and an amplifier precharge circuit that precharges a data I/O line pair that is on the side of the data amplifier.

Abstract: The invention provides a semiconductor device having, in each of stacked chip dies, not only vias the number of which corresponds to the number of signals input to and output from a single chip die but also vias the number of which corresponds to the number of signals input to and output from the stacked chip dies, and switches for controlling the input and output to and from the vias. The conduction and non-conduction of the switches are controlled by means of ROMs, whereby signals from the plurality of chip dies stacked can be output in parallel. This eliminates the need of increasing the data transfer speed of each chip die in accordance with the transfer speed of the system.

Abstract: A semiconductor memory device according to the present invention includes: a memory cell array having a normal memory cell and a redundant memory cell that is used to replace the normal memory cell when it is defective; a word driver selecting a predetermined word line within the memory cell array based on a row address supplied in synchronism with an active command, and canceling selection of the word line in response to a precharge command; and a signal control circuit resetting a repair address generated when the row address indicates the normal memory cell that is defective, without resetting a predecode signal generated by predecoding the row address, in response to issuance of the precharge command.

Abstract: A semiconductor memory device comprises a plate voltage generating circuit that generates a plate voltage supplied to a memory cell array and a plate voltage supply terminal that supplies a plate voltage from the outside. A first switching circuit is provided to switch the supply of the plate voltage between the supply from the plate voltage generating circuit and the supply from the outside through the plate voltage supply terminal.

Abstract: A semiconductor memory device according to the present invention includes: a memory cell array having a normal memory cell and a redundant memory cell that is used to replace the normal memory cell when it is defective; a word driver selecting a predetermined word line within the memory cell array based on a row address supplied in synchronism with an active command, and canceling selection of the word line in response to a precharge command; and a signal control circuit resetting a repair address generated when the row address indicates the normal memory cell that is defective, without resetting a predecode signal generated by predecoding the row address, in response to issuance of the precharge command.

Abstract: To provide a first power supply wiring that supplies a lower-side write potential to a sense amplifier, a second power supply wiring that supplies a higher-side write potential to the sense amplifier, a third power supply wiring that supplies an overdrive potential to the sense amplifier, and a stabilizing capacitance arranged between the first power supply wiring and the third power supply wiring. With this configuration, a capacitance value applied to the lower-side write potential and a capacitance value applied to the overdrive potential inevitably match, and thus fluctuation of the lower-side write potential and fluctuation of the overdrive potential at an initial stage of a sense operation are offset.

Abstract: A reference voltage generating circuit comprises: a monitor circuit, including a low threshold voltage PMOS transistor, a low threshold voltage NMOS transistor, and a resistor having a predetermined resistance which are connected in series, for generating a reference voltage at one end; and an additional circuit for supplying a monitor current to the monitor circuit and for controlling the other end of the monitor circuit to be at a constant voltage, wherein a voltage value of the reference voltage is corrected within a range corresponding to a process fluctuation from a predetermined center value, based on the monitor current changing in response to the process fluctuation.

Abstract: There are provided are a plurality of memory mats, a sub-word driver that accesses a normal memory cell irrespective of whether a row address to which access is requested is a defective address, a sub-word driver that accesses a redundant memory cell belonging to a memory mat different from the normal memory cell indicated by the row address, when the row address is a defective address. According to the present invention, the normal memory cell and a redundant memory cell belong to memory mats different to each other, and thus the normal memory cell can be accessed concurrently with determining operation of the repair determining circuit.

Abstract: There are provided a row predecoder that predocodes an address irrespective of whether the address to which access is requested is a defective address, a row main decoder that controls a sub-word driver, based on a predecode signal generated by the row predecoder, and a repair determining circuit that determines whether the address is a defective address. The row main decoder, the row predecoder, and the repair determining circuit all have a shape in which a column direction is set to be a longitudinal direction. The row predecoder and the repair determining circuit are arranged adjacent to each other in the column direction, and are arranged in parallel with the row main decoder.

Abstract: A test method for a semiconductor device that is provided with an ECC circuit that uses product code that is composed of a first code and a second code for implementing error correction of a memory, the test method includes steps of: obtaining first pass/fail determination results and second pass/fail determination results that are realized by independent correction operations based on the first code and the second code, respectively; recording the results in a first fail memory and a second fail memory, respectively; executing a prescribed logical operation such as an AND operation relating to the contents of the first fail memory and the contents of the second fail memory; and based on the results of the logical operation, remedying both fail bits and potential fail bits.

Abstract: A semiconductor memory device includes a plurality of banks, each of which is constituted of a plurality of memory cell arrays that are aligned in series in the longitudinal direction, wherein each memory cell array includes a plurality of memory cells, and wherein memory cell arrays of banks are collectively aggregated into a plurality of blocks, each of which includes memory cell arrays aligned in the perpendicular direction, in connection with a plurality of DQ pads. DQ pads are arranged in proximity to blocks. Substantially the same distance is set between memory cells and DQ pads so as to reduce dispersions in access times with respect to all DQ pads, thus achieving high-speed access in the semiconductor memory device. The wiring region of IO lines is reduced in the center area of the chip.

Abstract: A semiconductor device includes a column decoder that generates a column selecting signal that selects any of a plurality of bit line pairs to which memory cells are connected according to a column address that is input; a bit line selecting switch that connects by the column selecting signal any of a plurality of bit line pairs and a data I/O line pair that outputs data that has been read from a memory cell to the outside; a data amplifier that amplifies a voltage differential of a data I/O line pair and outputs data that has been read to an output buffer; a data I/O line switch that is provided in the data I/O lines; an I/O line precharge circuit that precharges a data I/O line pair that is not on the side of the data amplifier; and an amplifier precharge circuit that precharges a data I/O line pair that is on the side of the data amplifier.

Abstract: A semiconductor memory device comprises: a memory cell array in which memory cells are divided into banks; cache memories each for storing data of a word line selected by a row address; a setting register for setting a data holding capacity so that a holding area where data is held during a self refresh period and a non-holding area where data is not held during the self refresh period are commonly included in each bank; a refresh controller for outputting a row address to be refreshed at predetermined intervals during the self refresh period and for performing a refresh operation for a selected word line corresponding to the row address in an activated bank; and a bank controller for activating all banks when the selected word line is included in the holding area and inactivating all banks when the selected word Line is included in the non-holding area.

Abstract: A reference voltage generating circuit comprises: a monitor circuit, including a low threshold voltage PMOS transistor, a low threshold voltage NMOS transistor, and a resistor having a predetermined resistance which are connected in series, for generating a reference voltage at one end; and an additional circuit for supplying a monitor current to the monitor circuit and for controlling the other end of the monitor circuit to be at a constant voltage, wherein a voltage value of the reference voltage is corrected within a range corresponding to a process fluctuation from a predetermined center value, based on the monitor current changing in response to the process fluctuation.

Abstract: A test method for a semiconductor device that is provided with an ECC circuit that uses product code that is composed of a first code and a second code for implementing error correction of a memory, the test method includes steps of: obtaining first pass/fail determination results and second pass/fail determination results that are realized by independent correction operations based on the first code and the second code, respectively; recording the results in a first fail memory and a second fail memory, respectively; executing a prescribed logical operation such as an AND operation relating to the contents of the first fail memory and the contents of the second fail memory; and based on the results of the logical operation, remedying both fail bits and potential fail bits.

Abstract: A dynamic semiconductor storage device in which the power supply current during the standby time is diminished to decrease the power consumption and to suppress the chip area from increasing. During the normal operation, the information as to a word line associated with a row address accessed during the normal operation is stored in a RAM. In entering self refresh, data of memory cells connected to a word line associated with a row address accessed during the normal operation time is read out and check bits for the data are appended in an encoder and written in a check bit area. As an initializing operation for the first self refresh entry after power up sequence, the data retention time of the memory cells is inspected every word line. Based on the results of inspection, the setting value of the refresh period of the word line is determined and written in the RAM to set the word line based refresh period. During error check for the refresh operation, any error is corrected by an error correction circuit.

Abstract: Inverters are connected between a pseudo power supply wiring and a main power supply wiring, while inverters are connected between a main power supply wiring VDD and a pseudo power supply wiring. Connected to the sources of transistors are switching areas for switching to the main power supply wiring or the pseudo power supply wiring. Connected to the sources of transistors are switching areas for switching to the main power supply wiring or the pseudo power supply wiring. Even if improper connections are found or logical changes are required, the connection destination of the source is switched easily.