Abstract: A test method for a semiconductor device that is provided with an ECC circuit that uses product code that is composed of a first code and a second code for implementing error correction of a memory, the test method includes steps of: obtaining first pass/fail determination results and second pass/fail determination results that are realized by independent correction operations based on the first code and the second code, respectively; recording the results in a first fail memory and a second fail memory, respectively; executing a prescribed logical operation such as an AND operation relating to the contents of the first fail memory and the contents of the second fail memory; and based on the results of the logical operation, remedying both fail bits and potential fail bits.

Abstract: A dynamic semiconductor storage device in which the power supply current during the standby time is diminished to decrease the power consumption and to suppress the chip area from increasing. During the normal operation, the information as to a word line associated with a row address accessed during the normal operation is stored in a RAM. In entering self refresh, data of memory cells connected to a word line associated with a row address accessed during the normal operation time is read out and check bits for the data are appended in an encoder and written in a check bit area. As an initializing operation for the first self refresh entry after power up sequence, the data retention time of the memory cells is inspected every word line. Based on the results of inspection, the setting value of the refresh period of the word line is determined and written in the RAM to set the word line based refresh period. During error check for the refresh operation, any error is corrected by an error correction circuit.

Abstract: A dynamic semiconductor storage device in which the power supply current during the standby time is diminished to decrease the power consumption and to suppress the chip area from increasing. During the normal operation, the information as to a word line associated with a row address accessed during the normal operation is stored in a RAM. In entering self refresh, data of memory cells connected to a word line associated with a row address accessed during the normal operation time is read out and check bits for the data are appended in an encoder and written in a check bit area. As an initializing operation for the first self refresh entry after power up sequence, the data retention time of the memory cells is inspected every word line. Based on the results of inspection, the setting value of the refresh period of the word line is determined and written in the RAM to set the word line based refresh period. During error check for the refresh operation, any error is corrected by an error correction circuit.

Abstract: A refresh control method of a semiconductor memory device which controls a self-refresh operation to hold data in a memory array having a plurality of memory cells disposed at intersections of word lines corresponding to row addresses and bit lines corresponding to column addresses, comprising: a step for dividing the memory array into a holding area used as a copy source which includes memory cells on a predetermined number of word lines, and a copy area used as a copy destination which includes memory cells on word lines to which entire data of the holding area is to be copied, a step for executing copy operation in which data of each memory cell of the holding area is copied to one or more memory cells in the copy area on the same bit line or the same pair of bit lines before executing the self-refresh operation, and a step for executing the self-refresh operation in which a row address of the holding area is designated and a corresponding word line is selected and driven, and at the same time, one or more

Abstract: A dynamic semiconductor storage device in which the power supply current during the standby time is diminished to decrease the power consumption and to suppress the chip area from increasing. During the normal operation, the information as to a word line associated with a row address accessed during the normal operation is stored in a RAM. In entering self refresh, data of memory cells connected to a word line associated with a row address accessed during the normal operation time is read out and check bits for the data are appended in an encoder and written in a check bit area. As an initializing operation for the first self refresh entry after power up sequence, the data retention time of the memory cells is inspected every word line. Based on the results of inspection, the setting value of the refresh period of the word line is determined and written in the RAM to set the word line based refresh period. During error check for the refresh operation, any error is corrected by an error correction circuit.

Abstract: A dynamic semiconductor storage device in which the power supply current during the standby time is diminished to decrease the power consumption and to suppress the chip area from increasing. During the normal operation, the information as to a word line associated with a row address accessed during the normal operation is stored in a RAM. In entering self refresh, data of memory cells connected to a word line associated with a row address accessed during the normal operation time is read out and check bits for the data are appended in an encoder and written in a check bit area. As an initializing operation for the first self refresh entry after power up sequence, the data retention time of the memory cells is inspected every word line. Based on the results of inspection, the setting value of the refresh period of the word line is determined and written in the RAM to set the word line based refresh period. During error check for the refresh operation, any error is corrected by an error correction circuit.

Abstract: A semiconductor storage device having a memory cell array in which a plurality of memory cells is provided at intersections of a plurality of bit lines and a plurality of word lines and executing refreshing for holding data, including: memory cells for pairing provided on the memory cell array, for compensating for errors of each memory cell; a control circuit for checking a data holding ability of memory cell under test in a predetermined period after power-on; a storage circuit for storing information which specifies the memory cells under test for which it is determined that the data holding ability is low in the checking of the control circuit; and a selecting-line activating circuit for activating circuit for activating a selecting line for pairing corresponding to the memory cells for pairing based on a result of comparing a specific address to be input with the information stored in the storage circuit.

Abstract: A refresh control method of a semiconductor memory device which controls a self-refresh operation to hold data in a memory array having a plurality of memory cells disposed at intersections of word lines corresponding to row addresses and bit lines corresponding to column addresses, comprising: a step for dividing the memory array into a holding area used as a copy source which includes memory cells on a predetermined number of word lines, and a copy area used as a copy destination which includes memory cells on word lines to which entire data of the holding area is to be copied, a step for executing copy operation in which data of each memory cell of the holding area is copied to one or more memory cells in the copy area on the same bit line or the same pair of bit lines before executing the self-refresh operation, and a step for executing the self-refresh operation in which a row address of the holding area is designated and a corresponding word line is selected and driven, and at the same time, one or more

Abstract: A test method for a semiconductor device that is provided with an ECC circuit that uses product code that is composed of a first code and a second code for implementing error correction of a memory, the test method includes steps of: obtaining first pass/fail determination results and second pass/fail determination results that are realized by independent correction operations based on the first code and the second code, respectively; recording the results in a first fail memory and a second fail memory, respectively; executing a prescribed logical operation such as an AND operation relating to the contents of the first fail memory and the contents of the second fail memory; and based on the results of the logical operation, remedying both fail bits and potential fail bits.

Abstract: A semiconductor storage device having a memory cell array in which a plurality of memory cells is provided at intersections of a plurality of bit lines and a plurality of word lines and executing refreshing for holding data, comprising: memory cells for pairing provided on the memory cell array, for compensating for errors of each memory cell; a control circuit for checking a data holding ability of memory cell under test in a predetermined period after power-on; a storage circuit for storing information which specifies the memory cells under test for which it is determined that the data holding ability is low in the checking of the control circuit; and a selecting-line activating circuit for activating circuit for activating a selecting line for pairing corresponding to the memory cells for pairing based on a result of comparing a specific address to be input with the information stored in the storage circuit.

Abstract: Disclosed is a dynamic semiconductor storage device in which the power supply current during the standby time is diminished to decrease the power consumption and to suppress the chip area from increasing. During the normal operation, the information as to a word line associated with a row address accessed during the normal operation is stored in a RAM. In entering self refresh, data of memory cells connected to a word line associated with a row address accessed during the normal operation time is read out and check bits for the data are appended in an encoder and written in a check bit area. As an initializing operation for the first self refresh entry after power up sequence, the data retention time of the memory cells is inspected every word line. Based on the results of inspection, the setting value of the refresh period of the word line is determined and written in the RAM to set the word line based refresh period.

Abstract: In a semiconductor integrated circuit device which comprises a first interconnect channel including a plurality of second-layer metal interconnect layers extended in a first direction over a semiconductor chip, a second interconnect channel including a plurality of, third-layer metal interconnect layers extended in a second direction perpendicular to the first direction, an internal power supply circuit which receives a source voltage supplied from an external terminal and generates a voltage different from the source voltage, and which is provided with stabilizing capacitors, a large part of the stabilizing capacitors are formed in an area in which the second- and third-layer metal interconnect lines intersect each other.

Abstract: In a semiconductor integrated circuit device which comprises a first interconnect channel including a plurality of second-layer metal interconnect layers extended in a first direction over a semiconductor chip, a second interconnect channel including a plurality of third-layer metal interconnect layers extended in a second direction perpendicular to the first direction, an internal power supply circuit which receives a source voltage supplied from an external terminal and generates a voltage different from the source voltage, and which is provided with stabilizing capacitors, a large part of the stabilizing capacitors are occupied by capacitors formed in an area in which the second- and third-layer metal interconnect lines intersect each other.

Abstract: In a semiconductor integrated circuit device which comprises a first interconnect channel including a plurality of second-layer metal interconnect layers extended in a first direction over a semiconductor chip, a second interconnect channel including a plurality of third-layer metal interconnect layers extended in a second direction perpendicular to the first direction, an internal power supply circuit which receives a source voltage supplied from an external terminal and generates a voltage different from the source voltage, and which is provided with stabilizing capacitors, a large part of the stabilizing capacitors are in an area in which the second- and third-layer metal interconnect lines intersect each other.