Patents by Inventor Yoshitaka Yamamoto

Yoshitaka Yamamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10374097
    Abstract: To provide a transistor having a high on-state current. A semiconductor device includes a first insulator containing excess oxygen, a first oxide semiconductor over the first insulator, a second oxide semiconductor over the first oxide semiconductor, a first conductor and a second conductor which are over the second oxide semiconductor and are separated from each other, a third oxide semiconductor in contact with side surfaces of the first oxide semiconductor, a top surface and side surfaces of the second oxide semiconductor, a top surface of the first conductor, and a top surface of the second conductor, a second insulator over the third oxide semiconductor, and a third conductor facing a top surface and side surfaces of the second oxide semiconductor with the second insulator and the third oxide semiconductor therebetween. The first oxide semiconductor has a higher oxygen-transmitting property than the third oxide semiconductor.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: August 6, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Akihisa Shimomura, Yuhei Sato, Yasumasa Yamane, Yoshitaka Yamamoto, Hideomi Suzawa, Tetsuhiro Tanaka, Yutaka Okazaki, Naoki Okuno, Takahisa Ishiyama
  • Publication number: 20180233597
    Abstract: A manufacturing method of a semiconductor device in which the threshold is adjusted to an appropriate value is provided. The semiconductor device includes a semiconductor, a source or drain electrode electrically connected to the semiconductor, a first gate electrode and a second gate electrode between which the semiconductor is sandwiched, an electron trap layer between the first gate electrode and the semiconductor, and a gate insulating layer between the second gate electrode and the semiconductor. By keeping a potential of the first gate electrode higher than a potential of the source or drain electrode for 1 second or more while heating, electrons are trapped in the electron trap layer. Consequently, threshold is increased and Icut is reduced.
    Type: Application
    Filed: April 5, 2018
    Publication date: August 16, 2018
    Inventors: Yoshitaka YAMAMOTO, Tetsuhiro TANAKA, Toshihiko TAKEUCHI, Yasumasa YAMANE, Takayuki INOUE, Shunpei YAMAZAKI
  • Publication number: 20180151743
    Abstract: To provide a transistor having a high on-state current. A semiconductor device includes a first insulator containing excess oxygen, a first oxide semiconductor over the first insulator, a second oxide semiconductor over the first oxide semiconductor, a first conductor and a second conductor which are over the second oxide semiconductor and are separated from each other, a third oxide semiconductor in contact with side surfaces of the first oxide semiconductor, a top surface and side surfaces of the second oxide semiconductor, a top surface of the first conductor, and a top surface of the second conductor, a second insulator over the third oxide semiconductor, and a third conductor facing a top surface and side surfaces of the second oxide semiconductor with the second insulator and the third oxide semiconductor therebetween. The first oxide semiconductor has a higher oxygen-transmitting property than the third oxide semiconductor.
    Type: Application
    Filed: January 9, 2018
    Publication date: May 31, 2018
    Inventors: Shunpei YAMAZAKI, Akihisa SHIMOMURA, Yuhei SATO, Yasumasa YAMANE, Yoshitaka YAMAMOTO, Hideomi SUZAWA, Tetsuhiro TANAKA, Yutaka OKAZAKI, Naoki OKUNO, Takahisa ISHIYAMA
  • Patent number: 9960416
    Abstract: The present invention provides a positive electrode for a non-aqueous electrolyte secondary battery in which the charge/discharge rate of a secondary battery is increased by increasing the discharge/discharge rate of the positive electrode as a result of increasing the rate of incorporation and release of lithium ions in olivine-type phosphorous complex compound particles, a non-aqueous electrolyte secondary battery provided with this positive electrode for a non-aqueous electrolyte secondary battery, and a battery module provided with this non-aqueous electrolyte secondary battery.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: May 1, 2018
    Assignee: SUMITOMO OSAKA CEMENT CO., LTD.
    Inventors: Tomitaro Hara, Takao Fukunaga, Takayasu Iguchi, Takao Kitagawa, Yoshitaka Yamamoto
  • Patent number: 9947800
    Abstract: A transistor with favorable electrical characteristics, a transistor with stable electrical characteristics, or a highly integrated semiconductor device is provided. In a top-gate transistor in which an oxide semiconductor is used for a semiconductor layer where a channel is formed, elements are introduced to the semiconductor layer in a self-aligned manner after a gate electrode is formed. After that, a side surface of the gate electrode is covered with a structure body. The structure body preferably contains silicon oxide. A first insulating layer is formed to cover the semiconductor layer, the gate electrode, and the structure body. A second insulating layer is formed by a sputtering method over the first insulating layer. Oxygen is introduced to the first insulating layer when the second insulating layer is formed.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: April 17, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yoshitaka Yamamoto
  • Patent number: 9939127
    Abstract: A lighting device (100) includes: a surface light source (1); a first lens (L1) having a first focal point (F1), the first lens being provided on the light exit surface side of the surface light source; and a second lens (L2) having a second focal point (F2), the second lens being provided on a light exit surface side of the first lens, the surface light source, the first lens, and the second lens being configured such that a first virtual image (I1) is formed by the first lens and a second virtual image (I2) is formed by the second lens, wherein the first virtual image (I1) is formed between the second focal point (F2) and the first lens, and the second focal point (F2) is on a side opposite to the light source side relative to a predetermined focal position f?.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: April 10, 2018
    Assignees: Sharp Kabushiki Kaisha, TOHOKU UNIVERSITY
    Inventors: Tatsuo Uchida, Yoshito Suzuki, Tohru Kawakami, Takahiro Ishinabe, Katsunori Ehara, Yoshihiro Hashimoto, Toshiki Matsuoka, Kozo Nakamura, Yasuhisa Itoh, Yoshitaka Yamamoto, Yutaka Ishii, David Montgomery
  • Patent number: 9893194
    Abstract: A method for adjusting threshold of a semiconductor device is provided. In a plurality of semiconductor devices each including a semiconductor, a source or drain electrode electrically in contact with the semiconductor, a gate electrode, and a charge trap layer between a gate electrode and the semiconductor, a state where the potential of the gate electrode is set higher than the potential of the source or drain electrode while the semiconductor devices are heated at 150° C. or higher and 300° C. or lower is kept for one second or longer to trap electrons in the charge trap layer, so that the threshold is increased and Icut is reduced. Here, the potential difference between the gate electrode and the source or drain electrode is set so that it is different between the semiconductor devices, and the thresholds of the semiconductor devices are adjusted to be appropriate to each purpose.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: February 13, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshitaka Yamamoto, Tetsuhiro Tanaka, Takayuki Inoue, Hideomi Suzawa
  • Patent number: 9882059
    Abstract: To provide a transistor having a high on-state current. A semiconductor device includes a first insulator containing excess oxygen, a first oxide semiconductor over the first insulator, a second oxide semiconductor over the first oxide semiconductor, a first conductor and a second conductor which are over the second oxide semiconductor and are separated from each other, a third oxide semiconductor in contact with side surfaces of the first oxide semiconductor, a top surface and side surfaces of the second oxide semiconductor, a top surface of the first conductor, and a top surface of the second conductor, a second insulator over the third oxide semiconductor, and a third conductor facing a top surface and side surfaces of the second oxide semiconductor with the second insulator and the third oxide semiconductor therebetween. The first oxide semiconductor has a higher oxygen-transmitting property than the third oxide semiconductor.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: January 30, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Akihisa Shimomura, Yuhei Sato, Yasumasa Yamane, Yoshitaka Yamamoto, Hideomi Suzawa, Tetsuhiro Tanaka, Yutaka Okazaki, Naoki Okuno, Takahisa Ishiyama
  • Patent number: 9812466
    Abstract: A highly reliable semiconductor device that is suitable for high-speed operation is provided. A semiconductor device includes a first circuit, a second circuit, and a third circuit. The first circuit has an arithmetic processing function. The second circuit includes a memory circuit. The memory circuit includes a transistor which includes a first conductor, a second conductor, a first insulator, a second insulator, and a semiconductor. The first conductor includes a region overlapping the semiconductor with the first insulator positioned between the first conductor and the semiconductor. The second conductor includes a region overlapping the semiconductor with the second insulator positioned between the second conductor and the semiconductor. The first conductor is capable of selecting on or off of the transistor. The third circuit is electrically connected to the second conductor, and is capable of changing the potential of the second conductor in synchronization with an operation of the transistor.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: November 7, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tomoaki Atsumi, Masayuki Sakakura, Yoshitaka Yamamoto, Jun Koyama, Tetsuhiro Tanaka, Kazuki Tanemura
  • Publication number: 20170271521
    Abstract: A transistor with favorable electrical characteristics, a transistor with stable electrical characteristics, or a highly integrated semiconductor device is provided. In a top-gate transistor in which an oxide semiconductor is used for a semiconductor layer where a channel is formed, elements are introduced to the semiconductor layer in a self-aligned manner after a gate electrode is formed. After that, a side surface of the gate electrode is covered with a structure body. The structure body preferably contains silicon oxide. A first insulating layer is formed to cover the semiconductor layer, the gate electrode, and the structure body. A second insulating layer is formed by a sputtering method over the first insulating layer. Oxygen is introduced to the first insulating layer when the second insulating layer is formed.
    Type: Application
    Filed: June 1, 2017
    Publication date: September 21, 2017
    Inventors: Shunpei YAMAZAKI, Yoshitaka YAMAMOTO
  • Patent number: 9748563
    Abstract: An electrode material of the present invention includes surface-coated LixAyDzPO4 particles obtained by coating surfaces of LixAyDzPO4 (in which, A represents one or more selected from the group consisting of Co, Mn, Ni, Fe, Cu and Cr, D represents one or more selected from the group consisting of Mg, Ca, Sr, Ba, Ti, Zn, B, Al, Ga, In, Si, Ge, Sc, Y and rare earth elements, 0<x?2, 0<y?1, and 0?z?1.5) particles with a carbonaceous coat, and an elution amount of Li is in a range of 200 ppm to 700 ppm and an elution amount of P is in a range of 500 ppm to 2000 ppm when the surface-coated LixAyDzPO4 particles are immersed in a sulfuric acid solution having a hydrogen-ion exponent of 4 for 24 hours.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: August 29, 2017
    Assignee: SUMITOMO OSAKA CEMENT CO., LTD.
    Inventors: Akinori Yamazaki, Yoshitaka Yamamoto, Takao Kitagawa, Hirofumi Yasumiishi
  • Patent number: 9685560
    Abstract: A transistor with favorable electrical characteristics, a transistor with stable electrical characteristics, or a highly integrated semiconductor device is provided. In a top-gate transistor in which an oxide semiconductor is used for a semiconductor layer where a channel is formed, elements are introduced to the semiconductor layer in a self-aligned manner after a gate electrode is formed. After that, a side surface of the gate electrode is covered with a structure body. The structure body preferably contains silicon oxide. A first insulating layer is formed to cover the semiconductor layer, the gate electrode, and the structure body. A second insulating layer is formed by a sputtering method over the first insulating layer. Oxygen is introduced to the first insulating layer when the second insulating layer is formed.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: June 20, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yoshitaka Yamamoto
  • Patent number: 9672873
    Abstract: A novel semiconductor device where multilevel data can be written and read. The semiconductor device includes first to fifth transistors, a capacitor, a bit line, and a power supply line. Write operation is performed in such a manner that first data is supplied to a gate of the fifth transistor through the first transistor; the first transistor is turned off; second data is supplied to a second electrode of the capacitor through the second transistor to convert the first data into third data; and the second electrode of the capacitor are made electrically floating. The second electrode of the capacitor is initialized to GND through the third transistor. Read operation is performed by charging or discharging the bit line through the fourth transistor and the fifth transistor. The first to third transistors are preferably oxide semiconductor transistors.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: June 6, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshitaka Yamamoto, Kiyoshi Kato
  • Patent number: 9543295
    Abstract: A semiconductor device that includes transistors with different threshold voltages is provided. Alternatively, a semiconductor device including a plurality of kinds of circuits and transistors whose electrical characteristics are different between the circuits is provided. The semiconductor device includes a first transistor and a second transistor. The first transistor includes an oxide semiconductor, a conductor, a first insulator, a second insulator, and a third insulator. The conductor has a region where the conductor and the oxide semiconductor overlap with each other. The first insulator is positioned between the conductor and the oxide semiconductor. The second insulator is positioned between the conductor and the first insulator. The third insulator is positioned between the conductor and the second insulator. The second insulator has a negatively charged region.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: January 10, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshitaka Yamamoto, Masayuki Sakakura, Tetsuhiro Tanaka, Daisuke Matsubayashi
  • Patent number: 9525023
    Abstract: One embodiment of the present invention is a semiconductor device which includes a gate electrode; a gate insulating film formed to cover the gate electrode; a semiconductor layer formed over the gate insulating film and placed above the gate electrode; a second insulating film formed over the semiconductor layer; a first insulating film formed over a top surface and a side surface of the second insulating film, a side surface of the semiconductor layer, and the gate insulating film; silicon layers and which are formed over the first insulating film and electrically connected to the semiconductor layer; and a source electrode and a drain electrode which are formed over the silicon layers. The source electrode and the drain electrode are electrically separated from each other over the first insulating film. The semiconductor layer is not in contact with each of the source electrode and the drain electrode.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: December 20, 2016
    Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Hidekazu Miyairi, Koji Dairiki, Yasuhiro Jinbo, Tomohiro Kimura, Yoshitaka Yamamoto
  • Publication number: 20160343870
    Abstract: A semiconductor device in which the threshold is adjusted is provided. In a transistor including a semiconductor, a source or drain electrode electrically connected to the semiconductor, a gate electrode, and an electron trap layer between the gate electrode and the semiconductor, the electron trap layer includes crystallized hafnium oxide. The crystallized hafnium oxide is deposited by a sputtering method using hafnium oxide as a target. When the substrate temperature is Tsub (° C.) and the proportion of oxygen in an atmosphere is P (%) in the sputtering method, P?45?0.15×Tsub is satisfied. The crystallized hafnium oxide has excellent electron trapping properties. By the trap of an appropriate number of electrons, the threshold of the semiconductor device can be adjusted.
    Type: Application
    Filed: August 8, 2016
    Publication date: November 24, 2016
    Inventors: Yoshitaka YAMAMOTO, Tetsuhiro TANAKA, Takayuki INOUE, Hideomi SUZAWA
  • Publication number: 20160276489
    Abstract: An object is to suppress conducting-mode failures of a transistor that uses an oxide semiconductor film and has a short channel length. A semiconductor device includes a gate electrode 304, a gate insulating film 306 formed over the gate electrode, an oxide semiconductor film 308 over the gate insulating film, and a source electrode 310a and a drain electrode 310b formed over the oxide semiconductor film. The channel length L of the oxide semiconductor film is more than or equal to 1 ?m and less than or equal to 50 ?m. The oxide semiconductor film has a peak at a rotation angle 2? in the vicinity of 31° in X-ray diffraction measurement.
    Type: Application
    Filed: May 31, 2016
    Publication date: September 22, 2016
    Applicants: Semiconductor Energy Laboratory Co., Ltd., SHARP KABUSHIKI KAISHA
    Inventors: Kenichi OKAZAKI, Masatoshi YOKOYAMA, Masayuki SAKAKURA, Yukinori SHIMA, Yosuke KANZAKI, Hiroshi MATSUKIZONO, Takuya MATSUO, Yoshitaka YAMAMOTO
  • Patent number: 9450080
    Abstract: The semiconductor device is manufactured by the following method. A first oxide semiconductor film is formed over a first gate electrode and a first insulating film, oxygen is added to the first oxide semiconductor film, and then a second oxide semiconductor film is formed over the first oxide semiconductor film. Then, heat treatment is performed. Next, part of the first insulating film, part of the first oxide semiconductor film, and part of the second oxide semiconductor film are etched to form a first gate insulating film having a projection. Next, a pair of electrodes is formed over the second oxide semiconductor film, and a third oxide semiconductor film is formed over the second oxide semiconductor film and the pair of electrodes. Then, a second gate insulating film is formed over the third oxide semiconductor film, and a second gate electrode is formed over the second gate insulating film.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: September 20, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Naoto Yamade, Yoshitaka Yamamoto, Hideomi Suzawa, Masayuki Sakakura, Yuhei Sato, Yasumasa Yamane
  • Patent number: 9449853
    Abstract: A semiconductor device in which the threshold is adjusted is provided. In a transistor including a semiconductor, a source or drain electrode electrically connected to the semiconductor, a gate electrode, and an electron trap layer between the gate electrode and the semiconductor, the electron trap layer includes crystallized hafnium oxide. The crystallized hafnium oxide is deposited by a sputtering method using hafnium oxide as a target. When the substrate temperature is Tsub (° C.) and the proportion of oxygen in an atmosphere is P (%) in the sputtering method, P?45?0.15×Tsub is satisfied. The crystallized hafnium oxide has excellent electron trapping properties. By the trap of an appropriate number of electrons, the threshold of the semiconductor device can be adjusted.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: September 20, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshitaka Yamamoto, Tetsuhiro Tanaka, Takayuki Inoue, Hideomi Suzawa
  • Publication number: 20160267950
    Abstract: A novel semiconductor device where multilevel data can be written and read. The semiconductor device includes first to fifth transistors, a capacitor, a bit line, and a power supply line. Write operation is performed in such a manner that first data is supplied to a gate of the fifth transistor through the first transistor; the first transistor is turned off; second data is supplied to a second electrode of the capacitor through the second transistor to convert the first data into third data; and the second electrode of the capacitor are made electrically floating. The second electrode of the capacitor is initialized to GND through the third transistor. Read operation is performed by charging or discharging the bit line through the fourth transistor and the fifth transistor. The first to third transistors are preferably oxide semiconductor transistors.
    Type: Application
    Filed: May 20, 2016
    Publication date: September 15, 2016
    Inventors: Yoshitaka YAMAMOTO, Kiyoshi KATO