Patents by Inventor Yoshitaka Yamamoto

Yoshitaka Yamamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9525023
    Abstract: One embodiment of the present invention is a semiconductor device which includes a gate electrode; a gate insulating film formed to cover the gate electrode; a semiconductor layer formed over the gate insulating film and placed above the gate electrode; a second insulating film formed over the semiconductor layer; a first insulating film formed over a top surface and a side surface of the second insulating film, a side surface of the semiconductor layer, and the gate insulating film; silicon layers and which are formed over the first insulating film and electrically connected to the semiconductor layer; and a source electrode and a drain electrode which are formed over the silicon layers. The source electrode and the drain electrode are electrically separated from each other over the first insulating film. The semiconductor layer is not in contact with each of the source electrode and the drain electrode.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: December 20, 2016
    Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Hidekazu Miyairi, Koji Dairiki, Yasuhiro Jinbo, Tomohiro Kimura, Yoshitaka Yamamoto
  • Publication number: 20160343870
    Abstract: A semiconductor device in which the threshold is adjusted is provided. In a transistor including a semiconductor, a source or drain electrode electrically connected to the semiconductor, a gate electrode, and an electron trap layer between the gate electrode and the semiconductor, the electron trap layer includes crystallized hafnium oxide. The crystallized hafnium oxide is deposited by a sputtering method using hafnium oxide as a target. When the substrate temperature is Tsub (° C.) and the proportion of oxygen in an atmosphere is P (%) in the sputtering method, P?45?0.15×Tsub is satisfied. The crystallized hafnium oxide has excellent electron trapping properties. By the trap of an appropriate number of electrons, the threshold of the semiconductor device can be adjusted.
    Type: Application
    Filed: August 8, 2016
    Publication date: November 24, 2016
    Inventors: Yoshitaka YAMAMOTO, Tetsuhiro TANAKA, Takayuki INOUE, Hideomi SUZAWA
  • Publication number: 20160276489
    Abstract: An object is to suppress conducting-mode failures of a transistor that uses an oxide semiconductor film and has a short channel length. A semiconductor device includes a gate electrode 304, a gate insulating film 306 formed over the gate electrode, an oxide semiconductor film 308 over the gate insulating film, and a source electrode 310a and a drain electrode 310b formed over the oxide semiconductor film. The channel length L of the oxide semiconductor film is more than or equal to 1 ?m and less than or equal to 50 ?m. The oxide semiconductor film has a peak at a rotation angle 2? in the vicinity of 31° in X-ray diffraction measurement.
    Type: Application
    Filed: May 31, 2016
    Publication date: September 22, 2016
    Applicants: Semiconductor Energy Laboratory Co., Ltd., SHARP KABUSHIKI KAISHA
    Inventors: Kenichi OKAZAKI, Masatoshi YOKOYAMA, Masayuki SAKAKURA, Yukinori SHIMA, Yosuke KANZAKI, Hiroshi MATSUKIZONO, Takuya MATSUO, Yoshitaka YAMAMOTO
  • Patent number: 9449853
    Abstract: A semiconductor device in which the threshold is adjusted is provided. In a transistor including a semiconductor, a source or drain electrode electrically connected to the semiconductor, a gate electrode, and an electron trap layer between the gate electrode and the semiconductor, the electron trap layer includes crystallized hafnium oxide. The crystallized hafnium oxide is deposited by a sputtering method using hafnium oxide as a target. When the substrate temperature is Tsub (° C.) and the proportion of oxygen in an atmosphere is P (%) in the sputtering method, P?45?0.15×Tsub is satisfied. The crystallized hafnium oxide has excellent electron trapping properties. By the trap of an appropriate number of electrons, the threshold of the semiconductor device can be adjusted.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: September 20, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshitaka Yamamoto, Tetsuhiro Tanaka, Takayuki Inoue, Hideomi Suzawa
  • Patent number: 9450080
    Abstract: The semiconductor device is manufactured by the following method. A first oxide semiconductor film is formed over a first gate electrode and a first insulating film, oxygen is added to the first oxide semiconductor film, and then a second oxide semiconductor film is formed over the first oxide semiconductor film. Then, heat treatment is performed. Next, part of the first insulating film, part of the first oxide semiconductor film, and part of the second oxide semiconductor film are etched to form a first gate insulating film having a projection. Next, a pair of electrodes is formed over the second oxide semiconductor film, and a third oxide semiconductor film is formed over the second oxide semiconductor film and the pair of electrodes. Then, a second gate insulating film is formed over the third oxide semiconductor film, and a second gate electrode is formed over the second gate insulating film.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: September 20, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Naoto Yamade, Yoshitaka Yamamoto, Hideomi Suzawa, Masayuki Sakakura, Yuhei Sato, Yasumasa Yamane
  • Publication number: 20160267950
    Abstract: A novel semiconductor device where multilevel data can be written and read. The semiconductor device includes first to fifth transistors, a capacitor, a bit line, and a power supply line. Write operation is performed in such a manner that first data is supplied to a gate of the fifth transistor through the first transistor; the first transistor is turned off; second data is supplied to a second electrode of the capacitor through the second transistor to convert the first data into third data; and the second electrode of the capacitor are made electrically floating. The second electrode of the capacitor is initialized to GND through the third transistor. Read operation is performed by charging or discharging the bit line through the fourth transistor and the fifth transistor. The first to third transistors are preferably oxide semiconductor transistors.
    Type: Application
    Filed: May 20, 2016
    Publication date: September 15, 2016
    Inventors: Yoshitaka YAMAMOTO, Kiyoshi KATO
  • Publication number: 20160260835
    Abstract: A transistor with favorable electrical characteristics, a transistor with stable electrical characteristics, or a highly integrated semiconductor device is provided. In a top-gate transistor in which an oxide semiconductor is used for a semiconductor layer where a channel is formed, elements are introduced to the semiconductor layer in a self-aligned manner after a gate electrode is formed. After that, a side surface of the gate electrode is covered with a structure body. The structure body preferably contains silicon oxide. A first insulating layer is formed to cover the semiconductor layer, the gate electrode, and the structure body. A second insulating layer is formed by a sputtering method over the first insulating layer. Oxygen is introduced to the first insulating layer when the second insulating layer is formed.
    Type: Application
    Filed: March 1, 2016
    Publication date: September 8, 2016
    Inventors: Shunpei YAMAZAKI, Yoshitaka YAMAMOTO
  • Patent number: 9401396
    Abstract: Provided is a method for manufacturing a semiconductor device, in which a degradation of characteristics of a thin film transistor can be suppressed by performing plasma oxidation treatment on a gate insulating film containing nitrogen. An embodiment of the present invention is a method for manufacturing a semiconductor device comprising a thin film transistor including a gate electrode, a gate insulating film containing nitrogen, and a channel region in microcrystalline semiconductor films. The method includes the steps of performing plasma treatment on the gate insulating film in an oxidizing gas atmosphere containing hydrogen and an oxidizing gas containing an oxygen atom, and forming the microcrystalline semiconductor film over the gate insulating film. Formula (1), a/b?2, and Formula (2), b>0, are satisfied, where the amount of hydrogen and the amount of the oxidizing gas in the oxidizing gas atmosphere are a and b, respectively.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: July 26, 2016
    Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Kanta Abe, Hidekazu Miyairi, Tetsuhiro Tanaka, Takashi Ienaga, Yoshitaka Yamamoto
  • Patent number: 9362411
    Abstract: An object is to suppress conducting-mode failures of a transistor that uses an oxide semiconductor film and has a short channel length. A semiconductor device includes a gate electrode 304, a gate insulating film 306 formed over the gate electrode, an oxide semiconductor film 308 over the gate insulating film, and a source electrode 310a and a drain electrode 310b formed over the oxide semiconductor film. The channel length L of the oxide semiconductor film is more than or equal to 1 ?m and less than or equal to 50 ?m. The oxide semiconductor film has a peak at a rotation angle 2? in the vicinity of 31° in X-ray diffraction measurement.
    Type: Grant
    Filed: April 12, 2013
    Date of Patent: June 7, 2016
    Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Kenichi Okazaki, Masatoshi Yokoyama, Masayuki Sakakura, Yukinori Shima, Yosuke Kanzaki, Hiroshi Matsukizono, Takuya Matsuo, Yoshitaka Yamamoto
  • Patent number: 9349418
    Abstract: A novel semiconductor device where multilevel data can be written and read. The semiconductor device includes first to fifth transistors, a capacitor, a bit line, and a power supply line. Write operation is performed in such a manner that first data is supplied to a gate of the fifth transistor through the first transistor; the first transistor is turned off; second data is supplied to a second electrode of the capacitor through the second transistor to convert the first data into third data; and the second electrode of the capacitor are made electrically floating. The second electrode of the capacitor is initialized to GND through the third transistor. Read operation is performed by charging or discharging the bit line through the fourth transistor and the fifth transistor. The first to third transistors are preferably oxide semiconductor transistors.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: May 24, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshitaka Yamamoto, Kiyoshi Kato
  • Patent number: 9331207
    Abstract: A semiconductor device includes a gate electrode; a gate insulating film over the gate electrode; an oxide semiconductor film in contact with the gate insulating film and including a channel formation region which overlaps with the gate electrode; a source electrode and a drain electrode over the oxide semiconductor film; and an oxide insulating film over the oxide semiconductor film, the source electrode, and the drain electrode. The source electrode and the drain electrode each include a first metal film having an end portion at the end of the channel formation region, a second metal film over the first metal film and containing copper, and a third metal film over the second metal film. The second metal film is formed on the inner side than the end portion of the first metal film.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: May 3, 2016
    Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Shunpei Yamazaki, Naoya Sakamoto, Takahiro Sato, Shunsuke Koshioka, Takayuki Cho, Yoshitaka Yamamoto, Takuya Matsuo, Hiroshi Matsukizono, Yosuke Kanzaki
  • Patent number: 9310619
    Abstract: To provide a thin optical sheet having improved efficiency for light utilization, an optical sheet (5) of one mode of the present invention includes, in sequence from a light entry side to a light emission side, a plurality of first prisms (13), a ¼ wavelength plate (11), and a polarized-light separating element (12), the plurality of first prisms (13) each having (i) a first surface (13a) through which light enters the first prism and (ii) a second surface (13b) that reflects the light, having entered the first prism, toward the light emission side, the optical film further including, between the plurality of first prisms in an in-plane direction of the optical film, a second prism (14) that reflects light.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: April 12, 2016
    Assignees: Sharp Kabushiki Kaisha, Tohoku University
    Inventors: Tatsuo Uchida, Yoshito Suzuki, Tohru Kawakami, Kazuo Sekiya, Masahiro Nishizawa, Takahiro Ishinabe, Katsunori Ehara, Yoshihiro Hashimoto, Yasuhisa Itoh, Yoshitaka Yamamoto, Yutaka Ishii
  • Patent number: 9312349
    Abstract: To provide a semiconductor device in which the threshold value is controlled. Furthermore, to provide a semiconductor device in which a deterioration in electrical characteristics which becomes more noticeable as a transistor is miniaturized can be suppressed. The semiconductor device includes a first semiconductor film, a source electrode and a drain electrode electrically connected to the first semiconductor film, a gate insulating film, and a gate electrode in contact with the gate insulating film. The gate insulating film includes a first insulating film and a trap film, and charge is trapped in a charge trap state in an interface between the first insulating film and the trap film or inside the trap film.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: April 12, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuhiro Tanaka, Takayuki Inoue, Yoshitaka Yamamoto, Hideomi Suzawa, Tamae Moriwaka
  • Publication number: 20160071840
    Abstract: A semiconductor device that includes transistors with different threshold voltages is provided. Alternatively, a semiconductor device including a plurality of kinds of circuits and transistors whose electrical characteristics are different between the circuits is provided. The semiconductor device includes a first transistor and a second transistor. The first transistor includes an oxide semiconductor, a conductor, a first insulator, a second insulator, and a third insulator. The conductor has a region where the conductor and the oxide semiconductor overlap with each other. The first insulator is positioned between the conductor and the oxide semiconductor. The second insulator is positioned between the conductor and the first insulator. The third insulator is positioned between the conductor and the second insulator. The second insulator has a negatively charged region.
    Type: Application
    Filed: September 1, 2015
    Publication date: March 10, 2016
    Inventors: Yoshitaka YAMAMOTO, Masayuki SAKAKURA, Tetsuhiro TANAKA, Daisuke MATSUBAYASHI
  • Patent number: 9269822
    Abstract: A method for manufacturing a semiconductor device with adjusted threshold is provided. In a semiconductor device including a semiconductor, a source or drain electrode electrically connected to the semiconductor, a first gate electrode and a second gate electrode between which the semiconductor is provided, a charge trap layer provided between the first gate electrode and the semiconductor, and a gate insulating layer provided between the second gate electrode and the semiconductor, a threshold is increased by trapping electrons in the charge trap layer by keeping a potential of the first gate electrode at a potential higher than a potential of the source or drain electrode for 1 second or more while heating. After the threshold adjustment process, the first gate electrode is removed or insulated from other circuits. Alternatively, a resistor may be provided between the first gate electrode and other circuits.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: February 23, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshitaka Yamamoto, Tetsuhiro Tanaka, Takayuki Inoue, Hideomi Suzawa, Yasuhiko Takemura
  • Patent number: 9263705
    Abstract: A successive deposition apparatus by which a reduction in the luminous efficiency of a light-emitting element can be suppressed even in high-speed deposition of a light-emitting layer thereof is provided. The apparatus includes: a second deposition chamber; a third deposition chamber coupled to the second deposition chamber; a transfer unit for transferring a substrate from second deposition chamber to third deposition chamber; plural third deposition sources arranged in the substrate transfer direction in the second deposition chamber; and a fourth and fifth deposition sources alternately arranged in the transfer direction in the third deposition chamber. In the third deposition chamber, the fourth deposition source is placed nearest to the second deposition source. The fourth deposition source contains a host material, and the fifth deposition source contains a dopant material. The HOMO level of a material of the third deposition source is adjusted to that of the host material.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: February 16, 2016
    Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Satoshi Seo, Hisao Ikeda, Manabu Niboshi, Katsunori Mitsuhashi, Seiichi Mitsui, Yoshitaka Yamamoto
  • Publication number: 20160043110
    Abstract: A highly reliable semiconductor device that is suitable for high-speed operation is provided. A semiconductor device includes a first circuit, a second circuit, and a third circuit. The first circuit has an arithmetic processing function. The second circuit includes a memory circuit. The memory circuit includes a transistor which includes a first conductor, a second conductor, a first insulator, a second insulator, and a semiconductor. The first conductor includes a region overlapping the semiconductor with the first insulator positioned between the first conductor and the semiconductor. The second conductor includes a region overlapping the semiconductor with the second insulator positioned between the second conductor and the semiconductor. The first conductor is capable of selecting on or off of the transistor. The third circuit is electrically connected to the second conductor, and is capable of changing the potential of the second conductor in synchronization with an operation of the transistor.
    Type: Application
    Filed: August 4, 2015
    Publication date: February 11, 2016
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tomoaki Atsumi, Masayuki SAKAKURA, Yoshitaka YAMAMOTO, Jun KOYAMA, Tetsuhiro TANAKA, Kazuki TANEMURA
  • Patent number: 9236507
    Abstract: The photoelectric conversion element includes a semiconductor substrate, a first amorphous film of a first conductivity type disposed on an entire surface of one surface of the semiconductor substrate, a first conductive oxide layer disposed on the first amorphous film, a second amorphous film of the first conductivity type disposed on a part of the other surface of the semiconductor substrate, a second conductive oxide layer disposed on the second amorphous film, a third amorphous film of a second conductivity type disposed on the other part of the other surface of the semiconductor substrate, and a third conductive oxide layer disposed on the third amorphous film. Electric conductivity of the first conductive oxide layer is lower than electric conductivities of the second and the third conductive oxide layer. Transmittance of the first conductive oxide layer is higher than transmittances of the second and the third conductive oxide layer.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: January 12, 2016
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Toshihiko Sakai, Kenji Kimoto, Naoki Koide, Yoshitaka Yamamoto
  • Patent number: 9217552
    Abstract: A lighting device (100) includes: a surface light source (1); a first lens (L1) having a first focal point (F1), the first lens being provided on the light exit surface side of the surface light source; and a second lens (L2) having a second focal point (F2), the second lens being provided on a light exit surface side of the first lens, the surface light source, the first lens, and the second lens being configured such that a first virtual image (I1) is formed by the first lens and a second virtual image (I2) is formed by the second lens, wherein the first virtual image (I1) is formed between the second focal point (F2) and the first lens, the second focal point (F2) is on a side opposite to the light source side relative to a predetermined focal position f?, and at least either of a light entry surface or a light exit surface of the first lens or the second lens includes a non-revolution surface (SO) as a lens surface, and a plurality of boundary lines (B1-B4) whose curvatures vary discontinuously are provid
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: December 22, 2015
    Assignees: Sharp Kabushiki Kaisha, Tohoku University
    Inventors: Tatsuo Uchida, Yoshito Suzuki, Tohru Kawakami, Takahiro Ishinabe, Katsunori Ehara, Yoshihiro Hashimoto, Toshiki Matsuoka, Kozo Nakamura, Yasuhisa Itoh, Yoshitaka Yamamoto, Yutaka Ishii
  • Patent number: 9196743
    Abstract: Provided is a semiconductor device in which generation of a parasitic channel in an end region of an oxide semiconductor film is suppressed. The semiconductor device includes a gate electrode, an oxide semiconductor film, a source electrode and a drain electrode, and a channel region formed in the oxide semiconductor film. The channel region is formed between a first side surface of the source electrode and a second side surface of the drain electrode opposite to the first side surface. The oxide semiconductor film has an end region which does not overlap with the gate electrode. The end region which does not overlap with the gate electrode is positioned between a first region that is the nearest to one end of the first side surface and a second region that is the nearest to one end of the second side surface.
    Type: Grant
    Filed: April 11, 2013
    Date of Patent: November 24, 2015
    Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Masatoshi Yokoyama, Tsutomu Murakawa, Kenichi Okazaki, Masayuki Sakakura, Takuya Matsuo, Akihiro Oda, Shigeyasu Mori, Yoshitaka Yamamoto