Patents by Inventor Yoshiyuki Yoneda
Yoshiyuki Yoneda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20020000645Abstract: A semiconductor module includes a plurality of semiconductor devices each including a circuit substrate carrying thereon a single memory semiconductor chip and a socket for holding the semiconductor devices detachably.Type: ApplicationFiled: May 26, 1998Publication date: January 3, 2002Inventors: MITSUTAKA SATO, TETSUYA FUJISAWA, SHIGEYUKI MARUYAMA, JUNICHI KASAI, TOSHIMI KAWAHARA, TOSHIO HAMANO, YOSHIHIRO KUBOTA, MITSUNADA OSAWA, YOSHIYUKI YONEDA, KAZUTO TSUJI, HIROHISA MATSUKI
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Patent number: 6329711Abstract: A semiconductor device includes a semiconductor element, a resin package sealing the semiconductor element, resin projections protruding from a mounting surface of the resin package, metallic film parts provided to the resin projections, connecting members electrically connecting electrode pads on the semiconductor element and the metallic film parts, and connection pads extending from the metallic film parts, the connecting members being connected to the connection pads.Type: GrantFiled: November 30, 1998Date of Patent: December 11, 2001Assignee: Fujitsu LimitedInventors: Toshimi Kawahara, Mamoru Suwa, Masanori Onodera, Syuichi Monma, Shinya Nakaseko, Takashi Hozumi, Yoshiyuki Yoneda, Ryuji Nomoto
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Patent number: 6271583Abstract: A semiconductor device includes a substrate having a first surface, a second surface and at least one conductor part which are exposed at both the first and second surfaces of the substrate, a semiconductor chip provided on the first surface of the substrate and having a plurality of electrode pads, a plurality of leads, a plurality of bonding-wires electrically connecting the leads and the conductor parts to corresponding ones of the electrode pads of the semiconductor chip, and a resin package encapsulating the semiconductor chip, a part of the leads, and the substrate so that the conductor parts are exposed at the second surface of the substrate.Type: GrantFiled: June 16, 1998Date of Patent: August 7, 2001Assignee: Fujitsu LimitedInventors: Hideharu Sakoda, Yoshiyuki Yoneda, Kazuto Tsuji
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Patent number: 6255740Abstract: This invention relates to a semiconductor device in which a plurality of outer terminals are arranged in a lattice formation on a flat surface. The semiconductor device has a semiconductor chip, a lead member having a lead portion and an outer connecting terminal connected integrally to the lead portion, the lead portion electrically connected to the semiconductor chip, the lead portion extending outwardly from the semiconductor chip, the outer connecting terminal extending downwardly from the lead portion, a sealing resin sealing the semiconductor chip and the lead portion, a bottom face of the semiconductor chip and a bottom face of the lead portion being exposed from the sealing resin, and an insulating member covering the bottom face of the semiconductor chip and the bottom face of the lead portion.Type: GrantFiled: May 1, 1997Date of Patent: July 3, 2001Assignee: Fujitsu LimitedInventors: Kazuto Tsuji, Yoshiyuki Yoneda, Hideharu Sakoda, Ryuji Nomoto, Eiji Watanabe, Seiichi Orimo, Masanori Onodera, Masaki Waki
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Publication number: 20010001714Abstract: A method of fabricating a semiconductor device includes a step of attaching a circuit substrate on a semiconductor wafer in alignment with each other, providing an electrical interconnection between the circuit substrate and semiconductor devices formed in the wafer, providing solder bumps on the circuit substrate, and dicing the semiconductor wafer together with the circuit substrate thereon along a scribe line.Type: ApplicationFiled: January 24, 2001Publication date: May 24, 2001Applicant: FUJITSU LIMITEDInventors: Toshiyuki Motooka, Yoshiyuki Yoneda, Ryuji Nomoto, Toshimi Kawahara, Junichi Kasai
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Patent number: 6207477Abstract: A method of fabricating a semiconductor device includes a step of attaching a circuit substrate on a semiconductor wafer in alignment with each other, providing an electrical interconnection between the circuit substrate and semiconductor devices formed in the wafer, providing solder bumps on the circuit substrate, and dicing the semiconductor wafer together with the circuit substrate thereon along a scribe line.Type: GrantFiled: February 11, 1998Date of Patent: March 27, 2001Assignee: Fujitsu LimitedInventors: Toshiyuki Motooka, Yoshiyuki Yoneda, Ryuji Nomoto, Toshimi Kawahara, Junichi Kasai
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Patent number: 6159770Abstract: There is provided a method for fabricating semiconductor devices including resin packages sealing semiconductor elements and external connection terminals respectively resin projections formed on the resin packages and metallic film parts provided to the resin projections. The semiconductor elements are mounted to a lead frame having recess portions located in positions corresponding to positions of the resin projections, metallic film parts being provided in the recess portions. The semiconductor elements are electrically connected to the metallic film parts. The resin packages that seal the semiconductor elements and gate portions are integrally formed with the resin packages. The lead frame is etched so that the resin packages are separated from the lead frame together with the metallic layer parts. The resin packages are attached to an adhesive tape provided to a frame and being used as a carrier.Type: GrantFiled: November 16, 1998Date of Patent: December 12, 2000Assignee: Fujitsu LimitedInventors: Masafumi Tetaka, Shinichiro Maki, Nobuo Ohyama, Seiichi Orimo, Hideharu Sakoda, Yoshiyuki Yoneda, Akihiro Shigeno, Ryoichi Yokoyama, Fumitoshi Fujisaki, Masao Fukunaga, Kazuto Tsuji, Terumi Kamifukumoto, Kenji Itasaka, Masanori Onodera
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Patent number: 6072239Abstract: A device includes a chip, and a resin package sealing the chip, the resin package having resin projections located on a mount-side surface of the resin package. Metallic films are respectively provided to the resin projections. Connecting parts electrically connect electrode pads of the chip and the metallic films.Type: GrantFiled: November 6, 1996Date of Patent: June 6, 2000Assignee: Fujitsu LimitedInventors: Yoshiyuki Yoneda, Kazuto Tsuji, Seiichi Orimo, Hideharu Sakoda, Ryuji Nomoto, Masanori Onodera, Junichi Kasai
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Patent number: 6069408Abstract: A method of manufacturing a semiconductor device includes the steps of: mounting a semiconductor chip on a holding board having electrode accommodation recesses formed thereon, and mounting electrode members to the electrode accommodation recesses, the electrode members being formed separately from the semiconductor element; electrically connecting electrode pads formed on the semiconductor chip with the electrode members; forming a resin package for sealing the semiconductor chip on the holding board by using a die, the holding board serving as a part of the die; and separating the resin package including the electrode members from the holding board.Type: GrantFiled: January 14, 1999Date of Patent: May 30, 2000Assignee: Fujitsu LimitedInventors: Toshiyuki Honda, Akihiro Oku, Takanori Watanabe, Kazuto Tsuji, Yoshiyuki Yoneda
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Patent number: 6025650Abstract: This invention relates to a semiconductor device in which a plurality of outer terminals are arranged in a lattice formation on a flat surface. The semiconductor device comprises a semiconductor chip having a plurality of pads, a resin portion sealing said semiconductor chip and a terminal portion in which a prescribed number of pole terminals electrically connected to said pads provided in said semiconductor chip are provided, said pole terminals being exposed from said resin portion. According to the invention, a cost for production is reduced and a reliability and electrical characteristics can be improved.Type: GrantFiled: October 30, 1997Date of Patent: February 15, 2000Assignee: Fujitsu LimitedInventors: Kazuto Tsuji, Yoshiyuki Yoneda, Hideharu Sakoda, Ryuuji Nomoto, Eiji Watanabe, Seiichi Orimo, Masanori Onodera, Junichi Kasai
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Patent number: 5930603Abstract: A method for producing a semiconductor device includes steps of: a) a positioning board forming process in which concave portions, each of which is located at a position corresponding to a position of a respective projecting electrode of a semiconductor device, and first positioning portions, which are used for determining a position of a sealing resin with respect to the projecting electrode, are integrally formed on a flat-plate member so as to form a positioning board; b) a filling process in which an electrode material for forming the projecting electrode is filled in the concave portions formed on the positioning board; c) a bonding process in which a composite board is formed by mounting a circuit board on the positioning board so as to bond each of the electrode material filled in the concave portions to the circuit board; d) a sealing resin forming process in which a mold having a cavity for forming a sealing resin and second positioning portions for determining a position of the positioning board witType: GrantFiled: May 27, 1997Date of Patent: July 27, 1999Assignee: Fujitsu LimitedInventors: Kazuto Tsuji, Yoshiyuki Yoneda, Seiichi Orimo, Ryuji Nomoto, Masanori Onodera, Hideharu Sakoda
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Patent number: 5904506Abstract: A semiconductor device includes a rigid member embedded in a resin package body for supporting thereon outer leads that extend from the resin package body and test pads provided on the outer leads for testing the semiconductor device.Type: GrantFiled: April 10, 1998Date of Patent: May 18, 1999Assignee: Fujitsu LimitedInventors: Yoshiyuki Yoneda, Kazuto Tsuji
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Patent number: 5891758Abstract: A method of manufacturing a semiconductor device includes the steps of: mounting a semiconductor chip on a holding board having electrode accommodation recesses formed thereon, and mounting electrode members to the electrode accommodation recesses, the electrode members being formed separately from the semiconductor element; electrically connecting electrode pads formed on the semiconductor chip with the electrode members; forming a resin package for sealing the semiconductor chip on the holding board by using a die, the holding board serving as a part of the die; and separating the resin package including the electrode members from the holding board.Type: GrantFiled: October 31, 1997Date of Patent: April 6, 1999Assignee: Fujitsu Limited, Ltd.Inventors: Toshiyuki Honda, Akihiro Oku, Takanori Watanabe, Kazuto Tsuji, Yoshiyuki Yoneda
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Patent number: 5808357Abstract: A semiconductor device includes a substrate having a first surface, a second surface and at least one conductor parts which are exposed at both the first and second surfaces of the substrate, a semiconductor chip provided on the first surface of the substrate and having a plurality of electrode pads, a plurality of leads, a plurality of bonding-wires electrically connecting the leads and the conductor parts to corresponding ones of the electrode ads of the semiconductor chip, and a resin package encapsulating the semiconductor chip, part of the leads, and the substrate so that the conductor parts are exposed at the second surface of the substrate.Type: GrantFiled: June 7, 1995Date of Patent: September 15, 1998Assignee: Fujitsu LimitedInventors: Hideharu Sakoda, Yoshiyuki Yoneda, Kazuto Tsuji
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Patent number: 5804468Abstract: A process for manufacturing semiconductor device having a package in which a semiconductor device is sealed includes a base, and a metallic film is formed on a surface of the base. The semiconductor chip is formed on the metallic film. A pad formed on the semiconductor chip is connected to the metallic film by a wire. A sealing layer is formed on the metallic film. Leads are formed on the glass layer. A connecting layer is formed on the metallic film and contains electrically conductive particles. The connecting layer is in contact with a lead for a power supply system and connecting the metallic film to the lead.Type: GrantFiled: November 21, 1995Date of Patent: September 8, 1998Assignees: Fujitsu Limited, Kyushu Fujitsu Electronics LimitedInventors: Kazuto Tsuji, Yoshiyuki Yoneda, Hideharu Sakoda, Michio Sono, Ichiro Yamaguchi, Toshio Hamano, Yoshihiro Kubota, Michio Hayakawa, Yoshihiko Ikemoto, Yukio Saigo, Naomi Miyaji
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Patent number: 5767527Abstract: A semiconductor device includes a rigid member embedded in a resin package body for supporting thereon outer leads that extend from the resin package body and test pads provided on the outer leads for testing the semiconductor device.Type: GrantFiled: July 5, 1995Date of Patent: June 16, 1998Assignee: Fujitsu LimitedInventors: Yoshiyuki Yoneda, Kazuto Tsuji
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Patent number: 5750421Abstract: A semiconductor device including a plurality of leads respectively made up of an inner lead and an outer lead, a semiconductor chip electrically connected to the inner leads, and a package encapsulating at least the inner leads of the leads and the semiconductor chip so that the outer leads extend outwardly of the package. The package has an upper part and a lower part which have mutually different sizes such that a stepped part is formed between the upper and lower parts by the different sizes, and each of the outer leads have a wide part which is wider than other parts of the outer lead extending outwardly of the package only within the stepped part of the package.Type: GrantFiled: January 27, 1997Date of Patent: May 12, 1998Assignees: Fujitsu Limited, Kyushu Fujitsu Electronics Limited, Fujitsu Automation LimitedInventors: Junichi Kasai, Kazuto Tsuji, Norio Taniguchi, Takashi Mashiko, Masao Sakuma, Yukio Saigo, Yoshiyuki Yoneda, Masashi Takenaka
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Patent number: 5736428Abstract: A process for manufacturing semiconductor device including a plurality of leads respectively made up of an inner lead and an outer lead, a semiconductor chip electrically connected to the inner leads, and a package encapsulating at least the inner leads of the leads and the semiconductor chip so that the outer leads extend outwardly of the package. The package has an upper part and a lower part which have mutually different sizes such that a stepped part is formed between the upper and lower parts by the different sizes, and each of the outer leads have a wide part which is wider than other parts of the outer lead extending outwardly of the package only within the stepped part of the package.Type: GrantFiled: January 27, 1997Date of Patent: April 7, 1998Assignees: Fujitsu Limited, Kyushu Fujitsu Electronics Limited, Fujitsu Automation LimitedInventors: Junichi Kasai, Kazuto Tsuji, Norio Taniguchi, Takashi Mashiko, Masao Sakuma, Yukio Saigo, Yoshiyuki Yoneda, Masashi Takenaka
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Patent number: 5666064Abstract: A semiconductor device comprises a plurality of leads respectively made up of an inner lead and an outer lead, a semiconductor chip electrically connected to the inner leads of the leads, and a package encapsulating at least the inner leads of the leads and the semiconductor chip so that the outer leads extend outwardly of the package. The package has an upper part and a lower part which have mutually different sizes such that a stepped part is formed between the upper and lower parts by the different sizes, and each of the outer leads have a wide part which is wider than other parts of the outer lead extending outwardly of the package only within the stepped part of the package.Type: GrantFiled: May 15, 1995Date of Patent: September 9, 1997Assignees: Fujitsu Limited, Kyushu Fujitsu Elecronics Limited, Fujitsu Automation LimitedInventors: Junichi Kasai, Kazuto Tsuji, Norio Taniguchi, Takashi Mashiko, Masao Sakuma, Yukio Saigo, Yoshiyuki Yoneda, Masashi Takenaka
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Patent number: 5656550Abstract: This invention relates to a semiconductor device in which a plurality of outer terminals are arranged in a lattice formation on a flat surface. The semiconductor device has a semiconductor chip, a lead member having a lead portion and an outer connecting terminal connected integrally to the lead portion, the lead portion electrically connected to the semiconductor chip, the lead portion extending outwardly from the semiconductor chip, the outer connecting terminal extending downwardly from the lead portion, a sealing resin sealing the semiconductor chip and the lead portion, a bottom face of the semiconductor chip and a bottom face of the lead portion being exposed from the sealing resin, and an insulating member covering the bottom face of the semiconductor chip and the bottom face of the lead portion.Type: GrantFiled: March 5, 1996Date of Patent: August 12, 1997Assignee: Fujitsu LimitedInventors: Kazuto Tsuji, Yoshiyuki Yoneda, Hideharu Sakoda, Ryuji Nomoto, Eiji Watanabe, Seiichi Orimo, Masanori Onodera, Masaki Waki