Abstract: Embodiments of the disclosure provide a circuit structure and method to control electrostatic discharge (ESD) events in a resistor-capacitor (RC) circuit. Circuit structures according to the disclosure may include a trigger transistor coupled in parallel with the RC circuit, and a gate terminal coupled to part of the RC circuit. A mirror transistor coupled in parallel with the RC circuit transmits a current that is less than a current through the trigger transistor. A snapback device has a gate terminal coupled to a source or drain of the mirror transistor, and a pair of anode/cathode terminals coupled in parallel with the RC circuit. A current at the gate terminal of the snapback device, derived from current in the mirror transistor, controls an anode/cathode current flow in the snapback device.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to diode triggered Silicon controlled rectifiers and methods of manufacture. The structure includes a diode string comprising a first type of diodes and a second type of diode in bulk technology in series with the diode string of the first type of diodes.

Abstract: Embodiments of the disclosure provide a circuit structure and method to control electrostatic discharge (ESD) events in a resistor-capacitor (RC) circuit. Circuit structures according to the disclosure may include a trigger transistor coupled in parallel with the RC circuit, and a gate terminal coupled to part of the RC circuit. A mirror transistor coupled in parallel with the RC circuit transmits a current that is less than a current through the trigger transistor. A snapback device has a gate terminal coupled to a source or drain of the mirror transistor, and a pair of anode/cathode terminals coupled in parallel with the RC circuit. A current at the gate terminal of the snapback device, derived from current in the mirror transistor, controls an anode/cathode current flow in the snapback device.

Abstract: A grant-free resource configuration method and an apparatus are provided. The method includes: listening to, by a terminal device, a physical downlink control channel on a paging occasion by using a grant-free resource configuration identifier; and obtaining, by the terminal device on the physical downlink control channel or a physical downlink shared channel indicated by the physical downlink control channel, grant-free resource configuration information sent by a network device. In this grant-free resource configuration solution, the terminal device listens to a physical downlink control channel on a same paging occasion by using different identifiers, and obtains grant-free resource configuration information. A configuration occasion is preset, to ensure that the grant-free resource configuration information can be effectively received by the terminal device. In addition, the grant-free resource configuration identifier is used, to facilitate grant-free resource configuration for the terminal device.

Abstract: A composition of matter may include pores and non-tri-zone particles and tri-zone particles. In one implementation, each tri-zone particle may include carbon fragments intertwined with each other and separated from one another by mesopores. Each tri-zone particle may also include a deformable perimeter that may coalesce with adjacent non-tri-zone particles or tri-zone particles. In some aspects, the tri-zone particles may include aggregates formed by a multitude of the tri-zone particles joined together. In some aspects, mesopores may be interspersed throughout the aggregates. Each tri-zone particle may also include agglomerates, where each agglomerate includes a multitude of the aggregates joined together. In some aspects, macropores may be interspersed throughout the aggregates.

Abstract: A low power hybrid reverse (LPHR) bandgap reference (BGR) and digital temperature sensor (DTS) or a digital thermometer, which utilizes subthreshold metal oxide semiconductor (MOS) transistor and the PNP parasitic Bi-polar Junction Transistor (BJT) device to form a reverse BGR that serves as the base for configurable BGR or DTS operating modes. The LPHR architecture uses low-cost MOS transistors and the standard parasitic PNP device. Based on a reverse bandgap voltage, the LPHR can work as a configurable BGR. By comparing the configurable BGR with the scaled base-emitter voltage, the circuit can also perform as a DTS with a linear transfer function with single-temperature trim for high accuracy.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an electrostatic discharge (ESD) device and methods of manufacture. The structure (ESD device) includes: a trigger collector region having fin structures of a first dopant type, a collector region having fin structures in a well of a second dopant type and further including a lateral ballasting resistance; an emitter region having a well of the second dopant type and fin structures of the first dopant type; and a base region having a well and fin structures of the second dopant type.

Abstract: The measurement method includes operations of applying a first gate bias voltage to a gate terminal of a first transistor that is included in a radio frequency (RF) power amplifier during a direct current (DC) measurement period, wherein the first transistor operates in a linear operation mode during the DC measurement period; measuring a first drain-source voltage of the first transistor and a current flowing through the first transistor via a connection node during the DC measurement period; applying a second gate bias voltage and a drain bias voltage to a gate terminal and a drain terminal of a second transistor that is electrically connected to the first transistor via the connection node; and measuring a DC value of the second transistor via the connection node during the DC measurement period.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an electrostatic discharge (ESD) device and methods of manufacture. The structure (ESD device) includes: a trigger collector region having fin structures of a first dopant type, a collector region having fin structures in a well of a second dopant type and further including a lateral ballasting resistance; an emitter region having a well of the second dopant type and fin structures of the first dopant type; and a base region having a well and fin structures of the second dopant type.

Abstract: Provided herein is a rechargeable power source that can be quickly charged and used for charging mobile and cordless devices. The power source includes an ultracapacitor which comprises a composite structure including, for example open graphene structures or graphene nanoribbons attached to an oxide layer. The oxide layer is on a metal foil surface. The oxide layer includes more than one metal atom.

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure, including a doped well in a semiconductor substrate, in addition to a base region, emitter region, and collector region in the doped well. An insulative material is within the doped well, with a first end horizontally adjacent the collector region and a second end opposite the first end. A doped semiconductor region is within the doped well adjacent the second end of the insulative material. The doped semiconductor region is positioned to define an avalanche junction between the collector region and the doped semiconductor region across the doped well.

Abstract: A circuit structure includes: a network of clamps; sense elements in series with the clamps and configured to sense a turn-on of at least one clamp of the network of clamps; and feedback elements connected to the clamps to facilitate triggering of remaining clamps of the network of clamps.

Abstract: A circuit structure includes: a network of clamps; sense elements in series with the clamps and configured to sense a turn-on of at least one clamp of the network of clamps; and feedback elements connected to the clamps to facilitate triggering of remaining clamps of the network of clamps.

Abstract: Provided is a method for synthesizing a perovskite quantum dot film, including: preparing a cellulose nanocrystal (CNC) solution, wherein the CNC solution includes a plurality of CNCs with sulfate groups; preparing a precursor solution; mixing the CNC solution and the precursor solution to form a mixed solution; and filtering and drying the mixed solution to form a perovskite quantum dot film.

Abstract: A composition of matter may include pores and non-tri-zone particles and tri-zone particles. In one implementation, each tri-zone particle may include carbon fragments intertwined with each other and separated from one another by mesopores. Each tri-zone particle may also include a deformable perimeter that may coalesce with adjacent non-tri-zone particles or tri-zone particles. In some aspects, the tri-zone particles may include aggregates formed by a multitude of the tri-zone particles joined together. In some aspects, mesopores may be interspersed throughout the aggregates. Each tri-zone particle may also include agglomerates, where each agglomerate includes a multitude of the aggregates joined together. In some aspects, macropores may be interspersed throughout the aggregates.

Abstract: A battery is disclosed that includes an anode, a graded interface layer disposed on the anode, a cathode positioned opposite to the anode, an electrolyte, and a separator. The anode may output lithium ions during cycling of the battery. A graded interface layer may be disposed on the anode and include a tin fluoride layer. A tin-lithium alloy region may form between the tin fluoride layer and the anode. The tin-lithium alloy region may produce a lithium fluoride uniformly dispersed between the anode and the tin fluoride layer during operational cycling of the battery. The electrolyte may disperse throughout the cathode and the anode. The separator may be positioned between the anode and cathode. In some aspects, the battery may also include lithium electrodeposited on one or more exposed surfaces of the anode.

Abstract: A composition of matter suitable for incorporation into a battery electrode is disclosed. In some implementations, the composition of matter may include pores that may be defined in size or shape by several carbonaceous particles. Each of the particles may have multiple regions such that adjacent regions are separated from each other by some of the pores. Deformable regions may be distributed throughout a perimeter of each of the particles, for example, to accommodate coalescence of multiple adjacent particles. The composition of matter may also include a plurality of aggregates and a plurality of agglomerates, where each aggregate includes a multitude of the particles joined together, and each agglomerate includes a multitude of the aggregates joined together.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to bi-directional silicon controlled rectifiers (SCRs) and methods of manufacture. The structure includes: a plurality of diffusion regions; a plurality of p-type (P+) wells adjacent to the diffusion regions, wherein the P+ wells are directly connected; and a plurality of n-type (N+) wells adjacent to the P+ wells.

Abstract: The invention provides an antenna structure comprising a plurality of wire segments formed in a loop. Connecting units are provided between the wire segments, each of which is switchable between a conductive state and a reactive state. With the connecting units in the conductive state a loop antenna is formed with a first (longer) signal range and with the connecting units in the reactive state an antenna structure is formed with a second (shorter) signal range. Said reactive state is adapted to introduce a phase delay between the adjacent wire segments. This enables the same antenna to be used for long range signal communication and short range communication, for example for system configuration or commissioning. The antenna structure may be used with luminaires of a lighting system.