Abstract: A graphic processing unit (GPU) with a configurable filtering module (CFU) and an operation method thereof are presented. The graphic processing unit comprises a memory module and a configurable filtering module. The memory module stores at least one texture image. The configurable filtering module, connected to the memory module, comprises a plurality of filter equations, from which a filter equation is selected. A plurality of pixel points are sampled from the texture image. Each sampled pixel point is set with a weight value respectively. Each sampled pixel point with a weight value corresponding thereto is substituted into the selected filter equation to perform an operational process to acquire an operated value. Thereby, the user can decide the operation method of the GPU by selecting an appropriate filter equation and setting adjustable parameters in the filter equation.

Abstract: A method for fabricating a inductor carrier comprises the steps of providing a substrate with a protective layer; forming a first photoresist layer on protective layer; patterning the first photoresist layer to form a first opening and first apertures; forming a first metal layer within first opening and first apertures; removing the first photoresist layer; forming a first dielectric layer on protective layer; forming a second photoresist layer on first dielectric layer; patterning the second photoresist layer to form a second aperture and a plurality of third apertures; forming a second metal layer within second aperture and third apertures; removing the second photoresist layer; forming a second dielectric layer on first dielectric layer; forming a third photoresist layer on second dielectric layer; patterning the third photoresist layer to form a fifth aperture and sixth apertures; forming a third metal layer within fifth aperture and sixth apertures.

Abstract: A method for performing dynamic configuration includes: freezing a bus between a dynamic configurable cache and a plurality of cores/processors by rejecting a request from any of the cores/processors during a bus freeze period, wherein the dynamic configurable cache is implemented with an on-chip memory; and adjusting a size of a portion of the dynamic configurable cache, wherein the portion of the dynamic configurable cache is capable of caching/storing information for one of the cores/processors. An associated apparatus is also provided. In particular, the apparatus includes the plurality of cores/processors, the dynamic configurable cache, and a dynamic configurable cache controller, and can operate according to the method.

Abstract: A method for fabricating a inductor carrier comprises the steps of providing a substrate with a protective layer; forming a first photoresist layer on protective layer; patterning the first photoresist layer to form a first opening and first apertures; forming a first metal layer within first opening and first apertures; removing the first photoresist layer; forming a first dielectric layer on protective layer; forming a second photoresist layer on first dielectric layer; patterning the second photoresist layer to form a second aperture and a plurality of third apertures; forming a second metal layer within second aperture and third apertures; removing the second photoresist layer; forming a second dielectric layer on first dielectric layer; forming a third photoresist layer on second dielectric layer; patterning the third photoresist layer to form a fifth aperture and sixth apertures; forming a third metal layer within fifth aperture and sixth apertures.

Abstract: A method for fabricating a inductor carrier comprises the steps of providing a substrate with a protective layer; forming a first photoresist layer on protective layer; patterning the first photoresist layer to form a first opening and first apertures; forming a first metal layer within first opening and first apertures; removing the first photoresist layer; forming a first dielectric layer on protective layer; forming a second photoresist layer on first dielectric layer; patterning the second photoresist layer to form a second aperture and a plurality of third apertures; forming a second metal layer within second aperture and third apertures; removing the second photoresist layer; forming a second dielectric layer on first dielectric layer; forming a third photoresist layer on second dielectric layer; patterning the third photoresist layer to form a fifth aperture and sixth apertures; forming a third metal layer within fifth aperture and sixth apertures.

Abstract: A lubricant applicator includes a base, a plurality of elastic members, and a plate member. The base includes a hollow space for receiving lubricant. The elastic support member is mounted within the hollow space of the base. The plate member is received in the hollow space and supported by the elastic support member. The plate member comprises a first slot and a plurality of through openings formed in an upper surface thereof. The first slot is shaped to accommodate a golden finger interface.

Abstract: A chip with tri-layer electrodes and micro-cavity arrays for control of bioparticles and a manufacturing method thereof are revealed. The chip captures and releases bioparticles into and from preset cavities by dielectrophoresis (DEP) force generated by electrodes. The chip includes an upper layer body, a middle layer body, a lower layer body, respectively disposed with an electrode, and micro flow chambers. The electrodes of the upper layer body and the middle layer body are common electrodes while the electrode of the lower layer body is a dispersive electrode array exposed on the bottom of lower-layer microcavity. The cell capture and release at the single-cell level and the cell population level are attained by application of an AC electric field.

Abstract: A method for fabricating a carrier with a three-dimensional inductor comprises the steps of providing a substrate having a protective layer; forming a first photoresist layer on the protective layer; patterning the first photoresist layer to form a second opening and a plurality of disposing slots; forming a first metal layer in second opening and disposing slots; removing the first photoresist layer; forming a first dielectric layer on the protective layer; forming a second photoresist layer on the first dielectric layer; patterning the second photoresist layer to form a plurality of slots; forming a second metal layer in slots to form a plurality of inductive portions; removing the second photoresist layer; forming a second dielectric layer on the first dielectric layer; forming a third photoresist layer on the second dielectric layer; patterning the third photoresist layer to form a plurality of slots; and forming a third metal layer in slots.

Abstract: A method for fabricating a carrier with a three-dimensional inductor comprises the steps of providing a substrate having a protective layer; forming a first photoresist layer on the protective layer; patterning the first photoresist layer to form a second opening and a plurality of disposing slots; forming a first metal layer in second opening and disposing slots; removing the first photoresist layer; forming a first dielectric layer on the protective layer; forming a second photoresist layer on the first dielectric layer; patterning the second photoresist layer to form a plurality of slots; forming a second metal layer in slots to form a plurality of inductive portions; removing the second photoresist layer; forming a second dielectric layer on the first dielectric layer; forming a third photoresist layer on the second dielectric layer; patterning the third photoresist layer to form a plurality of slots; and forming a third metal layer in slots.

Abstract: An LED lamp includes a lamp body, a pair of holders received in the lamp body, a circuit board with a number of LEDs, and a pair of connectors. The circuit board is received in the lamp body but spaced from insides of the lamp body. The opposite ends of the circuit board are fixed to the holders correspondingly. The connectors are fixed to the holders and abut against opposite ends of the lamp body.

Abstract: A stream processing system includes a stream processing module coupled to a memory module and operable so as to fetch stream elements from the memory module, to process the stream elements fetched thereby, and to store processed stream elements in the memory module. The stream processing module includes a number (N) of stream processing units, and the memory module is configured with a number (N) of memory bank units each corresponding to a respective one of the stream processing units. The memory module is reconfigurable based on a desired inter-level configuration so that each of the memory bank units is configured to have a memory size sufficient to meet processing requirement of the respective one of the stream processing units.

Abstract: A graphic processing unit (GPU) with a configurable filtering module (CFU) and an operation method thereof are presented. The graphic processing unit comprises a memory module and a configurable filtering module. The memory module stores at least one texture image. The configurable filtering module, connected to the memory module, comprises a plurality of filter equations, from which a filter equation is selected. A plurality of pixel points are sampled from the texture image. Each sampled pixel point is set with a weight value respectively. Each sampled pixel point with a weight value corresponding thereto is substituted into the selected filter equation to perform an operational process to acquire an operated value. Thereby, the user can decide the operation method of the GPU by selecting an appropriate filter equation and setting adjustable parameters in the filter equation.

Abstract: In a multi-core stream processing system and scheduling method of the same, a scheduler is coupled to a number (N) of stream processing units and a number (N+1) of stream fetching units, where N?2. When the scheduler receives a stream element from a Pth stream fetching unit, the scheduler assigns a Pth stream processing unit as a target stream processing unit when the Pth stream processing unit does not encounter a bottleneck condition, assigns a Qth stream processing unit, which does not encounter the bottleneck condition, as the target stream processing unit when the Pth stream processing unit encounters the bottleneck condition, where 1?P?N, 1?Q?N, and P?Q, and dispatches the received stream element to the target stream processing unit such that the target stream processing unit processes the stream element dispatched from the scheduler.

Abstract: A method for performing image signal processing (ISP) with the aid of a graphics processing unit (GPU) includes: utilizing an ISP pipeline to perform pre-processing on source data of at least one portion of at least one source frame image to generate intermediate data of at least one portion of at least one intermediate frame image, where the ISP pipeline stores the intermediate data into a memory; and utilizing the GPU to retrieve the intermediate data from the memory and perform specific processing on the intermediate data to generate processed data, where the GPU stores the processed data into the external/on-chip memory. In particular, at least one of the intermediate data and the processed data complies with a specific color format. In addition, an associated apparatus is further provided.

Abstract: The present invention discloses a backlight module and a display device comprising the backlight module. The backlight module includes a light source, a light guide plate and a frame, wherein the light guide plate has a light entrance end and a first side. An angle is included between the light entrance end and the first side, wherein a plurality of light diffusing structures are formed on the light entrance end. The light source is disposed at a position corresponding to the light entrance end and emits a light toward the light diffusing structures. The frame has a first wall facing an inner surface of the first side. A centre line perpendicular to the light entrance end is defined on the light guide plate, wherein the distance between the inner surface and the centre line increases in a direction toward the light source.

Abstract: A chip with tri-layer electrodes and micro-cavity arrays for control of bioparticles and a manufacturing method thereof are revealed. The chip captures and releases bioparticles into and from preset cavities by dielectrophoresis (DEP) force generated by electrodes. The chip includes an upper layer body, a middle layer body, a lower layer body, respectively disposed with an electrode, and micro flow chambers. The electrodes of the upper layer body and the middle layer body are common electrodes while the electrode of the lower layer body is a dispersive electrode array exposed on the bottom of lower-layer microcavity. The cell capture and release at the single-cell level and the cell population level are attained by application of an AC electric field.

Abstract: A method for repairing a display panel having a defect is provided, wherein a polarizer has been attached to a surface of the display panel, and the method includes following steps. First, a recess corresponding to the defect is formed at an outer surface of the polarizer. Afterward, a light-shielding material is filled into the recess. Besides, a display panel with a good display quality is also provided.

Abstract: A lubricant applicator includes a base, a plurality of elastic members, and a plate member. The base includes a hollow space for receiving lubricant. The elastic support member is mounted within the hollow space of the base. The plate member is received in the hollow space and supported by the elastic support member. The plate member comprises a first slot and a plurality of through openings formed in an upper surface thereof. The first slot is shaped to accommodate a golden finger interface.

Abstract: A stream processing system includes a stream processing module coupled to a memory module and operable so as to fetch stream elements from the memory module, to process the stream elements fetched thereby, and to store processed stream elements in the memory module. The stream processing module includes a number (N) of stream processing units, and the memory module is configured with a number (N) of memory bank units each corresponding to a respective one of the stream processing units. The memory module is reconfigurable based on a desired inter-level configuration so that each of the memory bank units is configured to have a memory size sufficient to meet processing requirement of the respective one of the stream processing units.

Abstract: In a stream processing method and system, each of a plurality of stream elements stored in a previous-stage module is configured with a specific index value. Each stream element includes a group of stream data. A stream fetching module fetches from the previous-stage module the stream elements in sequence such that the index values of the fetched stream elements correspond to a sequence of predetermined index values associated with a desired stream fetching pattern, and provides in sequence the stream elements fetched thereby to a post-stage module.