Abstract: In a multi-core stream processing system and scheduling method of the same, a scheduler is coupled to a number (N) of stream processing units and a number (N+1) of stream fetching units, where N?2. When the scheduler receives a stream element from a Pth stream fetching unit, the scheduler assigns a Pth stream processing unit as a target stream processing unit when the Pth stream processing unit does not encounter a bottleneck condition, assigns a Qth stream processing unit, which does not encounter the bottleneck condition, as the target stream processing unit when the Pth stream processing unit encounters the bottleneck condition, where 1?P?N, 1?Q?N, and P?Q, and dispatches the received stream element to the target stream processing unit such that the target stream processing unit processes the stream element dispatched from the scheduler.

Abstract: An efficient system and method for adaptive tile depth filter (ATDF) is disclosed. The key concept of this system and method is to consider more occlusion conditions in order to achieve a better performance of filter before the conventional Z test process in three dimensional graphics pipeline. Two occlusion criteria, Zmax and Zmin (depth range in a tile), are introduced first for occlusion and non-occlusion fragments in a tile. The points between Zmax and Zmin are in uncertain fragment which may need to go through the later Z test. Moreover, a new technique, coverage mask, can further filter the points in the uncertain fragment to a final uncertain fragment and non-occlusion fragment. Besides, the coverage mask can be used to efficiently decide which tile needs the further sub-tile depth filter.

Abstract: An integrated circuit comprises a test interface, an embedded in-circuit emulator, a circuit-under-debugging, and a memory. The embedded in-circuit emulator is used for software debugging via the test interface. The circuit-under-debugging comprises a scan chain dumping states of every delayed flip-flop (DFF) out of the circuit-under-debugging. The memory stores the states from the scan chain and transfers the states to a computer via the test interface.

Abstract: A notebook computer with a height-adjustable display unit is disclosed. The notebook computer includes a main unit, a display unit, and a height-adjusting mechanism. The height-adjusting mechanism includes a saw-toothed arm, a channel, and a locking mechanism. The saw-toothed arm is rotationally coupled to the main unit. The channel is fixed in the display unit and movably accepts the saw-toothed arm therein. The locking mechanism lock or unlock the movement of the saw-toothed arm in the channel. The height-adjusting mechanism affords adjustable support for the display unit. The height of the display unit can be adjusted as required.

Abstract: An efficient system and method for adaptive tile depth filter (ATDF) is disclosed. The key concept of this system and method is to consider more occlusion conditions in order to achieve a better performance of filter before the conventional Z test process in three dimensional graphics pipeline. Two occlusion criteria, Zmax and Zmin (depth range in a tile), are introduced first for occlusion and non-occlusion fragments in a tile. The points between Zmax and Zmin are in uncertain fragment which may need to go through the later Z test. Moreover, a new technique, coverage mask, can further filter the points in the uncertain fragment to a final uncertain fragment and non-occlusion fragment. Besides, the coverage mask can be used to efficiently decide which tile needs the further sub-tile depth filter.

Abstract: An integrated circuit comprises a test interface, an embedded in-circuit emulator, a circuit-under-debugging, and a memory. The embedded in-circuit emulator is used for software debugging via the test interface. The circuit-under-debugging comprises a scan chain dumping states of every delayed flip-flop (DFF) out of the circuit-under-debugging. The memory stores the states from the scan chain and transfers the states to a computer via the test interface.

Abstract: A system of early rejection after transformation in a Graphics Processing Unit is disclosed. The system includes following elements: (1) a vertex cache, for receiving vertex data of a triangle from system memory or video memory and storing the vertex data; (2) a vertex shader arithmetic logic unit, for operating the vertex data and related statuses of the vertex data; (3) a early rejection after transformation device, for determining if the triangle is valid or invalid via referring the related statuses of the vertex data of the triangle; (4) a lighting and texture stage program, for lighting and texturing the triangle determined valid to vertex information; (5) an index cache, for receiving index data from a driver to assemble the vertex data into primitives; and (6) a clip module, for performing a clipping operation on the valid triangle passed by the early rejection after transformation device.

Abstract: Graphics processing unit instruction sets using a reconfigurable cache are disclosed. The Graphics processing unit instruction sets includes following elements: (1) a vertex shader unit, for operating vertex data; (2) a reconfigurable cache memory, for accessing data with the vertex shader unit via a plurality of data buses; (3) a bank interleaving, for achieving byte alignment for the reconfigurable cache memory; (4) a software control data feedback, for reducing accessing frequency of registers of the reconfigurable cache memory; and (5) a software control data write back, for determining if the data need to be written back to the registers.

Abstract: A clock distribution apparatus for providing a local clock signal having a first voltage swing to a circuit unit being on a same substrate includes a global clock distribution network for generating and distributing a global clock signal having a second voltage swing being less than the first voltage swing; and a local clock converting unit being electrically connected between the global clock distribution network and the circuit unit. The local clock converting unit includes a level shifter for converting the global clock signal into the local clock signal.

Abstract: A notebook computer with a height-adjustable display unit is disclosed. The notebook computer includes a main unit, a display unit, and a height-adjusting mechanism. The height-adjusting mechanism includes a saw-toothed arm, a channel, and a locking mechanism. The saw-toothed arm is rotationally coupled to the main unit. The channel is fixed in the display unit and movably accepts the saw-toothed arm therein. The locking mechanism lock or unlock the movement of the saw-toothed arm in the channel. The height-adjusting mechanism affords adjustable support for the display unit. The height of the display unit can be adjusted as required.

Abstract: A substituted oligofluorene for organic light-emitting diode (OLED) and organic photoconductor (OPC) has a chemical structure of: wherein X and Y are an integer of 0 or 1, G1 and G2 are independently of either CnH2n+1 or CnH2n+1O; and n is an integer of 0 to 16.

Abstract: A clock distribution apparatus for providing a local clock signal having a first voltage swing to a circuit unit being on a same substrate includes a global clock distribution network for generating and distributing a global clock signal having a second voltage swing being less than the first voltage swing; and a local clock converting unit being electrically connected between the global clock distribution network and the circuit unit. The local clock converting unit includes a level shifter for converting the global clock signal into the local clock signal.

Abstract: A method for performing multi-clock static timing analysis to determine whether a timing violation occurs on a logic circuit. A set of clock signals that are expected to cause a logic circuit to be in a worst-case situation if analyzed by using static timing analysis can be selected from a number of possible clock signals by using a simple determination process. The selected set of clock signals are then employed in static timing analysis on the logic circuit to verify whether no timing violation occurs on each signal transmission path of the logic circuit. If not, it indicates that the logic circuit using any selection of the possible clock signals will not cause timing violation thereon. Thus, the static timing analysis can be accomplished efficiently.

Abstract: The design flow method of the present invention accurately performs timing analysis during the circuit design stage, so that the DFT synthesis procedure can effectively control the timing information, preventing timing violation from happening during the IC design flow process. Furthermore, the information of the CTS procedure and the static-timing analysis procedure is combined to perform accurate timing estimation.

Abstract: An implementing method for buffering devices is provided, so as to dispose the buffering devices on a chip. The chip includes a signal source root and the number X of output bonding pads, in which the number X is a positive integer. The implementing method of the present invention includes (a) implementing a buffering device for the Nth layer at a location close to the middle place between two output bonding pads, and electrically connecting each one of the output bonding pads to the corresponding one of the buffering devices for the Nth layer, respectively. (b) A buffering device for the N+1th layer is implemented at a location close to the middle place between two buffering devices for the Nth layer, and each one of the buffering devices for the Nth layer is electrically connected to the corresponding one of the buffering devices for the N+1th layer, respectively. Then, the number of the buffering devices for the N+1th layer is judged whether or not to be 1.

Abstract: A method for evaluating cross-talk of a circuit and signal degrading due to mutual electric coupling between wires of a circuit. The method includes: simulating the signal transmitting on wires of the circuit during the normal operation of the circuit, and implementing cross-talk analysis of the circuit to modify the analysis according to the signal variation during the practical operation of the circuit in order to evaluate the cross talk on each wire in the circuit.

Abstract: A method for recycling metals from swarf includes steps of removing oil in swarf by means of surfactant having a feature of strong hydrophilicity. The steps involves repeated stirring and washing, separating solid from liquid, and separating oil from water so as to force oil separate from the surface of solid, finishing all the steps in 10–30 minutes. Metals after finished the treatment may have only 1% of oil remained thereon, possible to be reused in metalworking. Oil and washing solution are also reusable after treated, so the method is effective both for treating waste and for recycling resources.

Abstract: A control chip having a multiple-layer defer queue therein and a method of operating the control chip. The control chip is coupled to a CPU bus and a PCI bus. The control chip comprises of a PC request queue, a multiple-layer defer queue, a PCI access queue and a PCI controller. The multiple-layer defer queue facilitates the processing of a multiple of concurrent CPU requests that belong to a first request type. The multiple-layer defer queue supports retry and defer transactions, thereby reducing data transmission between the CPU and the control chip.

Abstract: A method for recycling metals from swarf includes steps of removing oil in swarf by means of surfactant having a feature of strong hydrophilicity. The steps involves repeated stirring and washing, separating solid from liquid, and separating oil from water so as to force oil separate from the surface of solid, finishing all the steps in 10-30 minutes. Metals after finished the treatment may have only 1% of oil remained thereon, possible to be reused in metalworking. Oil and washing solution are also reusable after treated, so the method is effective both for treating waste and for recycling resources.

Abstract: An implementing method for buffering devices is provided, so as to dispose the buffering devices on a chip. The chip includes a signal source root and the number X of output bonding pads, in which the number X is a positive integer. The implementing method of the present invention includes (a) implementing a buffering device for the Nth layer at a location close to the middle place between two output bonding pads, and electrically connecting each one of the output bonding pads to the corresponding one of the buffering devices for the Nth layer, respectively. (b) A buffering device for the N+1th layer is implemented at a location close to the middle place between two buffering devices for the Nth layer, and each one of the buffering devices for the Nth layer is electrically connected to the corresponding one of the buffering devices for the N+1th layer, respectively. Then, the number of the buffering devices for the N+1th layer is judged whether or not to be 1.