Patents by Inventor Young-Gon Kim
Young-Gon Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7149095Abstract: A stacked microelectronic assembly includes a plurality of microelectronic subassemblies. Each subassembly includes a substrate having at least one site, a plurality of first contacts and a plurality of second contacts. Each subassembly also has at least one microelectronic element assembled to the at least one attachment site and electrically connected to at least some of the first and second contacts. The substrate is folded so that the first contacts are accessible at a bottom of a subassembly and the second contacts are accessible at a top of a subassembly. The plurality of subassemblies are stacked one on top of another in a generally vertical configuration. The substrate of at least one of the subassemblies has a plurality of attachment sites and a plurality of microelectronic elements assembled to the attachment sites. The substrate is folded so that at least some of the plurality of microelectronic elements are disposed alongside one another.Type: GrantFiled: October 28, 2002Date of Patent: December 12, 2006Assignee: Tessera, Inc.Inventors: Michael Warner, Philip Damberg, John B. Riley, David Gibson, Young-Gon Kim, Belgacem Haba, Vernon Solberg
-
Patent number: 7076124Abstract: An integrated circuit cast on a single die having a plurality of receivers in a receiver region, a plurality of transmitters in a transmitter region, and a spatial separation region having a plurality of n-type and p-type subregions disposed on the single die to separate the transmitter region from the receiver region. The pn-junctions between the n-type and p-type subregions are reverse-biased thereby reducing or eliminating coupling of noise and crosstalk between the transmitter and receiver is reduced.Type: GrantFiled: December 20, 2002Date of Patent: July 11, 2006Assignee: Avago Technologies, Ltd.Inventors: Matthew Scott Abrams, Young Gon Kim, Myunghee Lee, Stefano Therisod, Robert Elsheimer
-
Patent number: 7061122Abstract: An ultra thin system-in-a-package (SIP) with independent test and repair capability comprises an interposer having arranged on a top surface and a bottom surface thereof a number of packaged semiconductor chips mounted via solder bumps in accordance with a Land Grid Array (LGA) format and wherein no underfill is used on the SIP.Type: GrantFiled: October 10, 2003Date of Patent: June 13, 2006Assignee: Tessera, Inc.Inventors: Young-Gon Kim, David Gibson, Michael Warner, Philip Damberg, Philip Osborn
-
Patent number: 7043657Abstract: A synchronous bus system includes a clock line having a forward direction clock segment and a reverse direction clock segment connected to each of a plurality of devices. The forward direction clock segment carries a forward direction clock signal, and the reverse direction clock segment carries a reverse direction clock signal. Synchronization clock circuitry, provided in each device, receives the forward direction clock signal and the reverse direction clock signal. Using the received clock signals, the synchronization clock circuitry derives a universal synchronization clock signal which is synchronous throughout all devices. Skew correction circuitry, provided in at least a portion of the devices, corrects for skew between the universal synchronization clock signal and one or more data signals for transferring data between devices.Type: GrantFiled: October 8, 2003Date of Patent: May 9, 2006Assignee: Integrated Memory Logic, Inc.Inventors: Jeongsik Yang, Young Gon Kim, Chiayao S. Tung, Shuen-Chin Chang, Yong E. Park
-
Publication number: 20060033216Abstract: A stacked chip assembly includes individual units having chips mounted on dielectric layers and traces on the dielectric layers interconnecting the contacts of the chips with terminals disposed in peripheral regions of the dielectric layers. At least some of the traces are multi-branched traces which connect chip select contacts to chip select terminals. The units are stacked one above the other with corresponding terminals of the different units being connected to one another by solder balls or other conductive elements so as to form vertical buses. Prior to stacking, the multi-branched traces of the individual units are selectively connected, as by forming solder bridges, so as to leave chip select contacts of chips in different units connected to different chip select terminals and thereby connect these chips to different vertical buses. The individual units desirably are thin and directly abut one another so as to provide a low-height assembly with good heat transfer from chips within the stack.Type: ApplicationFiled: October 17, 2005Publication date: February 16, 2006Applicant: Tessera, Inc.Inventors: L. Pflughaupt, David Gibson, Young-Gon Kim, Craig Mitchell, Wael Zohni, Ilyas Mohammed
-
Publication number: 20060004971Abstract: Memory systems and methods of controlling a flash memory are provided that execute one of a plurality of merge stages of an incremental merge operation responsive to receiving a command to the flash memory. Executing one of a plurality of merge stages may include receiving a command to the flash memory, determining whether the flash memory is executing an incremental merge operation and executing a next merge stage of the incremental merge operation if the flash memory is executing an incremental merge operation.Type: ApplicationFiled: November 16, 2004Publication date: January 5, 2006Inventors: Jin-Hyuk Kim, Chan-Ik Park, Young-Gon Kim, Kyong-Ae Kim
-
Patent number: 6977440Abstract: A stacked chip assembly includes individual units having chips mounted on dielectric layers and traces on the dielectric layers interconnecting the contacts of the chips with terminals disposed in peripheral regions of the dielectric layers. At least some of the traces are multi-branched traces which connect chip select contacts to chip select terminals. The units are stacked one above the other with corresponding terminals of the different units being connected to one another by solder balls or other conductive elements so as to form vertical buses. Prior to stacking, the multi-branched traces of the individual units are selectively connected, as by forming solder bridges, so as to leave chip select contacts of chips in different units connected to different chip select terminals and thereby connect these chips to different vertical buses. The individual units desirably are thin and directly abut one another so as to provide a low-height assembly with good heat transfer from chips within the stack.Type: GrantFiled: June 4, 2003Date of Patent: December 20, 2005Assignee: Tessera, Inc.Inventors: L. Elliott Pflughaupt, David Gibson, Young-Gon Kim, Craig S. Mitchell, Wael Zohni, Ilyas Mohammed
-
Patent number: 6937664Abstract: An apparatus for providing multi-symbol signaling includes a multi-symbol encoder circuit. The multi-symbol encoder circuit is operable to encode data into a plurality of symbols, each symbol uniquely defined by a signal transition and a signal region in a carrier signal. A driver circuit, coupled to the multi-symbol encoder circuit, is operable to drive the carrier signal.Type: GrantFiled: July 18, 2000Date of Patent: August 30, 2005Assignee: Integrated Memory Logic, Inc.Inventors: Yong E. Park, Jeongsik Yang, Shuen-Chin Chang, Young Gon Kim, Chiayao S. Tung, Cindy Y. Ng
-
Publication number: 20050173796Abstract: A microelectronic assembly and a fabrication method are provided which includes a microelectronic element such as a chip or element of a package. A plurality of surface-mountable contacts are arranged in an array exposed at a major surface of the microelectronic element. One or more passive elements, e.g., a resistor, inductor, capacitor, or combination of the same are mounted to the microelectronic element, with an inner terminal of the passive element conductively mounted to an exposed surface of one contact and an outer terminal displaced vertically from the major surface of the microelectronic element.Type: ApplicationFiled: February 22, 2005Publication date: August 11, 2005Applicant: Tessera, Inc.Inventors: L. Pflughaupt, David Gibson, Young-Gon Kim, Craig Mitchell, Wael Zohni, Ilyas Mohammed
-
Publication number: 20050168231Abstract: A probe for testing semiconductor chips includes a plurality of probe contacts providing z-direction compliancy. The probe contacts include a blind opening surrounded by a lateral sidewall for receiving an aligned chip contact. The chip contacts are manipulated with a downward vertical force and along a horizontal path for engagement with various portions of the probe contact within the blind opening. The alignment may be actively monitored for determining minimum contact resistance during the probing process.Type: ApplicationFiled: December 22, 2004Publication date: August 4, 2005Inventor: Young-Gon Kim
-
Patent number: 6913949Abstract: A stacked chip assembly includes individual units having chips mounted on dielectric layers and traces on the dielectric layers interconnecting the contacts of the chips with terminals disposed in peripheral regions of the dielectric layers. At least some of the traces are multi-branched traces which connect chip select contacts to chip select terminals. The units are stacked one above the other with corresponding terminals of the different units being connected to one another by solder balls or other conductive elements so as to form vertical buses. Prior to stacking, the multi-branched traces of the individual units are selectively interrupted, as by breaking the individual branches, so as to leave chip select contacts of chips in different units connected to different chip select terminals and thereby connect these chips to different vertical buses.Type: GrantFiled: April 28, 2004Date of Patent: July 5, 2005Assignee: Tessera, Inc.Inventors: L. Elliott Pflughaupt, David Gibson, Young-Gon Kim, Craig S. Mitchell
-
Publication number: 20050116326Abstract: A connection component for mounting a chip or other microelectronic element is formed from a starting unit including posts projecting from a dielectric element by crushing or otherwise reducing the height of at least some of the posts.Type: ApplicationFiled: October 6, 2004Publication date: June 2, 2005Applicant: Tessera, Inc.Inventors: Belgacem Haba, Masud Beroz, Young-Gon Kim, David Tuckerman
-
Patent number: 6897565Abstract: A stacked chip assembly includes individual units having chips mounted on dielectric layers and traces on the dielectric layers interconnecting the contacts of the chips with terminals disposed in peripheral regions of the dielectric layers. At least some of the traces are multi-branched traces which connect chip select contacts to chip select terminals. The units are stacked one above the other with corresponding terminals of the different units being connected to one another by solder balls or other conductive elements so as to form vertical buses. Prior to stacking, the multi-branched traces of the individual units are selectively interrupted, as by breaking the individual branches, so as to leave chip select contacts of chips in different units connected to different chip select terminals and thereby connect these chips to different vertical buses.Type: GrantFiled: October 9, 2002Date of Patent: May 24, 2005Assignee: Tessera, Inc.Inventors: L. Elliott Pflughaupt, David Gibson, Young-Gon Kim, Craig S. Mitchell
-
Publication number: 20040262777Abstract: An ultra thin system-in-a-package (SIP) with independent test and repair capability comprises an interposer having arranged on a top surface and a bottom surface thereof a number of packaged semiconductor chips mounted via solder bumps in accordance with a Land Grid Array (LGA) format and wherein no underfill is used on the SIP.Type: ApplicationFiled: October 10, 2003Publication date: December 30, 2004Applicant: Tessera, Inc.Inventors: Young-Gon Kim, David Gibson, Michael Warner, Philip Damberg, Philip Osborn
-
Publication number: 20040203190Abstract: A stacked chip assembly includes individual units having chips mounted on dielectric layers and traces on the dielectric layers interconnecting the contacts of the chips with terminals disposed in peripheral regions of the dielectric layers. At least some of the traces are multi-branched traces which connect chip select contacts to chip select terminals. The units are stacked one above the other with corresponding terminals of the different units being connected to one another by solder balls or other conductive elements so as to form vertical buses. Prior to stacking, the multi-branched traces of the individual units are selectively interrupted, as by breaking the individual branches, so as to leave chip select contacts of chips in different units connected to different chip select terminals and thereby connect these chips to different vertical buses.Type: ApplicationFiled: April 28, 2004Publication date: October 14, 2004Applicant: Tessera, Inc.Inventors: L. Elliott Pflughaupt, David Gibson, Young-Gon Kim, Craig S. Mitchell
-
Publication number: 20040145054Abstract: A bottom unit including a bottom unit semiconductor chip is mounted to a circuit board and one or more top elements such as packaged semiconductor chips are mounted to the bottom unit. Both mounting operations can be performed using the same techniques as commonly employed for mounting components to a circuit board. Ordinary packaged chips can be employed as the top elements, thereby reducing the cost of the assembly and allowing customization of the assembly by selecting packaged chips. The assembly achieves benefits similar to those obtained with a preassembled stacked chip unit, but without the expense of special handling of the bare dies included in the packaged chips.Type: ApplicationFiled: September 5, 2003Publication date: July 29, 2004Applicant: Tessera, Inc.Inventors: Kyong-Mo Bang, David Gibson, Young-Gon Kim, John B. Riley
-
Patent number: 6763486Abstract: Boundary scan testing methods that detect manufacturing defects in AC-coupled differential pairs may be based on a selected signal parameter: phase or frequency. The data is encoded by the signal parameter. In one embodiment, the signal parameter is compared to reference parameter data provided by the transmitter. In a second embodiment, the reference parameter data is sent from an external source. All the components on board are synchronized with this external source. In a third embodiment, the reference parameter data is embedded in each AC signal between the transmitter and receiver. Two lines of one differential link are used to send different patterns.Type: GrantFiled: May 9, 2001Date of Patent: July 13, 2004Assignee: Agilent Technologies, Inc.Inventors: Benny W H Lai, Young Gon Kim, Kenneth P Parker, Jeff Rearick
-
Publication number: 20040120630Abstract: An integrated circuit cast on a single die having a plurality of receivers in a receiver region, a plurality of transmitters in a transmitter region, and a spatial separation region having a plurality of n-type and p-type subregions disposed on the single die to separate the transmitter region from the receiver region. The pn-junctions between the n-type and p-type subregions are reverse-biased thereby reducing or eliminating coupling of noise and crosstalk between the transmitter and receiver is reduced.Type: ApplicationFiled: December 20, 2002Publication date: June 24, 2004Inventors: Matthew Scott Abrams, Young Gon Kim, Myunghee Lee, Stefano Therisod, Robert Elsheimer
-
Publication number: 20040105244Abstract: A lead assembly including a connector connecting structure having a plurality of separable portions and a plurality of leads. Each of the leads defined that they have a first end, a second end, a lead axis defined by the first and the second end, and an offset portion disposed between the first end and the second end. The offset portion being offset from the lead axis and adapted to be displaced downwardly with respect to the lead axis and bonded to a contact. The leads are preferably integral with the connecting structure. The connecting structure may be arranged outwardly of the leads, or may include parts interdispersed between groups of leads. The groups of leads may or may not correspond to individual units incorporating a microelectronic element.Type: ApplicationFiled: August 6, 2003Publication date: June 3, 2004Inventors: Ilyas Mohammed, Young-Gon Kim
-
Publication number: 20040031972Abstract: A stacked chip assembly includes individual units having chips mounted on dielectric layers and traces on the dielectric layers interconnecting the contacts of the chips with terminals disposed in peripheral regions of the dielectric layers. At least some of the traces are multi-branched traces which connect chip select contacts to chip select terminals. The units are stacked one above the other with corresponding terminals of the different units being connected to one another by solder balls or other conductive elements so as to form vertical buses. Prior to stacking, the multi-branched traces of the individual units are selectively connected, as by forming solder bridges, so as to leave chip select contacts of chips in different units connected to different chip select terminals and thereby connect these chips to different vertical buses. The individual units desirably are thin and directly abut one another so as to provide a low-height assembly with good heat transfer from chips within the stack.Type: ApplicationFiled: June 4, 2003Publication date: February 19, 2004Applicant: Tessera, Inc.Inventors: L. Elliott Pflughaupt, David Gibson, Young-Gon Kim, Craig S. Mitchell, Wael Zohni, Ilyas Mohammed