Patents by Inventor Young Hee Kim
Young Hee Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150236118Abstract: Field effect transistors fabricated using atomic layer doping processes are disclosed. In accordance with an embodiment of an atomic layer doping method, a semiconducting surface and a dopant gas mixture are prepared. Further, a dopant layer is grown on the semiconducting surface by applying the dopant gas mixture to the semiconducting surface under a pressure that is less than 500 Torr and a temperature that is between 300° C. and 750° C. The dopant layer includes at least 4×1020 active dopant atoms per cm3 that react with atoms on the semiconducting surface such that the reacted atoms increase the conductivity of the semiconducting surface.Type: ApplicationFiled: April 29, 2015Publication date: August 20, 2015Inventors: KEVIN K. CHAN, YOUNG-HEE KIM, ISAAC LAUER, RAMACHANDRAN MURALIDHAR, DAE-GYU PARK, XINHUI WANG, MIN YANG
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Publication number: 20150214364Abstract: A semiconductor fin including a single crystalline semiconductor material is formed on a dielectric layer. A semiconductor shell including an epitaxial semiconductor material is formed on all physically exposed surfaces of the semiconductor fin by selective epitaxy, which deposits the semiconductor material only on semiconductor surfaces and not on dielectric surfaces. The epitaxial semiconductor material can be different from the single crystalline semiconductor material, and the semiconductor shell can be bilaterally strained due to lattice mismatch. A fin field effect transistor including a strained channel can be formed. Further, the semiconductor shell can advantageously alter properties of the source and drain regions, for example, by allowing incorporation of more dopants or by facilitating a metallization process.Type: ApplicationFiled: January 24, 2014Publication date: July 30, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin K. Chan, Young-Hee Kim, Masaharu Kobayashi, Jinghong Li, Dae-Gyu Park
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Publication number: 20150193964Abstract: Disclosed herein is a real-time dynamic non-planar projection apparatus and method, which can reduce visual errors, such as distortion of a screen image or deviation from a border area, upon projecting screen images from a projector onto the surface of a non-planar object that is moved in real time. The presented real-time dynamic non-planar projection apparatus includes a preprocessing unit for preprocessing data related to a static part of a screen image to be projected onto a non-planar surface. A real-time projection unit classifies non-planar objects in the screen image to be projected onto the non-planar surface into a rigid body and a non-rigid body using data output from the preprocessing unit, respectively renders the rigid body and the non-rigid body depending on a viewer's current viewpoint, and projects rendered results onto the non-planar surface via projection mapping.Type: ApplicationFiled: January 6, 2015Publication date: July 9, 2015Inventors: Hang-Kee KIM, Young-Hee KIM, Yong-Sun KIM, Ki-Hong KIM, Hyun-Woo CHO, Jin-Ho KIM
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Patent number: 9076250Abstract: An apparatus for 3D reconstruction based on multiple GPUs and a method thereof are disclosed. The 3D reconstruction apparatus according to the present invention includes a 3D reconstruction apparatus, comprising: a camera configured to generate depth data for 3D space; a first GPU configured to update first TSDF volume data with first depth data generated for a first area and predict a surface point of an object which is present in the space from the first updated TSDF volume data; a second GPU configured to update second TSDF volume data with second depth data generated for a second area and predict a surface point of an object which is present in the space from the second updated TSDF volume data; and a master GPU configured to combine a surface point predicted from the first TSDF volume data and a surface point estimated from the second TSDF volume data.Type: GrantFiled: July 11, 2013Date of Patent: July 7, 2015Assignee: Electronics and Telecommunications Research InstituteInventors: Young Hee Kim, Ki Hong Kim, Jin Ho Kim
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Publication number: 20150179739Abstract: A stack of a germanium-containing layer and a dielectric cap layer is formed on an insulator layer. The stack is patterned to form germanium-containing semiconductor fins and germanium-containing mandrel structures with dielectric cap structures thereupon. A dielectric masking layer is deposited and patterned to mask the germanium-containing semiconductor fins, while physically exposing sidewalls of the germanium-containing mandrel structures. A ring-shaped compound semiconductor fin is formed around each germanium-containing mandrel structure by selective epitaxy of a compound semiconductor material. A center portion of each germanium-containing mandrel can be removed to physically expose inner sidewalls of the ring-shaped compound semiconductor fin. A high-mobility compound semiconductor layer can be formed on physically exposed surfaces of the ring-shaped compound semiconductor fin.Type: ApplicationFiled: December 20, 2013Publication date: June 25, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin K. Chan, Cheng-Wei Cheng, Young-Hee Kim, Masaharu Kobayashi, Effendi Leobandung, Dae-Gyu Park, Devendra K. Sadana
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Patent number: 9054192Abstract: A stack of a germanium-containing layer and a dielectric cap layer is formed on an insulator layer. The stack is patterned to form germanium-containing semiconductor fins and germanium-containing mandrel structures with dielectric cap structures thereupon. A dielectric masking layer is deposited and patterned to mask the germanium-containing semiconductor fins, while physically exposing sidewalls of the germanium-containing mandrel structures. A ring-shaped compound semiconductor fin is formed around each germanium-containing mandrel structure by selective epitaxy of a compound semiconductor material. A center portion of each germanium-containing mandrel can be removed to physically expose inner sidewalls of the ring-shaped compound semiconductor fin. A high-mobility compound semiconductor layer can be formed on physically exposed surfaces of the ring-shaped compound semiconductor fin.Type: GrantFiled: December 20, 2013Date of Patent: June 9, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin K. Chan, Cheng-Wei Cheng, Young-Hee Kim, Masaharu Kobayashi, Effendi Leobandung, Dae-Gyu Park, Devendra K. Sadana
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Patent number: 9048261Abstract: Field effect transistors fabricated using atomic layer doping processes are disclosed. In accordance with an embodiment of an atomic layer doping method, a semiconducting surface and a dopant gas mixture are prepared. Further, a dopant layer is grown on the semiconducting surface by applying the dopant gas mixture to the semiconducting surface under a pressure that is less than 500 Torr and a temperature that is between 300° C. and 750° C. The dopant layer includes at least 4×1020 active dopant atoms per cm3 that react with atoms on the semiconducting surface such that the reacted atoms increase the conductivity of the semiconducting surface.Type: GrantFiled: August 4, 2011Date of Patent: June 2, 2015Assignee: International Business Machines CorporationInventors: Kevin K. Chan, Young-Hee Kim, Isaac Lauer, Ramachandran Muralidhar, Dae-Gyu Park, Xinhui Wang, Min Yang
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Publication number: 20150138892Abstract: The present invention proposes a single poly EEPROM cell including a first control gate capacitor, a first tunnel gate capacitor, a first sense transistor, and a first selection transistor. In a single poly EEPROM cell according to the present invention, a Fowler Nordheim (FN) tunneling method is used in order to increase the recognition distance of an RFID tag chip in mode. In a single poly EEPROM device including a single poly EEPROM cell, the single poly EEPROM cell includes a first control gate capacitor MC1, a first tunnel gate capacitor MC2, a first sense transistor MN1, and a first selection transistor MN2, and the first sense transistor MN1 and the first selection transistor MN2 share a P type well PW.Type: ApplicationFiled: February 6, 2014Publication date: May 21, 2015Applicant: Changwon National University Industry Academy Cooperation CorpsInventor: Young-Hee KIM
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Publication number: 20150139532Abstract: Provided are an apparatus and method for tracking a camera that reconstructs a real environment in three dimensions by using reconstruction segments and a volumetric surface. The camera tracking apparatus using reconstruction segments and a volumetric surface includes a reconstruction segment division unit configured to divide three-dimensional space reconstruction segments extracted from an image acquired by a camera, a transformation matrix generation unit configured to generate a transformation matrix for at least one reconstruction segment among the reconstruction segments obtained by the reconstruction segment division unit, and a reconstruction segment connection unit configured to rotate or move the at least one reconstruction segment according to the transformation matrix generated by the reconstruction segment division unit and connect the rotated and moved reconstruction segment with another reconstruction segment.Type: ApplicationFiled: June 25, 2014Publication date: May 21, 2015Inventors: Young Hee KIM, Jin Ho KIM, Ki Hong KIM, Gil Haeng LEE
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Patent number: 9034748Abstract: Embodiments include a method comprising depositing a hard mask layer over a first layer, the hard mask layer including; lower hard mask layer, hard mask stop layer, and upper hard mask. The hard mask layer and the first layer are patterned and a spacer deposited on the patterned sidewall. The upper hard mask layer and top portion of the spacer are removed by selective etching with respect to the hard mask stop layer, the remaining spacer material extending to a first predetermined position on the sidewall. The hard mask stop layer is removed by selective etching with respect to the lower hard mask layer and spacer. The first hard mask layer and top portion of the spacer are removed by selectively etching the lower hard mask layer and the spacer with respect to the first layer, the remaining spacer material extending to a second predetermined position on the sidewall.Type: GrantFiled: September 4, 2013Date of Patent: May 19, 2015Assignee: International Business Machines CorporationInventors: Christopher V. Baiocco, Kevin K. Chan, Young-Hee Kim, Masaharu Kobayashi, Effendi Leobandung, Fei Liu, Dae-Gyu Park, Helen Wang, Xinhui Wang, Min Yang
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Publication number: 20150064897Abstract: Embodiments include a method comprising depositing a hard mask layer over a first layer, the hard mask layer including; lower hard mask layer, hard mask stop layer, and upper hard mask. The hard mask layer and the first layer are patterned and a spacer deposited on the patterned sidewall. The upper hard mask layer and top portion of the spacer are removed by selective etching with respect to the hard mask stop layer, the remaining spacer material extending to a first predetermined position on the sidewall. The hard mask stop layer is removed by selective etching with respect to the lower hard mask layer and spacer. The first hard mask layer and top portion of the spacer are removed by selectively etching the lower hard mask layer and the spacer with respect to the first layer, the remaining spacer material extending to a second predetermined position on the sidewall.Type: ApplicationFiled: September 4, 2013Publication date: March 5, 2015Applicant: International Business Machines CorporationInventors: Christopher V. Baiocco, Kevin K. Chan, Young-Hee Kim, Masaharu Kobayashi, Effendi Leobandung, Fei Liu, Dae-Gyu Park, Helen Wang, Xinhui Wang, Min Yang
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Patent number: 8962374Abstract: A stack of a first anti-reflective coating (ARC) layer and a titanium layer is formed on a front surface of a semiconductor substrate including a p-n junction, and is subsequently patterned so that a semiconductor surface is physically exposed in metal contact regions of the front surface of the semiconductor substrate. The remaining portion of the titanium layer is converted into a titania layer by oxidation. A metal layer is plated on the metal contact regions, and a copper line is subsequently plated on the metal layer or a metal semiconductor alloy derived from the metal layer. A second ARC layer is deposited over the titania layer and the copper line, and is subsequently patterned to provide electrical contact to the copper line.Type: GrantFiled: June 27, 2012Date of Patent: February 24, 2015Assignee: International Business Machines CorporationInventors: Satyavolu S. Papa Rao, Kathryn C. Fisher, Harold J. Hovel, Qiang Huang, Susan Huang, Young-Hee Kim
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Publication number: 20150042106Abstract: The present invention relates to a closed force transmission device in which an insertion depth of a latch bolt inserted into a latch bolt insertion groove can be adjusted to improve safety and components are simplified to allow for ease of assembly and to improve durability. The present invention also relates to a safety door lock using the device. The closed force transmission device of the present invention includes: a cylindrical body housing of which both sides are opened to penetrate a door; a main body slidably arranged within the body housing such that the main body moves in a straight line direction by the force applied from an external source, the main body having at least one tilt surface and a main body movement space formed orthogonally to the straight movement direction in a portion corresponding to the tilt surface.Type: ApplicationFiled: March 15, 2012Publication date: February 12, 2015Inventor: Young Hee Kim
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Patent number: 8946844Abstract: A stack of a first anti-reflective coating (ARC) layer and a titanium layer is formed on a front surface of a semiconductor substrate including a p-n junction, and is subsequently patterned so that a semiconductor surface is physically exposed in metal contact regions of the front surface of the semiconductor substrate. The remaining portion of the titanium layer is converted into a titania layer by oxidation. A metal layer is plated on the metal contact regions, and a copper line is subsequently plated on the metal layer or a metal semiconductor alloy derived from the metal layer. A second ARC layer is deposited over the titania layer and the copper line, and is subsequently patterned to provide electrical contact to the copper line.Type: GrantFiled: February 28, 2013Date of Patent: February 3, 2015Assignee: International Business Machines CorporationInventors: Satyavolu S. Papa Rao, Kathryn C. Fisher, Harold J. Hovel, Qiang Huang, Young-hee Kim, Susan Huang
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Patent number: 8916272Abstract: Disclosed is a surface protective film, a method for fabricating the same, and pouch, and a method for fabricating the same. The surface protective film includes a stack of films including a middle layer, and a first skin layer and a second skin layer on opposite sides of the middle layer, wherein at least one of the first skin layer and the second skin layer is formed of a resin having a hardness lower than a hardness of a surface to be protected by the surface protective film, and the middle layer is formed of a resin including high density polyethylene, thereby permitting protection of a display surface without formation of scratch at a very low cost compared to the related art without aging and with slip.Type: GrantFiled: October 20, 2008Date of Patent: December 23, 2014Assignee: LG Display Co., Ltd.Inventors: Ki Mock Son, Jong Hak Kim, Young Hee Kim, Han Jun Kang, Hee Sik Han, Sang Min Lee, Jong Seon Kim
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Patent number: 8912032Abstract: Current may be passed through an n-doped semiconductor region, a recessed metal semiconductor alloy portion, and a p-doped semiconductor region so that the diffusion of majority charge carriers in the doped semiconductor regions transfers heat from or into the semiconductor waveguide through Peltier-Seebeck effect. Further, a temperature control device may be configured to include a metal semiconductor alloy region located in proximity to an optoelectronic device, a first semiconductor region having a p-type doping, and a second semiconductor region having an n-type doping. The temperature of the optoelectronic device may thus be controlled to stabilize the performance of the optoelectronic device.Type: GrantFiled: January 23, 2013Date of Patent: December 16, 2014Assignee: International Business Machines CorporationInventors: Solomon Assefa, William M. Green, Young-hee Kim, Joris Van Campenhout, Yurii A. Vlasov
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Patent number: 8872817Abstract: A real-time three-dimensional (3D) real environment reconstruction apparatus and method are provided. The real-time 3D real environment reconstruction apparatus reconstructs a 3D real environment in real-time, or processes data input through RGB-D cameras in real-time using a plurality of GPUs so as to reconstruct a wide ranging 3D real environment.Type: GrantFiled: July 13, 2012Date of Patent: October 28, 2014Assignee: Electronics and Telecommunications Research InstituteInventor: Young-Hee Kim
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Patent number: 8861728Abstract: The present disclosure relates to integrated circuits having tamper detection and response devices and methods for manufacturing such integrated circuits. One integrated circuit having a tamper detection and response device includes at least one photovoltaic cell and at least one memory cell coupled to the at least one photovoltaic cell. When the at least one photovoltaic cell is exposed to radiation, the at least one photovoltaic cell generates a current that causes an alteration to a memory state of the at least one memory cell. Another integrated circuit having a tamper detection and response device includes at least one photovoltaic cell and a reactive material coupled to the at least one photovoltaic cell, wherein a current from the at least one photovoltaic cell triggers an exothermic reaction in the reactive material.Type: GrantFiled: October 17, 2012Date of Patent: October 14, 2014Assignee: International Business Machines CorporationInventors: Jack O. Chu, Gregory M. Fritz, Harold J. Hovel, Young-Hee Kim, Dirk Pfeiffer, Kenneth P. Rodbell
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Patent number: 8759139Abstract: A method of forming a photovoltaic device containing a buried emitter region and vertical metal contacts is provided. The method includes forming a plurality of metal nanoparticles on exposed portions of a single-crystalline silicon substrate that are not covered by patterned antireflective coatings (ARCs). A metal nanoparticle catalyzed etching process is then used to form trenches within the single-crystalline silicon substrate and thereafter the metal nanoparticles are removed from the trenches. An emitter region is then formed within exposed portions of the single-crystalline silicon substrate, and thereafter a metal contact is formed atop the emitter region.Type: GrantFiled: August 18, 2011Date of Patent: June 24, 2014Assignee: International Business Machines CorporationInventors: Jun Liu, Qiang Huang, Young-Hee Kim
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Patent number: 8748252Abstract: Methods of fabricating replacement metal gate transistors using bi-layer a hardmask are disclosed. By utilizing a bi-layer hardmask comprised of a first layer of nitride, followed by a second layer of oxide, the topography issues caused by transition regions of gates are mitigated, which simplifies downstream processing steps and improves yield.Type: GrantFiled: November 26, 2012Date of Patent: June 10, 2014Assignee: International Business Machines CorporationInventors: Effendi Leobandung, William Cote, Laertis Economikos, Young-Hee Kim, Dae-Gyu Park, Theodorus Eduardus Standaert, Kenneth Jay Stein, YS Suh, Min Yang