Abstract: A semiconductor memory apparatus includes a plurality of stacked semiconductor dies including a first semiconductor die comprising a first internal circuit configured to control input timing of a test control signal that is output as a plurality of delayed test control signals to the plurality of stacked semiconductor dies according to the controlled input timing in response to a test mode signal.

Abstract: A stacked semiconductor package includes a package substrate, an interposer mounted on the package substrate, a plurality of semiconductor chips stacked on the interposer, and a control unit provided in the interposer, that stores in advance data to be written in the plurality of semiconductor chips, and that outputs the data stored in advance according a test mode signal.

Abstract: A semiconductor apparatus includes a plurality of memory banks configured to perform a refresh operation in response to an address count value and row active signals; a refresh control block configured to update refresh bank informations which define a bank designated to perform the refresh operation in response to a refresh command and bank addresses, and activate a count control signal in response to the refresh bank informations; and a counter configured to change the address count value in response to activation of the count control signal.

Abstract: A semiconductor device includes a column command generation unit suitable for generating a column command delayed by a first delay time from a source command, in response to a first control signal and the source command, a bank address generation unit suitable for generating a bank address delayed by the first delay time from a bank source address, in response to the first control signal and the bank source address, a precharge command generation unit suitable for generating a precharge command delayed by a second delay time from the column command, in response to a second control signal and the column command, and a precharge bank address generation unit suitable for generating a precharge bank address delayed by the second delay time from the bank address, in response to the second control signal and the bank address.

Abstract: A strobe signal generation circuit may include: a counter to generate a first source signal and a second source signal by counting an external strobe signal; a delay to generate a first delayed signal and a second delayed signal by delaying the first source signal and the second source signal by a preset time; and a combination unit to generate internal strobe signals by selectively combining the first source signal, the second source signal, the first delayed signal, and the second delayed signal.

Abstract: A semiconductor memory apparatus includes a plurality of data storage regions; a first internal circuit configured to input a plurality of control signals to the plurality of data storage regions; and a second internal circuit configured to control input timing of a test control signal, and input the test control signal to the plurality of data storage regions according to the controlled input timing in response to a test mode signal.

Abstract: A semiconductor memory device includes: a master chip suitable for generating a plurality of first control signals and a second control signal based on a read command; and a plurality of slave chips each suitable for latching data read from a plurality of memory cells included in a corresponding slave chip and transmitting the latched data to the master chip based on a correspond control signal of the first control signals, wherein the master chip latches the data transmitted from the slave chips based on the first control signals and outputs the data latched in the master chip based on the second control signal.

Abstract: A semiconductor apparatus includes a plurality of memory banks configured to perform a refresh operation in response to an address count value and row active signals; a refresh control block configured to update refresh bank informations which define a bank designated to perform the refresh operation in response to a refresh command and bank addresses, and activate a count control signal in response to the refresh bank informations; and a counter configured to change the address count value in response to activation of the count control signal.

Abstract: A semiconductor apparatus includes a control signal reception portion. The control signal reception portion may set information related to operation of a memory chip by receiving a command signal and an address signal from one among a stack chip test portion, a control signal interface portion and a test setting portion.

Abstract: A semiconductor apparatus includes a first output control unit and a second output control unit. The first output control unit includes a plurality of non-inversion pipes and a plurality of inversion pipes. The non-inversion pipes non-invert input signals and output the non-inverted input signals to a signal transmission line as transmission signal, and the inversion pipes invert input signals and output the inverted input signals to the signal transmission line as the transmission signals. The second output control unit includes a plurality of non-inversion pipes and a plurality of inversion pipes. The non-inversion pipes non-invert the transmission signals and output the non-inverted transmission signals, and the inversion pipes invert the transmission signals and output the inverted transmission signals.

Abstract: A semiconductor apparatus includes a clock enable signal buffer unit configured to receive an input clock enable signal, and generate an output clock enable signal; a buffer control unit configured to generate a buffer enable signal in response to the output clock enable signal and a test enable signal; an input/output buffer unit configured to receive input patterns and generate output patterns; and a compression test unit configured to test the output patterns and the output clock enable signal according to the test enable signal.

Abstract: A semiconductor memory device includes a first pre-charge control block suitable for generating a first control signal by counting a number of toggles of an operation clock in response to a first active pulse in a self-refresh operation exit mode, a second pre-charge control block suitable for generating a second control signal in response to an active command for an active operation in a self-refresh operation mode, and an operation control block suitable for disabling the first pre-charge control block in the self-refresh operation mode, and disabling the second pre-charge control block in a self-refresh operation exit mode, wherein a pre-charge operation starts in response to the first and second control signals after the active operation. The semiconductor memory device may then be secured in a minimal time for stably performing an active operation during a self-refresh operation.

Abstract: A semiconductor apparatus includes a clock enable signal buffer unit configured to receive an input clock enable signal, and generate an output clock enable signal; a buffer control unit configured to generate a buffer enable signal in response to the output clock enable signal and a test enable signal; an input/output buffer unit configured to receive input patterns and generate output patterns; and a compression test unit configured to test the output patterns and the output clock enable signal according to the test enable signal.

Abstract: A semiconductor memory device includes: a core block suitable for storing write data as normal data or a part of combined data according to a data masking signal, and masking information indicating data masking of the combined data; and an error correcting code (ECC) block suitable for performing an ECC decoding operation on the normal data, and bypassing the ECC decoding operation on the combined data according to the masking information, wherein the combined data further includes masked data.

Abstract: A stacked semiconductor package includes a package substrate, an interposer mounted on the package substrate, a plurality of semiconductor chips stacked on the interposer, and a control unit provided in the interposer, that stores in advance data to be written in the plurality of semiconductor chips, and that outputs the data stored in advance according a test mode signal.

Abstract: A semiconductor memory apparatus includes a plurality of data storage regions; a first internal circuit configured to input a plurality of control signals to the plurality of data storage regions; and a second internal circuit configured to control input timing of a test control signal, and input the test control signal to the plurality of data storage regions according to the controlled input timing in response to a test mode signal.

Abstract: A semiconductor apparatus includes a plurality of memory banks configured to perform a refresh operation in response to an address count value and row active signals; a refresh control block configured to update refresh bank informations which define a bank designated to perform the refresh operation in response to a refresh command and bank addresses, and activate a count control signal in response to the refresh bank informations; and a counter configured to change the address count value in response to activation of the count control signal.

Abstract: A semiconductor memory device includes: a master chip suitable for generating a plurality of first control signals and a second control signal based on a read command; and a plurality of slave chips each suitable for latching data read from a plurality of memory cells included in a corresponding slave chip and transmitting the latched data to the master chip based on a correspond control signal of the first control signals, wherein the master chip latches the data transmitted from the slave chips based on the first control signals and outputs the data latched in the master chip based on the second control signal.

Abstract: A semiconductor apparatus includes a control signal reception portion. The control signal reception portion may set information related to operation of a memory chip by receiving a command signal and an address signal from one among a stack chip test portion, a control signal interface portion and a test setting portion.

Abstract: A semiconductor memory device includes a plurality of banks, a plurality of compression blocks configured to compress a plurality of first read data respectively provided by the banks and output a plurality of second read data, a plurality of pipe latches configured to latch the second read data and output third read data in series, an output controller configured to receive the third read data from the pipe latches and sequentially output fourth read data in response to a plurality of bank addresses and a read enable signal, and a pad configured to transfer the fourth read data sequentially outputted from the output controller to an outside of the semiconductor memory device.