Patents by Inventor Young Jun Ku
Young Jun Ku has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150170722Abstract: A semiconductor memory device includes a first pre-charge control block suitable for generating a first control signal by counting a number of toggles of an operation clock in response to a first active pulse in a self-refresh operation exit mode, a second pre-charge control block suitable for generating a second control signal in response to an active command for an active operation in a self-refresh operation mode, and an operation control block suitable for disabling the first pre-charge control block in the self-refresh operation mode, and disabling the second pre-charge control block in a self-refresh operation exit mode, wherein a pre-charge operation starts in response to the first and second control signals after the active operation. The semiconductor memory device may then be secured in a minimal time for stably performing an active operation during a self-refresh operation.Type: ApplicationFiled: April 18, 2014Publication date: June 18, 2015Applicant: SK hynix Inc.Inventors: Tae-Sik YUN, Jae-Bum KO, Young-Jun KU
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Publication number: 20150171875Abstract: A clock generation circuit includes a counting unit configured to generate a counting code during a preset time section of an input clock; a control code generation unit configured to generate a decoding code by varying the counting code; and a variable period oscillation unit configured to generate an output clock having a frequency corresponding to the decoding code.Type: ApplicationFiled: April 9, 2014Publication date: June 18, 2015Applicant: SK hynix Inc.Inventors: Ji Hwan KIM, Young Jun KU
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Patent number: 8994419Abstract: A semiconductor device may include first to fourth output lines, an input signal latch unit suitable for latching first to fourth input signals that are sequentially inputted in response to first to fourth clocks having sequential phases, respectively, a valid signal latch unit suitable for latching a valid signal in response to one clock among the first to fourth clocks, where the valid signal corresponds to one input signal among the first to fourth input signals and represents whether the corresponding input signal is valid or not, and a signal transfer unit suitable for transferring the latched input signals, which are obtained by latching the input signals in response to the first to fourth clocks, to the first to fourth output lines based on a correspondence relationship that is decided based on a valid signal latch result of the valid signal latch unit.Type: GrantFiled: December 17, 2013Date of Patent: March 31, 2015Assignee: SK Hynix Inc.Inventor: Young-Jun Ku
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Patent number: 8963596Abstract: A semiconductor apparatus includes: a clock receiving unit configured to receive an external clock signal and output the received clock signal as a reference clock signal; a delay locked loop (DLL) configured to delay the reference clock signal by a variable delay amount and generate a data latch clock signal; a data receiving unit configured to receive external data in synchronization with the data latch clock signal and output the received data as internal data; and a determination unit configured to detect a phase difference between the reference clock signal and the data latch clock signal and generate a determination signal, when the DLL is locked.Type: GrantFiled: March 18, 2013Date of Patent: February 24, 2015Assignee: SK Hynix Inc.Inventor: Young Jun Ku
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Publication number: 20150048870Abstract: A semiconductor device may include first to fourth output lines, an input signal latch unit suitable for latching first to fourth input signals that are sequentially inputted in response to first to fourth clocks having sequential phases, respectively, a valid signal latch unit suitable for latching a valid signal in response to one clock among the first to fourth clocks, where the valid signal corresponds to one input signal among the first to fourth input signals and represents whether the corresponding input signal is valid or not, and a signal transfer unit suitable for transferring the latched input signals, which are obtained by latching the input signals in response to the first to fourth clocks, to the first to fourth output lines based on a correspondence relationship that is decided based on a valid signal latch result of the valid signal latch unit.Type: ApplicationFiled: December 17, 2013Publication date: February 19, 2015Applicant: SK hynix Inc.Inventor: Young-Jun KU
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Publication number: 20150043289Abstract: A semiconductor memory device includes a pad configured to receive a first write data from outside of the semiconductor memory device, and a write circuit configured to generate a plurality of second write data which are to be written in memory cells of all banks to be tested in response to a test mode signal, data strobe signals, a write enable signal, and the first write data transferred through the pad.Type: ApplicationFiled: October 27, 2014Publication date: February 12, 2015Inventors: Young-Jun KU, Ki-Ho KIM
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Publication number: 20150023119Abstract: A semiconductor device includes a column command generation unit suitable for generating a column command delayed by a first delay time from a source command, in response to a first control signal and the source command, a bank address generation unit suitable for generating a bank address delayed by the first delay time from a bank source address, in response to the first control signal and the bank source address, a precharge command generation unit suitable for generating a precharge command delayed by a second delay time from the column command, in response to a second control signal and the column command, and a precharge bank address generation unit suitable for generating a precharge bank address delayed by the second delay time from the bank address, in response to the second control signal and the bank address.Type: ApplicationFiled: December 16, 2013Publication date: January 22, 2015Applicant: SK hynix Inc.Inventor: Young-Jun KU
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Patent number: 8922237Abstract: A semiconductor integrated circuit includes a plurality of semiconductor chips coupled to one another through vias, wherein a lowermost semiconductor chip of the plurality of semiconductor chips is configured to generate a first test pulse signal and transmit the first test pulse signal through the via, an uppermost semiconductor chip of the plurality of semiconductor chips is configured to generate a second test pulse signal while substantially maintaining a time difference with the first test pulse signal, and to transmit the second test pulse signal through the via, and the plurality of semiconductor chips are configured to generate test result signals for determining whether the vias are defective in response to the first test pulse signal and the second test pulse signal.Type: GrantFiled: September 5, 2012Date of Patent: December 30, 2014Assignee: SK Hynix Inc.Inventor: Young Jun Ku
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Patent number: 8897081Abstract: A semiconductor memory device includes a pad configured to receive a first write data from outside of the semiconductor memory device, and a write circuit configured to generate a plurality of second write data which are to be written in memory cells of all banks to be tested in response to a test mode signal, data strobe signals, a write enable signal, and the first write data transferred through the pad.Type: GrantFiled: December 12, 2013Date of Patent: November 25, 2014Assignee: SK Hynix Inc.Inventors: Young-Jun Ku, Ki-Ho Kim
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Publication number: 20140159789Abstract: A semiconductor apparatus includes: a clock receiving unit configured to receive an external clock signal and output the received clock signal as a reference clock signal; a delay locked loop (DLL) configured to delay the reference clock signal by a variable delay amount and generate a data latch clock signal; a data receiving unit configured to receive external data in synchronization with the data latch clock signal and output the received data as internal data; and a determination unit configured to detect a phase difference between the reference clock signal and the data latch clock signal and generate a determination signal, when the DLL is locked.Type: ApplicationFiled: March 18, 2013Publication date: June 12, 2014Applicant: SK HYNIX INC.Inventor: Young Jun KU
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Patent number: 8729940Abstract: A semiconductor device includes a delay line configured to delay a source clock by a delay equal to a first number of delay units in response to a delay control code and to generate a delayed source clock; a delay amount sensing unit configured to sense whether the delay amount of the delay line reaches a delay amount limit; a clock cycle measuring unit configured to measure the cycle of the source clock by counting a sampling clock in response to an output signal of the delay amount sensing unit, wherein a cycle of the sampling clock is equal to a second number of delay units; and a delay amount controlling unit configured to change the delay amount of the delay line in response to the measured cycle of the source clock as determined from an output signal of the clock cycle measuring unit.Type: GrantFiled: December 22, 2010Date of Patent: May 20, 2014Assignee: Hynix Semiconductor Inc.Inventor: Young-Jun Ku
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Publication number: 20140098620Abstract: A semiconductor memory device includes a read circuit configured to sequentially output a plurality of compressed data corresponding to all banks which are to be tested in response to a plurality of bank addresses and a read enable signal during a test mode and a pad configured to transfer the compressed data which are sequentially outputted from the read circuit to an outside of the semiconductor memory device.Type: ApplicationFiled: December 12, 2013Publication date: April 10, 2014Applicant: SK hynix Inc.Inventors: Young-Jun KU, Ki-Ho KIM
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Publication number: 20140063990Abstract: A multi-chip semiconductor apparatus includes a plurality of semiconductor chips which are electrically connected through a plurality of through-chip vias (TSVs) and stacked, wherein each of the semiconductor chips includes: a first data input/output line configured to transmit data for a first memory bank; a second data input/output line configured to transmit data for a second memory bank; and a data transmitting/receiving (TX/RX) unit configured to electrically connect any one of the first and second data input/output lines to a first TSV in response to selected memory bank information, during read and write operations for the corresponding semiconductor chip.Type: ApplicationFiled: December 19, 2012Publication date: March 6, 2014Applicant: SK HYNIX INC.Inventors: Young Jun KU, Tae Sik YUN
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Patent number: 8625363Abstract: A semiconductor memory device includes a read circuit configured to sequentially output a plurality of compressed data corresponding to all banks which are to be tested in response to a plurality of bank addresses and a read enable signal during a test mode and a pad configured to transfer the compressed data which are sequentially outputted from the read circuit to an outside of the semiconductor memory device.Type: GrantFiled: May 4, 2011Date of Patent: January 7, 2014Assignee: Hynix Semiconductor Inc.Inventors: Young-Jun Ku, Ki-Ho Kim
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Publication number: 20130207685Abstract: A semiconductor integrated circuit includes a plurality of semiconductor chips coupled to one another through vias, wherein a lowermost semiconductor chip of the plurality of semiconductor chips is configured to generate a first test pulse signal and transmit the first test pulse signal through the via, an uppermost semiconductor chip of the plurality of semiconductor chips is configured to generate a second test pulse signal while substantially maintaining a time difference with the first test pulse signal, and to transmit the second test pulse signal through the via, and the plurality of semiconductor chips are configured to generate test result signals for determining whether the vias are defective in response to the first test pulse signal and the second test pulse signal.Type: ApplicationFiled: September 5, 2012Publication date: August 15, 2013Applicant: SK HYNIX INC.Inventor: Young Jun KU
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Patent number: 8456931Abstract: A data transmission device in a semiconductor memory apparatus receives input data via a local data input/output line and output s the input data on a plurality of global data input/output lines. The data transmission device includes a write data generation block configured to receive the input data and test data and output one of input data and test data as write data in response to an activation of a test enable signal, and a loading block configured to apply the write data to one of the plurality of global data input/output lines in response to an enable signal.Type: GrantFiled: November 16, 2010Date of Patent: June 4, 2013Assignee: SK Hynix Inc.Inventor: Young Jun Ku
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Patent number: 8441831Abstract: A semiconductor integrated circuit includes a first semiconductor chip including a first output circuit which is enabled in a first operation mode and outputs a first output signal and a second output circuit which is enabled in a second operation mode and outputs a second output signal; a second semiconductor chip including a first input circuit which is enabled in the first operation mode and receives the first output signal and a second input circuit which is enabled in the second operation mode and receives the second output signal; and a common through chip via arranged to vertically penetrate through the semiconductor chip, be coupled with the first and second output circuits in one end and coupled with the first and second input circuits in the other end, and interface transfer of the first and second output signals which are enabled in different operation modes, including the first and second operation modes.Type: GrantFiled: September 9, 2010Date of Patent: May 14, 2013Assignee: Hynix Semiconductor Inc.Inventors: Young-Jun Ku, Tae-Sik Yun
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Patent number: 8411478Abstract: Various embodiments of a three-dimensional, stacked semiconductor integrated circuit are disclosed. In one exemplary embodiment, the circuit may include a master slice, a plurality of slave slices, and a plurality of through-silicon vias for connecting the master slice to the plurality of slave slices. At least one of the plurality of through-silicon vias may be configured to transmit an operation control signal from the master slice to the plurality of slave slices. The at least one of the plurality of through-silicon vias is configured to be shared by the plurality of slave slices.Type: GrantFiled: December 16, 2010Date of Patent: April 2, 2013Assignee: SK Hynix Inc.Inventors: Tae Sik Yun, Young Jun Ku
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Patent number: 8373478Abstract: A semiconductor device includes a first phase detector for detecting a phase of a second clock by comparing the phase of the second clock with the phase of the first clock, a second phase detector for detecting a phase of a clock obtained by delaying the second clock by a set delay amount, a third phase detector for detecting the phase of the second clock by delaying the first clock by the set delay amount, and a phase difference detection signal generator for setting a logic level of a phase difference detection signal corresponding to a phase difference between the first and second clocks detecting that the phase of the first or second clock is changed, and change the logic level of the phase difference detection signal.Type: GrantFiled: December 27, 2011Date of Patent: February 12, 2013Assignee: Hynix Semiconductor Inc.Inventor: Young-Jun Ku
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Patent number: 8339879Abstract: A repair circuit of a semiconductor apparatus includes a transmission control unit configured to generate first through nth (n is an integer equal to or greater than 2) control signals in response to a repair information signal, and enable all mth through nth control signals when the repair information signal indicating an mth (m is an integer equal to or greater than 1 and equal to or less than n) TSV is inputted; transmission units configured to allocate transmission paths for first through nth signals to first through nth TSVs and a repair TSV in response to the first through nth control signals; and receiving units configured to receive the signals transmitted from the first through nth TSVs and the repair TSV in response to the first through nth control signals.Type: GrantFiled: July 14, 2010Date of Patent: December 25, 2012Assignee: SK Hynix Inc.Inventors: Min Seok Choi, Young Jun Ku