Patents by Inventor Young Soo Ahn

Young Soo Ahn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8968470
    Abstract: Disclosed herein are a graphite crucible for electromagnetic induction-based silicon melting and an apparatus for silicon melting/refining using the same, which performs a melting operation by a combination of indirect melting and direct melting. The crucible is formed of a graphite material and includes a cylindrical body having an open upper part through which a silicon raw material is charged into the crucible, and an outer wall surrounded by an induction coil, wherein a plurality of slits are vertically formed through the outer wall and an inner wall of the crucible such that an electromagnetic force created by an electric current flowing in the induction coil acts toward an inner center of the crucible to prevent a silicon melt from contacting the inner wall of the crucible.
    Type: Grant
    Filed: September 28, 2009
    Date of Patent: March 3, 2015
    Assignee: Korea Institute of Energy Research
    Inventors: Bo Yun Jang, Young Soo Ahn, Joon Soo Kim, Sang Hyun Park, Dong Kook Kim, Gwon Jong Yu
  • Patent number: 8921182
    Abstract: A method for fabricating a nonvolatile memory device includes forming a stacked structure having a plurality of interlayer dielectric layers and a plurality of sacrificial layers wherein interlayer dielectric layers and sacrificial layers are alternately stacked over a substrate, forming a first hole exposing a part of the substrate by selectively etching the stacked structure, forming a first insulation layer in the first hole, forming a second hole exposing the part of the substrate by selectively etching the first insulation layer, and forming a channel layer in the second hole.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: December 30, 2014
    Assignee: SK Hynix Inc.
    Inventors: Sung-Wook Jung, Yun-Kyoung Lee, Young-Soo Ahn, Tae-Hwa Lee
  • Publication number: 20140349455
    Abstract: In a semiconductor memory device, a plurality of control gates is stacked in a first region and a second region of a substrate. A plurality of interlayer insulating layers is stacked in a portion of the second region of the substrate. Each interlayer insulating layer is formed at the same level as a corresponding one of the control gates. A plurality of sub-control gates is stacked in the first and second regions region of the substrate and interposed between the control gates and the interlayer insulating layers. A common node penetrates the interlayer insulating layers and the sub-control gates.
    Type: Application
    Filed: August 4, 2014
    Publication date: November 27, 2014
    Inventor: Young Soo AHN
  • Patent number: 8894893
    Abstract: A method of preparing transparent or nontransparent silica aerogel granules. The method includes forming a granular wet gel by spraying a silica sol into alcohol, the silica sol being prepared by mixing a water glass solution or an opacifier-containing water glass solution with an inorganic acid solution, forming a granular alcohol gel through gelation aging and solvent substitution of the granular wet gel in alcohol, hydrophobically modifying the surface of the granular alcohol gel using an organic silane compound, and drying the surface modified gel at ambient pressure or in a vacuum. The method may prepare silica aerogel granules in a short period of time through heat treatment at a relatively low temperature and at ambient pressure or in a vacuum, thereby ensuring excellent economic feasibility, continuity and reliability, suited for mass production.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: November 25, 2014
    Assignee: Korea Institute of Energy Research
    Inventors: Young-Soo Ahn, Jeong-gu Yeo, Churl-Hee Cho
  • Publication number: 20140342519
    Abstract: A three-dimensional (3-D) non-volatile memory device includes channel structures each including channel layers stacked over a substrate and extending in a first direction, wherein the channel layers include well regions, respectively, vertical gates located and spaced from each other between the channel structures, and a well pick-up line contacting on the well regions of the channel layers and extending in a second direction crossing the channel structures.
    Type: Application
    Filed: July 31, 2014
    Publication date: November 20, 2014
    Inventors: Yoo Hyun NOH, Jong Moo CHOI, Young Soo AHN
  • Patent number: 8871140
    Abstract: Disclosed herein is a method of manufacturing inorganic hollow yarns, such as cermets, oxide-non oxide composites, poorly sinterable non-oxides, and the like, at low costs. The method includes preparing a composition comprising a self-propagating high temperature reactant, a polymer and a dispersant, wet-spinning the composition through a spinneret to form wet-spun yarns, washing and drying the wet-spun yarns to form polymer-self propagating high temperature reactant hollow yarns, and heat-treating the polymer-self propagating high temperature reactant hollow yarns to remove a polymeric component from the polymer-self propagating high temperature reactant hollow yarns while inducing self-propagating high temperature reaction of the self-propagating high temperature reactant to form inorganic hollow yarns. The composition comprises 45˜60 wt % of the self-propagating high temperature reactant, 6˜17 wt % of the polymer, 0.1˜4 wt % of the dispersant, and the balance of an organic solvent.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: October 28, 2014
    Assignee: Korea Institute of Energy Research
    Inventors: Churl-Hee Cho, Do-Kyung Kim, Jeong-Gu Yeo, Young-Soo Ahn, Dong-Kook Kim, Hong-Soo Kim
  • Patent number: 8829599
    Abstract: In a semiconductor memory device, a plurality of control gates is stacked in a first region and a second region of a substrate. A plurality of interlayer insulating layers is stacked in a portion of the second region of the substrate. Each interlayer insulating layer is formed at the same level as a corresponding one of the control gates. A plurality of sub-control gates is stacked in the first and second regions region of the substrate and interposed between the control gates and the interlayer insulating layers. A common node penetrates the interlayer insulating layers and the sub-control gates.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: September 9, 2014
    Assignee: SK Hynix Inc.
    Inventor: Young Soo Ahn
  • Patent number: 8794035
    Abstract: Apparatus and method for manufacturing high purity polysilicon. The apparatus includes a vacuum chamber maintaining a vacuum atmosphere; first and second electron guns disposed at an upper side of the vacuum chamber to irradiate electron beams into the vacuum chamber; a silicon melting unit placed on a first electron beam-irradiating region corresponding to the first electron gun and in which powdery raw silicon is placed and melted by the first electron beam; and a unidirectional solidification unit placed on a second electron beam-irradiating region corresponding to the second electron gun and connected to the silicon melting unit via a runner. The unidirectional solidification unit is formed at a lower part thereof with a cooling channel and is provided therein with a start block driven in a downward direction.
    Type: Grant
    Filed: May 4, 2012
    Date of Patent: August 5, 2014
    Assignee: Korea Institute of Energy Research
    Inventors: Bo Yun Jang, Jin Seok Lee, Joon Soo Kim, Young Soo Ahn
  • Publication number: 20140160837
    Abstract: A resistive memory device Includes word lines stacked on top of one another, at least one first selection line formed over the word lines, a first channel layer passing through the word lines and the first selection line, a first phase change material layer formed in the first channel layer and overlapping the word lines, and a first insulating layer formed in the first channel layer and overlapping the first selection line.
    Type: Application
    Filed: March 16, 2013
    Publication date: June 12, 2014
    Applicant: SK hynix Inc.
    Inventor: Young Soo AHN
  • Patent number: 8735641
    Abstract: Disclosed is a method for selective dealkylation of alkyl-substituted C9+ aromatic compounds using a bimodal porous dealkylation catalyst at a low temperature. The catalyst has a bimodal porous structure including both mesopores and micropores. The catalyst includes a crystalline aluminosilicate and a metal. The catalyst is highly active at a low temperature. According to the method, C9+ aromatic compounds substituted with at least one C2+ alkyl group as by-products formed by xylene production can be selectively dealkylated and converted to BTX, etc. on a large scale within a short time. In addition, the method is an environmentally friendly process entailing reduced waste treatment cost when compared to conventional mesitylene production methods. Therefore, high value-added mesitylene can be separated from low value-added C9+ aromatic compounds at lower cost compared to conventional methods.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: May 27, 2014
    Assignees: S-Oil Corporation, Inha-Industry Partnership Institute
    Inventors: Sung Hyeon Baeck, Geon Joong Kim, Dong-Kyun Noh, Tae Young Jang, Tae-Yun Kim, Young Soo Ahn, Chan-ju Song, Sang-Cheol Paik
  • Patent number: 8687425
    Abstract: A nonvolatile memory device includes a plurality of channel structures formed over a substrate and including a plurality of interlayer dielectric layers alternately stacked with a plurality of channel layers; first and second vertical gates alternately disposed between the channel structures along one direction crossing with the channel structure and adjoining the plurality of channel layers with a memory layer interposed therebetween; and a pair of first and second word lines disposed over or under the channel structures and extending along the one direction in such a way as to overlap with the first and second vertical gates. The first word line is connected with the first vertical gates and the second word line is connected with the second vertical gates.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: April 1, 2014
    Assignee: SK Hynix Inc.
    Inventors: Young-Soo Ahn, Jong-Moo Choi, Yoo-Hyun Noh
  • Patent number: 8663739
    Abstract: The present invention relates to a method of manufacturing a mat containing aerogel and to a mat manufactured using this method. A method of manufacturing a mat containing silica aerogel according to an aspect of the invention includes: (S1) producing a wet gel by mixing water glass and alcohol in a reactor; (S2) modifying a surface of the wet gel by adding an organic silane compound and an organic solvent to the reactor and mixing; (S3) separating a upper liquid from a solution in the reactor and impregnating a fibrous matrix with the upper liquid; and (S4) drying the fibrous matrix impregnated with the upper liquid. According to an aspect of the invention, a mat containing silica aerogel can be manufactured using only water glass as raw material, even when applying the drying process in an ambient environment, without using expensive materials or supercritical apparatus.
    Type: Grant
    Filed: June 10, 2010
    Date of Patent: March 4, 2014
    Assignee: Korea Institute of Energy Research
    Inventors: Jeong-Gu Yeo, Young-Soo Ahn, Churl-Hee Cho, Jeong Min Hong
  • Patent number: 8659575
    Abstract: A capacitive touch panel device of a high-sensitivity digital system. The capacitive touch panel device includes a substrate, a display area formed at the center of the substrate, a non-active area formed along the outer periphery of the display area, extending to the end of the substrate, and mounted with a plurality of signal transmitting wire electrodes, two pairs of position sensing main sensor electrodes arranged in a two-dimensional fashion in the display area to display coordinates, a plurality of bridge electrodes interposed between the two pairs of position-sensing main sensor electrodes, an external terminal unit electrically connected to the ends of the plurality of signal transmitting wire electrodes, and a position sensing sub electrode electrically connected to each of the two pairs of position-sensing main sensor electrodes, and arranged in the direction different from the direction wherein the bridge electrodes are connected.
    Type: Grant
    Filed: July 2, 2009
    Date of Patent: February 25, 2014
    Assignee: Sanghyun Han
    Inventor: Young Soo Ahn
  • Publication number: 20130334589
    Abstract: In a semiconductor memory device, a plurality of control gates is stacked in a first region and a second region of a substrate. A plurality of interlayer insulating layers is stacked in a portion of the second region of the substrate. Each interlayer insulating layer is formed at the same level as a corresponding one of the control gates. A plurality of sub-control gates is stacked in the first and second regions region of the substrate and interposed between the control gates and the interlayer insulating layers. A common node penetrates the interlayer insulating layers and the sub-control gates.
    Type: Application
    Filed: December 10, 2012
    Publication date: December 19, 2013
    Applicant: SK Hynix Inc.
    Inventor: Young Soo AHN
  • Publication number: 20130307050
    Abstract: A nonvolatile memory device includes: a channel layer protruding perpendicular to a surface of a substrate; a tunnel insulation layer formed on a surface of the channel layer; a stack structure, in which a plurality of floating gate electrodes and a plurality of control gate electrodes are alternately formed along the channel layer; and a charge blocking layer interposed between each floating gate electrode, of the plurality of floating gate electrodes, and each control gate electrode of the plurality of control gate electrodes, wherein the floating gate electrode includes a first floating gate electrode between two control gate electrodes and a second floating gate electrode positioned in the lowermost and uppermost parts of the stack structure and having a smaller width in a direction parallel to the substrate than the first floating gate electrode.
    Type: Application
    Filed: September 10, 2012
    Publication date: November 21, 2013
    Inventors: Young-Soo AHN, Jeong-Seob OH
  • Publication number: 20130299121
    Abstract: The present disclosure relates to the preparation of a polymer composite material for building air conditioning or dehumidification having superior water-adsorbing ability, durability and antibacterial properties by electro spinning. Specifically, the disclosed method for preparing a polymer composite material for building air conditioning or dehumidification includes: (S1) adding a crosslinking agent or a crosslinking agent and a porous filler for conferring durability and antibacterial properties into a hydrophilic polymer solution antibacterial properties to prepare a polymer composite material solution; (S2) electrospinning the polymer composite material solution to prepare a nanofiber sheet; and (S3) crosslinking the nanofiber sheet by heat-treatment.
    Type: Application
    Filed: December 15, 2010
    Publication date: November 14, 2013
    Inventors: Young-soo Ahn, Jeong-gu Yeo, Kuck-tack Chue, Churl-hee Cho, Chang-kook Hong, Sang-youn Oh, Se-hee Kim, Hyeong-seon Oh, Jae-sik Ryu, Seung-hyun Shin
  • Publication number: 20130291596
    Abstract: Methods and apparatus for manufacturing high purity polysilicon. The apparatus includes a vacuum chamber; first and second electron guns disposed at an upper side of the vacuum chamber to irradiate electron beams into the vacuum chamber; a silicon melting unit which is placed on a first electron beam-irradiating region corresponding to the first electron gun and to which powdery raw silicon is fed and melted by the first electron beam; and a unidirectional solidification unit placed on a second electron beam-irradiating region corresponding to the second electron gun. The unidirectional solidification unit is provided therein with a start block driven in a downward direction to transfer molten silicon in the downward direction and is formed at a lower side thereof with a cooling channel. The start block includes a dummy bar having a silicon button joined to an upper portion of the dummy bar.
    Type: Application
    Filed: May 4, 2012
    Publication date: November 7, 2013
    Applicant: KOREA INSTITUTE OF ENERGY RESEARCH
    Inventors: Bo Yun Jang, Jin Seok Lee, Joon Soo Kim, Young Soo Ahn
  • Publication number: 20130291595
    Abstract: Apparatus and method for manufacturing high purity polysilicon. The apparatus includes a vacuum chamber maintaining a vacuum atmosphere; first and second electron guns disposed at an upper side of the vacuum chamber to irradiate electron beams into the vacuum chamber; a silicon melting unit placed on a first electron beam-irradiating region corresponding to the first electron gun and in which powdery raw silicon is placed and melted by the first electron beam; and a unidirectional solidification unit placed on a second electron beam-irradiating region corresponding to the second electron gun and connected to the silicon melting unit via a runner. The unidirectional solidification unit is formed at a lower part thereof with a cooling channel and is provided therein with a start block driven in a downward direction.
    Type: Application
    Filed: May 4, 2012
    Publication date: November 7, 2013
    Applicant: KOREA INSTITUTE OF ENERGY RESEARCH
    Inventors: Bo Yun Jang, Jin Seok Lee, Joon Soo Kim, Young Soo Ahn
  • Publication number: 20130277882
    Abstract: Disclosed herein is a method of manufacturing inorganic hollow yarns, such as cermets, oxide-non oxide composites, poorly sinterable non-oxides, and the like, at low costs. The method includes preparing a composition comprising a self-propagating high temperature reactant, a polymer and a dispersant, wet-spinning the composition through a spinneret to form wet-spun yarns, washing and drying the wet-spun yarns to form polymer-self propagating high temperature reactant hollow yarns, and heat-treating the polymer-self propagating high temperature reactant hollow yarns to remove a polymeric component from the polymer-self propagating high temperature reactant hollow yarns while inducing self-propagating high temperature reaction of the self-propagating high temperature reactant to form inorganic hollow yarns. The composition comprises 45˜60 wt % of the self-propagating high temperature reactant, 6˜17 wt % of the polymer, 0.1˜4 wt % of the dispersant, and the balance of an organic solvent.
    Type: Application
    Filed: June 18, 2013
    Publication date: October 24, 2013
    Inventors: CHURL-HEE CHO, Do-Kyung Kim, Jeong-Gu Yeo, Young-Soo Ahn, Dong-Kook Kim, Hong-Soo Kim
  • Publication number: 20130263777
    Abstract: There is disclosed an apparatus for manufacturing a silicon substrate including a crucible part, a molding part extended from an outlet of the crucible part, the molding part comprising a molding space where a silicon substrate is formed, and a dummy bar inserted in the molding space from a predetermined portion of the molding part, wherein the dummy bar is formed of a single-crystalline material.
    Type: Application
    Filed: April 28, 2012
    Publication date: October 10, 2013
    Applicant: KOREA INSTITUTE OF ENERGY RESEARCH
    Inventors: Jin Seok Lee, Bo Yun Jang, Joon Soo Kim, Young Soo Ahn