Abstract: A display panel and a display device are provided. The display panel includes a first substrate, a second substrate arranged opposite to the first substrate, an electrophoresis layer, a liquid-blocking portion and a supporting structure. The electrophoresis layer is arranged between the first substrate and the second substrate and includes multiple electrophoresis particles. The liquid-blocking portion is arranged at an edge of the first substrate and/or the second substrate. The supporting structure is arranged between the first substrate and the second substrate and includes a first supporting portion and a second supporting portion. A height of the first supporting portion is greater than that of the second supporting portion in a direction perpendicular to a plane where the first substrate is located. A minimum distance between the second supporting portion and the liquid-blocking portion is less than that between the first supporting portion and the liquid-blocking portion.

Abstract: The present disclosure provides a method for preparing lithium iron phosphate from ferric hydroxyphosphate, including: purifying ferrous sulfate to form a ferrous sulfate solution, adding hydrogen peroxide, phosphoric acid, an ammonium dihydrogen phosphate solution and ammonia water into the ferrous sulfate solution and then reacting to form a mixed slurry, holding the mixed slurry at a temperature for a period of time, and then washing with water and subjecting to press filtration to form ferric hydroxyphosphate precursors with different iron-phosphorus ratios; then flash drying, sintering at a high temperature, and pulverizing to obtain ferric hydroxyphosphate precursors with different iron-phosphorus ratios and different specific surface areas.

Abstract: The present application discloses a DQN-based distributed computing network coordinate flow scheduling system and method.

Abstract: Fin field effect transistor (FinFET) sense amplifier circuitry and related apparatuses and computing systems are disclosed. An apparatus includes a pull-up sense amplifier, a pull-down sense amplifier, column select gates, global input-output (GIO) lines, and GIO pre-charge circuitry. The pull-up sense amplifier includes P-type FinFETs having a first threshold voltage potential associated therewith. The pull-down sense amplifier includes N-type FinFETs having a second threshold voltage potential associated therewith. The second threshold voltage potential is substantially equal to the first threshold voltage potential. The GIO lines are electrically connected to the pull-up sense amplifier and the pull-down sense amplifier through the column select gates. The GIO pre-charge circuitry is configured to pre-charge the GIO lines to a low power supply voltage potential.

Abstract: Methods, systems, and devices for counter management for memory systems are described. A memory system may include circuitry configured to test localized counters of the memory system, where the circuitry may be configured to test a set of memory cells storing a value of the counter. During testing, the memory system may activate a row of memory cells a quantity of times, and the circuitry may increment a test counter associated with a subset of the set of memory cells for each activation to determine whether the subset is associated with an error. If a flag generated by the circuitry indicating a test count does not match an expected value, there may be an error associated with the subset. The circuitry may be operable to configure one or more multiplexers to refrain from using the subset to store the value of the counter based on the flag.

Abstract: A method for preparing isophorone diisocyanate by (1) reacting isophorone with hydrogen cyanide in the presence of a catalyst to obtain isophorone nitrile; (2) reacting the isophorone nitrile obtained in step (1) with ammonia gas and hydrogen in the presence of a catalyst to obtain isophorone diamine; and (3) subjecting the isophorone diamine to a phosgenation reaction to obtain the isophorone diisocyanate, wherein the content of impurities containing a secondary amine group in the isophorone diamine that undergoes the phosgenation reaction in step (3) is ?0.5 wt. The method reduces the content of hydrolyzed chlorine in the isophorone diisocyanate product, improves the yellowing resistance of the product, and the harm due to presence of hydrolyzed chlorine in the product is reduced.

Abstract: Methods, systems, and devices for testing operations for memory systems are described. A memory system may include a first circuit and a second circuit configured to test one or more counters tracking the quantity of activates to respective rows of memory cells. In some examples, the memory system may initiate an operation to validate a counter of the memory system. The first circuit may determine if a value of the counter is correct by comparing a set of counter bits representing the value of the counter to a set of parity bits. Subsequently, the second circuit may determine if the counter is incrementing correctly in accordance with a set quantity of activates to the corresponding row of memory cells. If the first circuit or the second circuit detect an error associated with the counter, the memory system may discard the row of memory cells associated with the faulty counter.

Abstract: Methods, systems, and devices for counter management for memory systems are described. A memory system may include circuitry configured to test localized counters of the memory system, where the circuitry may be configured to test a set of memory cells storing a value of the counter. During testing, the memory system may activate a row of memory cells a quantity of times, and the circuitry may increment a test counter associated with a subset of the set of memory cells for each activation to determine whether the subset is associated with an error. If a flag generated by the circuitry indicating a test count does not match an expected value, there may be an error associated with the subset. The circuitry may be operable to configure one or more multiplexers to refrain from using the subset to store the value of the counter based on the flag.

Abstract: Information output methods and apparatuses, computer equipment and readable storage media which relate to the field of computer technology are provided. The information output method includes: detecting whether a search connection is established between a delivery terminal and a beacon device deployed by a target physical object by using a pre-cached joint beacon atlas bound to the target physical object, where the joint beacon atlas records a set of communication identifiers covered by a physical object; if the search connection is established between the delivery terminal and the beacon device deployed by the target physical object, outputting a corresponding time point when the search connection is in a stable state as information of a delivery resource arriving at the target physical object.

Abstract: There is provided a display substrate, including: a base; light-emitting units on a side of the base; a flat light-shielding functional layer, including a black matrix and a first planarization layer, on a side of the light-emitting units away from the base, light outgoing openings being provided in the black matrix and being in one-to-one correspondence with the light-emitting units, and the first planarization layer at least filling the light outgoing openings; and a color filter layer, including color filter patterns in one-to-one correspondence with the light outgoing openings, on a side of the flat light-shielding functional layer away from the base, an orthographic projection of each color filter pattern on the base covering an orthographic projection of the light outgoing opening corresponding to the color filter pattern on the base. A method for manufacturing a display substrate, a display panel and a display apparatus are further provided.

Abstract: The present application relates to a method and apparatus of power distribution control for power module and a power module device. The method includes: obtaining temperature data of target devices in two or more power modules; analyzing whether the power modules are operating at full power when the temperature data of the target devices meets a preset temperature fault condition; and adjusting operating parameters of the power modules based on the temperature data when the power modules are not operating at full power.

Abstract: Methods, systems, and devices for non-destructive pattern identification at a memory device are described. A memory device may perform pattern identification within the memory device and output a flag indicating whether a first data pattern matches with a second data pattern. The memory device may access one or more memory cells, via a word line, and latch the second data pattern of the memory cells to a sense amplifier. The memory device may deactivate the word line, which may result in isolating the memory cells from potential destruction of data. The memory device may write a first data pattern to the sense amplifier and compare the first data pattern and second data pattern at the sense amplifier. The memory device may output a signal indicating whether the data patterns match.

Abstract: Some embodiments include an integrated assembly having a memory array over a base. First sense-amplifier-circuitry is associated with the base and includes sense amplifiers directly under the memory array. Vertically-extending digit lines are associated with the memory array and are coupled with the first sense-amplifier-circuitry. Second sense-amplifier-circuitry is associated with the base and is offset from the first sense-amplifier-circuitry. Control circuitry is configured to selectively couple the digit lines to either a voltage supply terminal or to the second sense-amplifier-circuitry.

Abstract: A temperature control system and method for devices under test and an image sensor-testing apparatus having the system are provided. The temperature control method for devices under test mainly comprises the steps of regulating the temperatures of a plurality of devices under test (DUTs) to a specific temperature in a temperature control zone; transferring the plurality of devices under test to a test plate and placing them into a plurality of test slots respectively; and measuring the temperatures of the device under test by the temperature-sensing elements in the test slots, wherein when at least one temperature-sensing element of the temperature-sensing elements detects that the device under test in the test slot corresponding to said at least one temperature-sensing element fails to meet the specific temperature, a temperature control element corresponding to the test slot regulates the temperature of the device under test.

Abstract: A system and method for video compression divides colors of all pixel points of a target video frame into R, G, and B values, and all pixels are placed in a three-dimensional coordinate system to establish a correspondence between each pixel point and the coordinate position. Fuzzy recombination and division are performed on all pixel blocks and pixel points with similar RGB values are divided into pixel blocks to obtain a first target pixel block. Pixel blocks with same RGB values but with coordinates which are not close to the first target pixel block are extracted and divided to obtain a second target pixel block. An area enveloping the second target pixel block is extracted, and vector changes of all dynamic pixel points on the enveloping line are traversed and analyzed to determine a minimum compression change block for compression process.

Abstract: An energy storage apparatus is provided. The energy storage apparatus includes: a support structure, which is provided with at least one support layer in a height direction of the support structure; an energy storage device, an air outlet is defined at the top of the energy storage device, and an air inlet is defined on a sidewall of the energy storage device, where the number of the energy storage device is at least two, the energy storage devices are arranged in at least two layers through the support layer, and the support layer between adjacent layers of energy storage devices is hollowed out or configured in a partitioning manner; and an air guide structure mounted on the energy storage device and in communication with an air inlet of the energy storage device.

Abstract: A microelectronic device is disclosed that incudes array regions individually comprising memory cells comprising access devices and storage node devices; digit lines coupled to the access devices that extend in a first direction; and word lines coupled to the access devices that extend in a second direction orthogonal to the first direction. Digit line exit regions horizontally alternate with the array regions in the first direction; sense amplifier sections comprising sense amplifier circuitry vertically overlie and horizontally overlapping the digit line exit regions; and routing structures within horizontal areas of the digit line exit regions, couple the sense amplifier circuitry of the sense amplifier sections to the digit lines.

Abstract: A microelectronic device comprises a first microelectronic device structure comprising a stack structure comprising conductive structures vertically alternating with insulative structures, a staircase structure within the stack structure, and vertical stacks of memory cells. Each vertical stack of memory cells individually comprises a vertical stack of capacitor structures, transistor structures each individually neighboring a capacitor structure of the capacitor structures, and a conductive pillar structure vertically extending through the transistor structures.

Abstract: Methods, systems, and devices for sensing a memory with shared sense components are described. A device may activate a word line and a plate line each coupled with a set of memory cells, where each memory cell of the set of memory cells is coupled with a respective digit line of a set of digit lines. The device may activate a set of switching components to couple each digit line of the set of digit lines with a respective sense component of a set of sense components, where each switching component of the set of switching components is coupled with a respective memory cell of the set of memory cells. The device may sense the set of memory cells based on activating the word line and the plate line and based on coupling the set of digit lines with the set of sense components.

Abstract: In some examples, a system may include a plurality of memory blocks, a first data bus coupled to the plurality of memory blocks in a memory device, a second data bus coupled to the plurality of memory blocks, a controller configured to perform memory read and write operations on the plurality of memory blocks via the first data bus, and a non-volatile storage (NVS) data transfer circuit configured to transfer data in a first memory block of the plurality of memory blocks to a NVS device via the second data bus. The first memory block may be a cold data block least accessed among the plurality of memory blocks. The cold data transfer may be performed via the second data bus when a different memory block is being accessed via the first data bus concurrently. The second data bus may be a fuse bus in the memory device.