Abstract: Apparatuses and methods for row hammer counter mat. A memory array may have a number of memory mats and a counter memory mat. The counter mat stores count values, each of which is associated with a row in one of the other memory mats. When a row is accessed, the count value is read out, changed, and written back to the counter mat. In some embodiments, the count value may be processed within access logic of the counter mat, and a row hammer flag may be provided to the bank logic. In some embodiments, the counter mat may have a folded architecture where each sense amplifier is coupled to multiple bit lines in the counter mat. The count value may be used to determine if the accessed row is an aggressor so that its victims can be refreshed as part of a targeted refresh.

Abstract: Apparatuses including a level shifter circuit are disclosed. An example apparatus according to the disclosure includes a plurality of array access control circuits and a level shifter circuit. The plurality of array access control circuits receive an access control signal and a respective plurality of section enable signals. An array access control circuit of the plurality of array access control circuits provides a section access control signal responsive to the access control signal when a respective section enable signal is in an active state. The level shifter circuit receives a control signal and provides an access control signal responsive to the first signal. A first logic level of the control signal is represented by a first power supply voltage and a first logic level of the access control signal is represented by a second power supply voltage greater than the first power supply voltage.

Abstract: Multi-level cells, and related methods, arrays, devices, and systems, are described. A device may include a memory array including a first reference section including a first number of memory cells and a first reference digit line. The memory array may also include a second reference section including a second number of memory cells and a second reference digit line. The memory array may also include a target section including a memory cell. The target section may further include a first digit line coupled to the memory cell via a first switch, wherein the first digit line is further coupled to the first reference digit line via a first sense amplifier. The target section may also include a second digit line coupled to the first digit line via a second switch, wherein the second digit line is further coupled to the second reference digit line via a second sense amplifier.

Abstract: An artificial intelligence (AI) technique to process and query data pertaining to an enterprise. A user raises a request which is processed to predict a knowledge context area based on a predetermined structure of the enterprise. The knowledge context area is predicted from multiple knowledge context areas, on the basis of the received user request and a conversation history of the user in past. Further, a knowledge database is selected from multiple knowledge databases based on the user request and the predicted knowledge context. The knowledge databases include preprocessed data from multiple data sources. The knowledge database is queried on the basis of the user request related to the knowledge context to obtain a result and the result is then displayed as an output.

Abstract: A system and method for video compression divides colors of all pixel points of a target video frame into R, G, and B values, and all pixels are placed in a three-dimensional coordinate system to establish a correspondence between each pixel point and the coordinate position. Fuzzy recombination and division are performed on all pixel blocks and pixel points with similar RGB values are divided into pixel blocks to obtain a first target pixel block. Pixel blocks with same RGB values but with coordinates which are not close to the first target pixel block are extracted and divided to obtain a second target pixel block. An area enveloping the second target pixel block is extracted, and vector changes of all dynamic pixel points on the enveloping line are traversed and analyzed to determine a minimum compression change block for compression process.

Abstract: Apparatuses and techniques for implementing aspects of proactive usage-based disturbance mitigation based on resource availability are described. In an example aspect, usage-based disturbance circuitry of a memory device performs usage-based disturbance mitigation based on multiple criteria. A primary criterion is associated with normal usage-based disturbance mitigation and can enable the memory device to balance power consumption with usage-based disturbance mitigation. At least one secondary criterion is less strict compared to the primary criterion. While a resource is available, the usage-based disturbance circuitry can proactively mitigate usage-based disturbance based on activated rows that satisfy the secondary criterion but don't yet satisfy the primary criterion. With these preemptive measures, the usage-based disturbance circuitry can reduce a probability of a waterfall event causing a denial-of-service (DOS) situation while the resource is available.

Abstract: Apparatuses and techniques for implementing aspects of a time-varying threshold for usage-based disturbance mitigation. In an example aspect, usage-based disturbance circuitry of a memory device utilizes a threshold that varies over time for detecting conditions associated with usage-based disturbance. By utilizing the time-varying threshold, the usage-based disturbance circuitry can reduce a probability of a waterfall event causing a denial-of-service (DOS) situation. In particular, the time-varying threshold can spread out the refreshing of rows over a longer time period. This enables the memory device to have sufficient resources to service other memory requests while also mitigating usage-based disturbance. In example implementations, the threshold is at least partially randomized, which can make it challenging for a malicious actor to identify and overcome the usage-based disturbance mitigation techniques.

Abstract: Apparatuses and techniques for implementing usage-based disturbance mitigation counter control are described. In some examples, a mitigation counter controller manages mitigation of usage-based disturbances by mitigating one or more wordlines in a memory device that have been disturbed. The mitigation counter controller may access a usage-based disturbance counter by activating a single sub wordline driver in the wordline, where the usage-based disturbance counter is associated with usage-based disturbances of the wordline. Activation of a single sub wordline driver to access the usage-based disturbance counter may reduce power consumption and may simplify the design of the memory device.

Abstract: Apparatuses and techniques for implementing bank-shared usage-based disturbance circuitry are described. Bank-shared usage-based disturbance circuitry is coupled to the at least two banks of a memory device and can mitigate usage-based disturbance within these banks. To detect a condition associated with usage-based disturbance, the bank-shared usage-based disturbance circuitry selectively reads data associated with usage-based disturbance from one of the at least two banks. To mitigate usage-based disturbance, the bank-shared usage-based disturbance circuitry can selectively cause one or more rows within either of the at least two banks to be refreshed. By using the same circuitry to mitigate usage-based disturbance across multiple banks, the total footprint, complexity, and power consumption of the memory device can be reduced relative to other memory devices that utilize circuitry that is dedicated for each bank.

Abstract: A microelectronic device comprises array regions individually comprising memory cells comprising access devices and storage node device, digit lines coupled to the access devices and extending in a first direction, word lines coupled to the access devices and extending in a second direction orthogonal to the first direction, and control logic devices over and in electrical communication with the memory cells. The microelectronic device further comprises capacitor regions horizontally offset from the array regions in the first direction and having a dimension in the second direction greater than each individual array region in the second direction. The capacitor regions individually comprise additional control logic devices vertically overlying the memory cells, and capacitor structures within horizontal boundaries of the additional control logic devices. Related microelectronic devices, electronic systems, and methods are also described.

Abstract: Methods, systems, and apparatus are provided for generating an image. A personalized text prompt is generated by processing an input embedding using a transformer model followed by a first fully connected neural network. The input embedding comprises a multi-dimensional embedding vector associated with a user profile and a plurality of user items. A scored label set is generated identifying a user's preferences by processing a set of attributes for the plurality of user items using a second fully connected neural network. The image is generated by processing the personalized text prompt and the scored label set using a diffusion model.

Abstract: Apparatuses and techniques for implementing usage-based disturbance (UBD) counter repair are described. In example implementations, a memory device includes multiple memory rows, multiple corresponding UBD counters, a register, and a spare UBD counter. If a UBD counter is faulty, logic can substitute the spare UBD counter. To do so, the logic can store a row address corresponding to the faulty UBD counter in the register. The logic can increment a value in the spare UBD counter responsive to a row activation corresponding to the stored row address. A mitigation procedure on a row that may be affected by the activation can be performed based on the value. A host device can control, at least partially, the UBD counter repair process. In these manners, a repair of a faulty UBD counter can be accomplished faster and/or with fewer resources as compared to replacing a memory row and corresponding UBD counter.

Abstract: A bandwidth configuration method and a related device are disclosed. An electronic device first determines bandwidth configuration schemes of N AP groups, and then adjusts the bandwidth configuration scheme of the AP group based on a physical topology similarity between the AP groups. When physical topologies of two AP groups are similar, if bandwidths of two APs at corresponding physical locations in the two AP groups are different, the electronic device determines a larger value of the bandwidths of the two APs as the bandwidths of the two APs.

Abstract: A value associated with a number of accesses of a word line and a length of said accesses may be stored on said word line. A timer may provide a periodic signal that increments a counter to update the value. The updated value may then be written back to the word line. In some examples, a memory device including the word lines may have a specification that prevents the word line from closing prior to writing the updated value to the word line.

Abstract: Apparatuses, systems, and methods for access based targeted refresh operations. A memory bank has a first sub-bank and a second sub-bank. A refresh control circuit detects an aggressor in one of the sub-banks. Responsive to an access in the other sub-bank, the refresh control circuit performs a targeted refresh operation based on the sub-bank based on the aggressor address.

Abstract: Methods, systems, and devices for vertical transistor fuse latches are described. An apparatus may include a substrate and a memory array that is coupled with the substrate. The apparatus may also include a latch that is configured to store information from a fuse for the memory array. The latch may be at least partially within an additional substrate separate from and above the substrate. The latch may include a quantity of p-type vertical transistors and a quantity of n-type vertical transistors each at least partially disposed within the additional substrate above the substrate.

Abstract: An exemplary register circuit includes a plurality of slots to store respective addresses and data pairs. During a write operation, each slot of a plurality of slots preceding a particular slot of the plurality of slots indicated as empty is shifted by one slot to fill the particular slot such that a first end slot of the plurality of slots is made available to receive a new write address and data pair. Each slot of the plurality of slots subsequent to the particular slot retains existing address and data pairs.

Abstract: A power configuration method is disclosed, which pertains to the field of communication technologies. In the power configuration method, a power configuration of an AP is determined based on signal quality data of a STA, to ensure coverage experience of the AP. Real coverage experience of the AP may be further obtained based on the signal quality data of the STA, to further optimize the power configuration of the AP.

Abstract: Apparatuses, systems, and methods for accurate bias temperature instability (BTI) mitigation. During a first period a signal is provided to a path of a device, and during a second period a BTI toggle signal is provided to the path. During the first period a ratio of the time that the signal is active or inactive is measured. During the second period the BTI toggle signal is provided with a duty cycle based on the measured ratio. The duty cycle may be higher if the measured ratio is lower and lower if the measured ratio was higher.

Abstract: Sense amplifiers for memory devices may include threshold voltage compensation circuitry configured to compensate a threshold voltage offset of a portion of the sense amplifier. Additionally, the sense amplifiers also perform pre-sensing of the portion of the sense amplifier. Moreover, the sense amplifier is configured to perform main sensing and latching in a phase after pre-sensing the portion of the sense amplifier.