Patents by Inventor Yuan He
Yuan He has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240282370Abstract: Memory devices including tri-state memory cells are disclosed. A memory device may include a first tri-state cell that may store a first voltage level that is one of three voltage levels, a second tri-state cell that may store a second voltage level that is one of the three voltage levels, and three input/output lines that may access the memory device. The three input/output lines may carry three respective binary signals based on the first voltage level and the second voltage level. A memory device may include a bank including a number of continuous arrays of tri-state memory cells. Each of the tri-state memory cells may be accessible by a respective bit line. Groups of the bit lines may be associated with respective column-select lines. The bank may include a number of sub-word-line drivers interspersed between the number of continuous arrays. Associated systems and methods are also disclosed.Type: ApplicationFiled: December 21, 2023Publication date: August 22, 2024Inventors: Jiyun Li, Yuan He
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Patent number: 12067257Abstract: Methods, systems, and devices for testing operations for memory systems are described. A memory system may include a first circuit and a second circuit configured to test one or more counters tracking the quantity of activates to respective rows of memory cells. In some examples, the memory system may initiate an operation to validate a counter of the memory system. The first circuit may determine if a value of the counter is correct by comparing a set of counter bits representing the value of the counter to a set of parity bits. Subsequently, the second circuit may determine if the counter is incrementing correctly in accordance with a set quantity of activates to the corresponding row of memory cells. If the first circuit or the second circuit detect an error associated with the counter, the memory system may discard the row of memory cells associated with the faulty counter.Type: GrantFiled: September 21, 2022Date of Patent: August 20, 2024Assignee: Micron Technology, Inc.Inventors: Yuan He, Sujeet V. Ayyapureddi
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Publication number: 20240274180Abstract: Methods, systems, and devices for sensing a memory with shared sense components are described. A device may activate a word line and a plate line each coupled with a set of memory cells, where each memory cell of the set of memory cells is coupled with a respective digit line of a set of digit lines. The device may activate a set of switching components to couple each digit line of the set of digit lines with a respective sense component of a set of sense components, where each switching component of the set of switching components is coupled with a respective memory cell of the set of memory cells. The device may sense the set of memory cells based on activating the word line and the plate line and based on coupling the set of digit lines with the set of sense components.Type: ApplicationFiled: February 19, 2024Publication date: August 15, 2024Inventors: Yuan He, Tae H. Kim, Scott James Derner
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Publication number: 20240260431Abstract: A display substrate and a display device are provided in the present invention. The display substrate includes: a base substrate; a black matrix, located above the base substrate, the black matrix including a plurality of first openings, each first opening including a first portion and a second portion, and the first portion being provided around the second portion; a pixel defining layer, located between the layer where the black matrix is located and the base substrate, the pixel defining layer including a plurality of second openings, an orthographic projection of the second opening on the base substrate overlapping with an orthographic projection of the second portion on the base substrate, and the orthographic projection of the second opening on the base substrate not overlapping with an orthographic projection of the first portion on the base substrate.Type: ApplicationFiled: October 25, 2021Publication date: August 1, 2024Inventors: Peng HOU, Yuan HE, Yunhao WANG
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Publication number: 20240244932Abstract: The present application provides display substrates and their manufacturing methods, and display devices. A display substrate includes a base substrate, an encapsulation layer, a filter layer and optical film layers. The encapsulation layer is located on the base substrate. The filter layer is located in the encapsulation layer. The filter layer includes black matrixes. The black matrixes include black matrix openings. The optical film layers are located on a side of the encapsulation layer away from the base substrate. The optical film layers are configured to transmit part of incident light and absorb part of the incident light. A light transmittance of the optical film layers is larger than that of the black matrixes. The optical film layers include optical film layer openings. Projections of the optical film layer openings on the base substrate are located within projections of the black matrix openings on the base substrate.Type: ApplicationFiled: May 19, 2021Publication date: July 18, 2024Inventors: Yunhao WANG, Peng HOU, Yongzhan HAN, Yuan HE, Can HUANG, Zhen LI, Yulin WANG, Jiandong BAO, Pengcheng ZHAO, Yide DU
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Publication number: 20240227600Abstract: A charging system includes n first charging modules, a first switch matrix, a second switch matrix, and m first output apparatuses. Each first charging module includes a plurality of first power converters, each first power converter has one output bus, the output bus of the first power converter is connected to the first switch matrix. The first switch matrix is configured to connect or disconnect output buses of any two of the plurality of first power converters. The first output apparatus j is connected to a corresponding first charging module by using the second switch matrix. The second switch matrix is configured to transmit, to the first output apparatus j, electric energy on an output bus of a first power converter in any first charging module corresponding to the first output apparatus j.Type: ApplicationFiled: March 21, 2024Publication date: July 11, 2024Applicant: Huawei Digital Power Technologies Co., Ltd.Inventors: Ziming DENG, Zezhou YANG, Yuanning HE, Zhanlin REN, Wei GUO, Wanxiang YE
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Publication number: 20240212738Abstract: Apparatuses and methods increased reliability row hammer counts. Each word line of a memory may have an associated count value, stored in memory cells of the word line. Information in memory cells may be prone to change, such as from neutron strike. A counter circuit may decrease the count value each time the word line is accessed, since a decreasing count will tend to overestimate accesses due to error. A count error correction circuit may check the count value against redundant information and correct the count value if there is an error. Decreasing counts and count error correction may be used together to further increase reliability.Type: ApplicationFiled: October 4, 2023Publication date: June 27, 2024Applicant: MICRON TECHNOLOGY, INC.Inventors: Hiroshi Akamatsu, Yuan He
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Patent number: 12018929Abstract: A non-contact key tooth profile learning method and system are provided. The non-contact key tooth profile learning method comprises the following steps: acquiring first profile point cloud data of a key by means of a line laser method; and processing the first profile point cloud data so as to obtain first 3D profile information.Type: GrantFiled: June 30, 2020Date of Patent: June 25, 2024Assignee: SHENZHEN XHORSE ELECTRONICS CO., LTDInventors: Yongfeng Xi, Yuan He, Yijie Hao, Guozhong Cao, Chenglong Li, Hui Liu
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Electric border gateway device and method for chaining and storage of sensing data based on the same
Patent number: 12010251Abstract: The present disclosure discloses an electric border gateway device which adopts the blockchain technology to implement communication authentication and data transmission encryption at the gateway. As a device for sinking and processing local information, the border gateway device may build not only a local blockchain network with a variety of local electric sensing terminal devices, but also a regional blockchain network with other border gateways and electric management platforms. As a critical node of these two types of blockchain, the border gateway may enable the authentication of identity legality between electric sensing terminal devices, the critical data storage in the blockchain ledger, the deployment and implementation of blockchain transaction by control and coordinated functions, and the safe and reliable data interaction. The present disclosure also discloses a method for chaining and storage of sensing data based on the electric border gateway device.Type: GrantFiled: December 18, 2020Date of Patent: June 11, 2024Assignee: Jiangsu Zhirong Energy Technology Co., Ltd.Inventors: Yuan He, Hui Liu, Yan Wang, Yao Sun -
Patent number: 12010831Abstract: Some embodiments include an integrated assembly having a memory array over a base. The memory array includes a three-dimensional arrangement of memory cells. Sense amplifiers are associated with the base and are directly under the memory array. Vertically-extending digit lines pass through the arrangement of the memory cells and are coupled with the sense amplifiers. Some embodiments include an integrated assembly having a memory bank containing 64 memory chunks arranged in a 16×4 configuration. Some embodiments include an integrated assembly having a memory bank which contains 512 megabytes divided amongst 64 memory chunks which each have 8 megabytes. The 64 memory chunks are arranged in a configuration having multiple rows which each contain a two or more of the memory chunks.Type: GrantFiled: January 5, 2021Date of Patent: June 11, 2024Assignee: Micron Technology, Inc.Inventors: Yuan He, Jiyun Li
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Publication number: 20240185832Abstract: The present disclosure relates to systems, methods, and products for using machine-learning networks to generate trustworthy audio and face mesh. A system, serving as a digital avatar, generates a trust audio and trust face mesh corresponding to an input text. A method includes generating a set of trust embedding vectors based on a reference audio; generate a text embedding vector based on the input text; generate a conditioned vector based on the set of trust embedding vectors and the text embedding vector; synthesize an audio representation based on the conditioned vector; generate the trust audio based on the synthesized audio representation; obtain a speech feature representation based on the trust audio; obtain an abstract feature vector based on the speech feature representation; and generate positions of vertices based on the abstract feature vector, the positions of vertices being used for generating the trust face mesh.Type: ApplicationFiled: December 5, 2022Publication date: June 6, 2024Inventors: Lan GUAN, Neeraj D. VADHAN, Sukryool KANG, Anwitha PARUCHURI, Anupam Anurag TRIPATHI, Sujeong CHA, Thomas Wayne HANCOCK, Jill GENGELBACH-WYLIE, Yuan HE, Andrew Francis HICKL, Ivan WONG, Surya Raghavendra VADLAMANI
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Publication number: 20240173270Abstract: Disclosed are a pharmaceutical composition containing ethanol and a use thereof. The pharmaceutical composition can be used in vivo for animals, and is prepared from the following raw material: ethanol having a concentration no lower than 50% and a liquid ethanol thickener. The pharmaceutical composition containing ethanol provided in the present invention has high developability and sufficient fluidity without toxic side effect on normal tissues. The present invention does not solidify in blood and can break endothelial cells or mucous membrane superficial tissues so as to allow for permanent embolization.Type: ApplicationFiled: September 4, 2023Publication date: May 30, 2024Applicant: SUZHOU YIBEN LIFE TECHNOLOGY CO., LTDInventors: Yonghua DONG, Yuan HE, Liangliang ZHAO, Miaoxia LI
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Publication number: 20240177745Abstract: Apparatuses and techniques for implementing shareable usage-based disturbance circuitry are described. Shareable usage-based disturbance circuitry includes circuits (e.g., shared circuits) that manage usage-based disturbance across at least two sections of a bank of memory within a die of a memory device. In example implementations, the shareable usage-based disturbance circuitry includes a counter circuit and/or an error-correction-code circuit that is coupled to sense amplifiers associated with two neighboring sections. With the shareable usage-based disturbance circuitry, dies within the memory device can be cheaper to manufacture, can consume less power, and can have a smaller footprint with less complex signal routing compared to other dies with other circuits dedicated to mitigating usage-based disturbance within each section.Type: ApplicationFiled: November 27, 2023Publication date: May 30, 2024Applicant: Micron Technology, Inc.Inventors: Yang Lu, Yuan He, Kang-Yong Kim
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Publication number: 20240170427Abstract: A microelectronic device comprises a first microelectronic device structure comprising a stack structure comprising conductive structures vertically alternating with insulative structures, a staircase structure within the stack structure, and vertical stacks of memory cells. Each vertical stack of memory cells individually comprises a vertical stack of capacitor structures, transistor structures each individually neighboring a capacitor structure of the capacitor structures, and a conductive pillar structure vertically extending through the transistor structures.Type: ApplicationFiled: January 31, 2024Publication date: May 23, 2024Inventors: Fatma Arzum Simsek-Ege, Yuan He
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Publication number: 20240166067Abstract: A charging system may include a plurality of power modules, a distributing switch module, and a plurality of charging ports. The distributing switch module includes a first distributing unit and a second distributing unit. The first distributing unit may connect a first part of power modules in the plurality of power modules to a first charging port, to distribute powers of the first part of power modules to the first charging port. The second distributing unit may connect a second part of power modules in the plurality of power modules to a second charging port, to distribute powers of the second part of power modules to the second charging port. Therefore, the first charging port may charge a first terminal, and the second charging port may charge a second terminal.Type: ApplicationFiled: February 2, 2024Publication date: May 23, 2024Inventors: Yuanning HE, Ping KUANG, Liqiong YI, Xinru HAN, Yichang WANG, Quanxi LIN
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Publication number: 20240161812Abstract: Some embodiments include an integrated assembly having a memory array over a base. First sense-amplifier-circuitry is associated with the base and includes sense amplifiers directly under the memory array. Vertically-extending digit lines are associated with the memory array and are coupled with the first sense-amplifier-circuitry. Second sense-amplifier-circuitry is associated with the base and is offset from the first sense-amplifier-circuitry. Control circuitry is configured to selectively couple the digit lines to either a voltage supply terminal or to the second sense-amplifier-circuitry.Type: ApplicationFiled: January 17, 2024Publication date: May 16, 2024Applicant: Micron Technology, Inc.Inventors: Yuan He, Beau D. Barry
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Publication number: 20240155107Abstract: A system and method for video compression divides colors of all pixel points of a target video frame into R, G, and B values, and all pixels are placed in a three-dimensional coordinate system to establish a correspondence between each pixel point and the coordinate position. Fuzzy recombination and division are performed on all pixel blocks and pixel points with similar RGB values are divided into pixel blocks to obtain a first target pixel block. Pixel blocks with same RGB values but with coordinates which are not close to the first target pixel block are extracted and divided to obtain a second target pixel block. An area enveloping the second target pixel block is extracted, and vector changes of all dynamic pixel points on the enveloping line are traversed and analyzed to determine a minimum compression change block for compression process.Type: ApplicationFiled: January 5, 2024Publication date: May 9, 2024Inventors: Qian LU, Hai-Yuan HE
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Publication number: 20240112724Abstract: Fin field effect transistor (FinFET) sense amplifier circuitry and related apparatuses and computing systems are disclosed. An apparatus includes a pull-up sense amplifier, a pull-down sense amplifier, column select gates, global input-output (GIO) lines, and GIO pre-charge circuitry. The pull-up sense amplifier includes P-type FinFETs having a first threshold voltage potential associated therewith. The pull-down sense amplifier includes N-type FinFETs having a second threshold voltage potential associated therewith. The second threshold voltage potential is substantially equal to the first threshold voltage potential. The GIO lines are electrically connected to the pull-up sense amplifier and the pull-down sense amplifier through the column select gates. The GIO pre-charge circuitry is configured to pre-charge the GIO lines to a low power supply voltage potential.Type: ApplicationFiled: September 29, 2022Publication date: April 4, 2024Inventors: Yuan He, Fatma Arzum Simsek-Ege
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Patent number: 11948656Abstract: Methods, systems, and devices for counter management for memory systems are described. A memory system may include circuitry configured to test localized counters of the memory system, where the circuitry may be configured to test a set of memory cells storing a value of the counter. During testing, the memory system may activate a row of memory cells a quantity of times, and the circuitry may increment a test counter associated with a subset of the set of memory cells for each activation to determine whether the subset is associated with an error. If a flag generated by the circuitry indicating a test count does not match an expected value, there may be an error associated with the subset. The circuitry may be operable to configure one or more multiplexers to refrain from using the subset to store the value of the counter based on the flag.Type: GrantFiled: September 21, 2022Date of Patent: April 2, 2024Assignee: Micron Technology, Inc.Inventor: Yuan He
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Publication number: 20240096436Abstract: Methods, systems, and devices for counter management for memory systems are described. A memory system may include circuitry configured to test localized counters of the memory system, where the circuitry may be configured to test a set of memory cells storing a value of the counter. During testing, the memory system may activate a row of memory cells a quantity of times, and the circuitry may increment a test counter associated with a subset of the set of memory cells for each activation to determine whether the subset is associated with an error. If a flag generated by the circuitry indicating a test count does not match an expected value, there may be an error associated with the subset. The circuitry may be operable to configure one or more multiplexers to refrain from using the subset to store the value of the counter based on the flag.Type: ApplicationFiled: September 21, 2022Publication date: March 21, 2024Inventor: Yuan He