Patents by Inventor Yuan Yang

Yuan Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240192288
    Abstract: An all-in-one sensing apparatus for transformer bushing tap monitoring includes: a tap lead device connected to a grounding wire of a transformer bushing through a mounting bracket and configured to lead out the grounding wire; a sensor assembly provided on the mounting bracket, connected to an oil taking port of the bushing, and configured to detect a temperature, a pressure, a partial discharge current and a hydrogen content of the bushing and upload the temperature, the pressure, the partial discharge current and the hydrogen content of the bushing; and a power module provided on the mounting bracket, and configured to supply power to the sensor assembly through coil induction, where an output terminal of the tap lead device is connected to the power module, and an output terminal of the power module is connected to the sensor assembly.
    Type: Application
    Filed: February 22, 2024
    Publication date: June 13, 2024
    Inventors: Guanghu Xu, Dingqian Yang, Dandong He, Xiaoguang Li, Duohu Gong, Shan Li, Yunkai Yue, Yuxuan Feng, Qingchuan Zhang, Yuan Zhang, Yadi Xie
  • Publication number: 20240195980
    Abstract: The method of the present disclosure includes: for a feature matrix of each channel of an image output from an intermediate layer of a neural network: determining row(s) and column(s) having same feature values at edges of the feature matrix as row(s) to be compressed and column(s) to be compressed, deleting the feature values of the row(s) to be compressed and the column(s) to be compressed, and reserving remaining feature values as reserved values; compressing the feature values of the row(s) to be compressed and the column(s) to be compressed to obtain edge value(s); and encoding the reserved values and the edge value(s), as well as a number of the row(s) to be compressed and a number of the column(s) to be compressed, and sending a result of the encoding to a decoder for restoring the feature matrix of the each channel by the decoder.
    Type: Application
    Filed: December 2, 2021
    Publication date: June 13, 2024
    Inventors: Huifen WANG, Yuan ZHANG, Mingchuan YANG, Leping SHEN
  • Patent number: 12009321
    Abstract: In various aspects, a package system includes at least a first package and a second package arranged on a same side of the package carrier. Each of the first package and the second package comprises an antenna to transmit and/or receive radio frequency signals. A cover may be arranged at a distance over the first package and the second package at the same side of the package carrier as the first package and the second package. The cover comprises at least one conductive element forming a predefined pattern on a side of the cover facing the first package and the second package. The predefined pattern is configured as a frequency selective surface. The package system further includes a radio frequency signal interface wirelessly connecting the antennas of the first package and the second package. The radio frequency signal interface comprises the at least one conductive element.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: June 11, 2024
    Assignee: Intel Corporation
    Inventors: Zhen Zhou, Tae Young Yang, Tolga Acikalin, Johanny Escobar Pelaez, Kenneth P. Foust, Chia-Pin Chiu, Renzhi Liu, Cheng-Yuan Chin
  • Patent number: 12010044
    Abstract: A method for managing data throughput of a network device is provided. The method includes: determining a network communication as belonging to a first class or a second class; enqueuing each packet received through the network communication determined as belonging to the first class to a first queue, and enqueuing each packet received through the networking communication determined as belonging to the second class to a second queue; dequeuing the first and second queues at a dequeuing ratio; determining a data rate of dequeuing the second queue; and adjusting the dequeuing ratio based on the data rate of dequeuing the second queue thus determined, a total bandwidth, and a guaranteed minimum bandwidth for the network communication determined as belonging to the first class.
    Type: Grant
    Filed: October 7, 2021
    Date of Patent: June 11, 2024
    Assignee: GT BOOSTER INC.
    Inventors: Shun Yuan Yang, Chiao Min Hu, Wei Teng Tai
  • Patent number: 12008127
    Abstract: Techniques are described for pooling data originating from different entities into a data pool managed by a data pool management system for performing accurate and resource-efficient statistical and other data operations by entities. Techniques further include maintaining rule sets that govern access to the data sets of the data pool. The DPMS uses the rule sets to determine whether a particular data set, on which a particular operation is requested to be performed, qualifies as authorized data for the requesting entity. In an embodiment, the DPMS determines, based on one rule set, that the particular data set does not qualify as authorized data for the particular operation. The DPMS further determines that based on another rule set the particular data set does qualify as authorized data for the particular operation. Based on determining that authorizing rule set overrides the non-authorizing rule set, DPMS proceeds to performing the particular operation using the particular data set.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: June 11, 2024
    Assignee: RATEGAIN ADARA, INC.
    Inventors: Michael Baird Leavitt, Chinmay Vikram Gandhi, Hongcheng Mi, Yuan Gao, Shuo Yang, Dylan Tao-Pei Su, Julius Quinoveva Quiaot, Jian An, Xiaozhou Fang, Melissa Beth Stein
  • Publication number: 20240186724
    Abstract: An antenna module includes an antenna box and a first connection wire. The antenna box can include a first antenna, a second antenna, a first connection terminal, a second connection terminal and a housing. The first and second antennas are located in the housing and the housing has a first opening collectively exposing a portion of the first connection terminal and a portion of the second connection terminal. Each of the first and second antennas is adapted to receive or transmit wireless signals according to one of a plurality of wireless communication standards and the first and second antennas are electrically connected to the first and second connection terminals, respectively. The wireless communication standards can be different from each other.
    Type: Application
    Filed: November 6, 2023
    Publication date: June 6, 2024
    Inventors: Tsai-Yi Yang, Yung-Sheng Tseng, Bo-Yuan Chang, Sheng-Shen Chang, Yu-Hua Chen, Shih-Shih Chien, En-Chin Wei
  • Publication number: 20240183082
    Abstract: A method for manufacturing an elastic fiber and the elastic fiber are provided. The method includes: providing a thermoplastic polyester elastomer; drying the thermoplastic polyester elastomer; melting the thermoplastic polyester elastomer by an extruder to form a melt; extruding the melt by a spinneret plate to form a plurality of filamentous streams; feeding the filamentous streams into a spinning channel for cooling and curing to form a plurality of monofilaments; and bundling and oiling the monofilaments by an oil wheel, after extending and guiding the monofilaments by a first godet roller and a second godet roller, and winding the monofilaments by a winder to obtain a thermoplastic polyester elastic fiber.
    Type: Application
    Filed: October 27, 2023
    Publication date: June 6, 2024
    Inventors: CHIH-YI LIN, KUO-KUANG CHENG, LI-YUAN CHEN, CHI-WEI CHANG, CHIA-CHUN YANG
  • Publication number: 20240184943
    Abstract: A cable modeling method and system, and an electronic device are provided. The method includes: acquiring preset cable attributes of a cable and a preset laying scenario of the cable; determining a start point, an end point and a path point of the cable according to the preset laying scenario; inputting the preset attributes of the cable, the start point, the end point, and the path point into an Autodesk Revit software to model the cable, thereby to obtain a cable simulation model; and laying the cable according to the cable simulation model. The method first determines a start point, an end point, and the path point of the cable through the preset laying scenario, and then inputs the preset attributes, the start point, the end point, and the path point into the Autodesk Revit software to model the cable, so as to obtain a cable simulation model.
    Type: Application
    Filed: August 23, 2023
    Publication date: June 6, 2024
    Inventors: Guangliang Zheng, Bo Li, Dezhi Han, Fucai Hua, Liangyin Yang, Gang Wang, Shunxing Wang, Hongyun Zou, Lanmu Zeng, Du Yang, Jianjun Zhang, Wei Liu, Xin Shao, Yuan Kong, Xiao Wang
  • Publication number: 20240182962
    Abstract: The present invention discloses an ultra-high-throughput single cell sequencing method, the method of the present invention including: firstly performing intracellular reverse transcription by using a reverse transcription sequence, or firstly performing intranuclear transposition of a transposase-accessible chromatin genome sequence by using a specific molecular barcode transposase-embedded complex, then compartmentalizing one or more cells or nuclei with one molecular labeled microbead by microwell-plate technology or microfluidic technology, followed by lysis of the cells or nuclei under the action of a lysis buffer, ligation of the sequences with the molecular label sequence on the molecular labeled microbeads through bridge primers, and PCR amplification to obtain a large quantity of sequences for construction of cDNA sequencing library, and then performing high-throughput sequencing, where information of specific transcriptome/genome accessibility of millions of single cells can be obtained in one run o
    Type: Application
    Filed: September 17, 2021
    Publication date: June 6, 2024
    Inventors: GUOJI GUO, YUAN LIAO, HAIDE CHEN, XIAOPING HAN, JINGJING WANG, GUODONG ZHANG, LEI YANG
  • Publication number: 20240186180
    Abstract: An integrated circuit (IC) structure includes a gate structure, a source epitaxial structure, a drain epitaxial structure, a front-side interconnection structure, a backside dielectric layer, and a backside via. The source epitaxial structure and the drain epitaxial structure are respectively on opposite sides of the gate structure. The front-side interconnection structure is on a front-side of the source epitaxial structure and a front-side of the drain epitaxial structure. The backside dielectric layer is on a backside of the source epitaxial structure and a backside of the drain epitaxial structure and has an air gap therein. The backside via extends through the backside dielectric layer to a first one of the source epitaxial structure and the drain epitaxial structure.
    Type: Application
    Filed: February 12, 2024
    Publication date: June 6, 2024
    Inventors: Che-Lun Chang, Wei-Yang Lee, Chia-Pin Lin, Yuan-Ching Peng
  • Patent number: 11998894
    Abstract: A composite solid base catalyst, a manufacturing method thereof and a manufacturing method of glycidol are provided. The composite solid base catalyst includes an aluminum carrier and a plurality of calcium particles. The plurality of calcium particles are supported by the aluminum carrier. Beta basic sites of the composite solid base catalyst are 0.58 mmol/g-3.89 mmol/g.
    Type: Grant
    Filed: June 14, 2022
    Date of Patent: June 4, 2024
    Assignees: NATIONAL TSING HUA UNIVERSITY, Chang Chun Plastics Co., Ltd., Chang Chun Petrochemical Co., LTD., DAIREN CHEMICAL CORP.
    Inventors: De-Hao Tsai, Yung-Tin Pan, Che-Ming Yang, Ching-Yuan Chang, Ding-Huei Tsai, Chien-Fu Huang, Yi-Ta Tsai
  • Patent number: 12002845
    Abstract: In a method of manufacturing a semiconductor device, a fin structure, which includes a stacked layer of first semiconductor layers and second semiconductor layers disposed over a bottom fin structure and a hard mask layer over the stacked layer, is formed. An isolation insulating layer is formed. A sacrificial cladding layer is formed over at least sidewalls of the exposed hard mask layer and stacked layer. A first dielectric layer is formed. A second dielectric layer is formed over the first dielectric layer. The second dielectric layer is recessed. A third dielectric layer is formed on the recessed second dielectric layer. The third dielectric layer is partially removed to form a trench. A fourth dielectric layer is formed by filling the trench with a dielectric material, thereby forming a wall fin structure.
    Type: Grant
    Filed: January 13, 2022
    Date of Patent: June 4, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ting-Yeh Chen, Wei-Yang Lee, Chia-Pin Lin, Yuan-Ching Peng
  • Patent number: 12002522
    Abstract: A memory device and an operation method thereof are provided. The operation method includes: in a programming operation, programming a plurality of threshold voltages of a plurality of switches on a plurality of string select lines and a plurality of ground select lines as a first reference threshold voltage, and programming a plurality of threshold voltages of a plurality of dummy memory cells on a plurality of dummy word lines as being gradually increased along a first direction or a second direction, and the threshold voltages of the dummy memory cells being higher than the first reference threshold voltage; wherein the first direction being from the string select lines to a plurality of word lines and the second direction being from the ground select lines to the word lines.
    Type: Grant
    Filed: May 13, 2022
    Date of Patent: June 4, 2024
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Tao-Yuan Lin, I-Chen Yang, Yao-Wen Chang
  • Patent number: 12002715
    Abstract: A method includes forming a first fin and a second fin on a substrate; forming a dummy gate material over the first fin and the second fin; etching the dummy gate material using a first etching process to form a recess between the first fin and the second fin, wherein a sacrificial material is formed on sidewalls of the recess during the first etching process; filling the recess with an insulation material; removing the dummy gate material and the sacrificial material using a second etching process; and forming a first replacement gate over the first fin and a second replacement gate over the second fin, wherein the first replacement gate is separated from the second replacement gate by the insulation material.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: June 4, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ya-Yi Tsai, Wei-Ting Guo, I-Wei Yang, Shu-Yuan Ku
  • Publication number: 20240178750
    Abstract: Controller and method for a quasi-resonant switching power supply. For example, a controller for a quasi-resonant switching power supply includes: a valley detector configured to receive a voltage signal, detect one or more voltage valleys of the voltage signal in magnitude, and generate a detection signal representing the detected one or more voltage valleys; a valley-locking controller configured to receive one or more signals, generate a mode control signal that indicates a selected valley-locking mode based at least in part on the one or more signals, select from the detected one or more voltage valleys, one or more valleys that correspond to the selected valley-locking mode, and generate a valley control signal indicating the one or more selected valleys; and a gate driver configured to generate a drive signal based on at least information associated with the valley control signal.
    Type: Application
    Filed: October 31, 2023
    Publication date: May 30, 2024
    Inventors: PENGLIN YANG, YUAN LIN
  • Publication number: 20240178261
    Abstract: Chip packages and methods for forming the same are provided. The chip package includes a substrate having a stepped sidewall, a first surface, and a second surface. The first surface and the second surface are opposite each other. The first surface and the second surface adjoin the stepped sidewall. The chip package also includes a capping layer having a first surface and a second surface opposite each other. The first surface of the capping layer faces the second surface of the substrate. The chip package further includes a dam structure and an adhesive layer. The dam structure bonds the capping layer to the substrate, and surrounds a sensing region in the substrate. The adhesive layer surrounds the dam structure and has a concave-tapered sidewall that extends along the outer edge of the dam structure in the direction from the second surface of the substrate to the capping layer.
    Type: Application
    Filed: October 20, 2023
    Publication date: May 30, 2024
    Inventors: Kuei-Wei CHEN, Chao-Yuan YANG, Yueh Hsien LI
  • Publication number: 20240177319
    Abstract: Many unsupervised domain adaptation (UDA) methods have been proposed to bridge the domain gap by utilizing domain invariant information. Most approaches have chosen depth as such information and achieved remarkable successes. Despite their effectiveness, using depth as domain invariant information in UDA tasks may lead to multiple issues, such as excessively high extraction costs and difficulties in achieving a reliable prediction quality. As a result, we introduce Edge Learning based Domain Adaptation (ELDA), a framework which incorporates edge information into its training process to serve as a type of domain invariant information. Our experiments quantitatively and qualitatively demonstrate that the incorporation of edge information is indeed beneficial and effective, and enables ELDA to outperform the contemporary state-of-the-art methods on two commonly adopted benchmarks for semantic segmentation based UDA tasks.
    Type: Application
    Filed: November 24, 2023
    Publication date: May 30, 2024
    Applicant: MEDIATEK INC.
    Inventors: Ting-Hsuan Liao, Huang-Ru Liao, Shan-Ya Yang, Jie-En Yao, Li-Yuan Tsao, Hsu-Shen Liu, Bo-Wun Cheng, Chen-Hao Chao, Chia-Che Chang, Yi-Chen Lo, Chun-Yi Lee
  • Patent number: 11996519
    Abstract: A gel composition, in particular a gelled electrolyte, comprising: i) fumed alumina particles, wherein the mean primary particle size of the particle is from 5 to 50 nm and the BET specific surface area is from 40 to 400 m2/g; ii) at least two organic solvents; and iii) a lithium salt; wherein the amount of the alumina particles is 0.2-10% by weight based on the total weight of the gel composition. A method to prepare a gelled electrolyte, a Li-ion battery, a Li-ion battery and a device are also provided.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: May 28, 2024
    Assignee: Evonik Operations GmbH
    Inventors: Shasha Su, Jinhua Jiang, Jing Feng, Dong Wang, Yuan-Chang Huang, Jun Yang, Bin Lei, Zhixin Xu
  • Patent number: 11993950
    Abstract: Example embodiments provide mechanical dampers. The mechanical dampers may be applied to dissipate energy in a structure that arises for example from a dynamic load such as seismic activity, vehicle impact, vibration of the structure, wind forces, an explosion, etc. The damper comprises a pair of clamping plates. A shear plate is held between the clamping plates. The shear plate is movable in transverse directions relative to the clamping plates. The damper also comprises a conical wedge coupled between one of the clamping plates and the shear plate. The conical wedge comprises a female conical element and a male conical element that projects into a conical indentation of the female conical element.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: May 28, 2024
    Assignee: The University of British Columbia
    Inventors: Tsung Yuan Yang, Hengchao Xu, Lisa Tobber
  • Publication number: 20240170587
    Abstract: The present disclosure discloses a thin film photovoltaic cell, a cell pack and a method for fabricating the thin film photovoltaic cell, a film layer structure of the thin film photovoltaic cell is arranged in sequential attachment by: a transparent substrate, a transparent electrode, a thin film photovoltaic layer, a first metal electrode layer, an insulating layer, a second metal electrode layer, and a protective layer; the thin film photovoltaic cell includes a power generation region, a positive electrode and a negative electrode, the positive electrode and the negative electrode are respectively arranged at both ends of the power generation region; a plurality of first via structure patterns are arranged in the power generation region of the thin film photovoltaic cell, and in the power generation region of the thin film photovoltaic cell, the transparent electrode is connected to the second metal electrode layer with the first via structure patterns.
    Type: Application
    Filed: November 22, 2023
    Publication date: May 23, 2024
    Applicant: TRULY SEMICONDUCTORS LTD.
    Inventors: Liang YANG, Xiongcai XIE, Yuan LI, Guang HUANG