Abstract: An example connector assembly includes a guide shielding cage with a cage body and an upper heat sink bracket. The cage body includes upper window. A lower wall of the upper heat sink bracket is formed with a window corresponding to the upper window. The connector assembly also includes an upper heat sink module including a heat dissipating member. The heat dissipating member is capable of moving between a releasing position which is higher and an acting position which is lower relative to the upper insertion space. The cage body further includes fixing pieces positioned at two sides of the top wall and extend upwardly. The lower wall of the upper heat sink bracket engages with the fixing pieces of the cage body, and the upper heat sink bracket further comprises a latching piece which extends from the lower wall and latches into the top wall of the cage body.

Abstract: The present application provides a touch sensing circuit, which comprises a plurality of analog front-end circuits, a noise processing circuit, and a compensation circuit. The analog front-end circuits generate a plurality of output signals according to a plurality of sensing signals. The noise processing circuit is coupled to the analog front-end circuits and generates an average noise according to the output signals. The compensation circuit is coupled to the noise processing circuit and compensates the output signals according to the average noise. By applying the touch sensing circuit of the present application, the influence of common-mode noise may be suppressed and the sensitivity of sensing touches may be improved.

Abstract: Semiconductor devices, integrated circuits and methods of forming the same are provided. In one embodiment, a semiconductor device includes a metal-insulator-metal structure which includes a bottom conductor plate layer including a first opening and a second opening, a first dielectric layer over the bottom conductor plate layer, a middle conductor plate layer over the first dielectric layer and including a third opening, a first dummy plate disposed within the third opening, and a fourth opening, a second dielectric layer over the middle conductor plate layer, and a top conductor plate layer over the second dielectric layer and including a fifth opening, a second dummy plate disposed within the fifth opening, a sixth opening, and a third dummy plate disposed within the sixth opening. The first opening, the first dummy plate, and the second dummy plate are vertically aligned.

Abstract: Passive devices are provided. In an embodiment, a passive device includes a substrate comprising a first region and a second region, a first lower contact feature and a second lower contact feature in a dielectric layer and directly over the first region and the second region, respectively, a first vertical stack of conductive features disposed over the first region, a metal-insulator-metal (MIM) capacitor disposed over the second region and comprising a vertical stack of conductor plates, a first contact via extending through the first vertical stack of conductive features and electrically coupled to the first lower contact feature, and a second contact via extending through a portion of the vertical stack of conductor plates and electrically coupled to the second lower contact feature. A number of conductive features penetrated by the first contact via is different than a number of conductor plates penetrated by the second contact via.

Abstract: A device structure according to the present disclosure includes a passivation layer, a first conductor plate layer disposed on the passivation layer, a second conductor plate layer disposed over the first conductor layer, a third conductor plate layer disposed over the second conductor layer, and a fourth conductor plate layer disposed over the third conductor layer. The second conductor plate layer encloses the first conductor plate layer and the fourth conductor plate layer encloses the third conductor plate layer. The device structure, when used in a back-end-of-line passive device, reduces leakage and breakdown due to corner discharge effect.

Abstract: A method of manufacturing a semiconductor device includes forming a first conductive layer over a first insulating layer and forming a first dielectric layer over the first conductive layer. A second conductive layer is formed over a first portion of the first dielectric layer. A second dielectric layer is formed over the second conductive layer. A third conductive layer is formed over the second dielectric layer and the second portion of the first dielectric layer. A third dielectric layer is formed over the third conductive layer. A first conductive contact is formed contacting the first conductive layer. A second conductive contact is formed contacting the third conductive layer. The second conductive layer is an electrically floating layer.

Abstract: A voltage-controlled oscillator device includes first and second voltage-controlled oscillators, a first switch group including two first switches, and a second switch group including two second switches. The first voltage-controlled oscillator includes a first inductor group, a first negative resistance circuit and a first voltage output terminal group. The second voltage-controlled oscillator includes a second inductor group, a second negative resistance circuit and a second voltage output terminal group. For the first switch group, first control terminals are electrically connected to the first voltage output terminal group, first input terminals are electrically connected to the second voltage output terminal group, first output terminals are electrically connected.

Abstract: The invention discloses an electronic device. The electronic device comprises a body and a function module. The function module is rotatably disposed in the body, and includes a housing, a function component and a rigid-flex circuit board. The housing includes a shaft portion. The shaft portion is engaged to the body. The function component and the rigid-flex circuit board are disposed in the housing. The rigid-flex circuit board includes a rigid board portion and at least a flexible board portion. The rigid board portion is electrically connected to the function component. The flexible board portion is connected to the rigid board portion. The flexible board portion passes through the shaft portion and extends into the body.

Abstract: A package structure includes an optical die, an optical die, a supporting structure, and a lens structure. The optical die includes a photonic region. The optical die is disposed on and electrically coupled to the optical die. The supporting structure is disposed on the optical die, where the electric die is disposed between the supporting structure and the optical die. The lens structure is disposed on the supporting structure and optically coupled to the photonic region of the optical die, where the supporting structure is disposed between the lens structure and the electric die.

Abstract: A metal-insulator-metal (MIM) structure and methods of forming the same for reducing the accumulation of external stress at the corners of the conductor layers are disclosed herein. An exemplary device includes a substrate that includes an active semiconductor device. A stack of dielectric layers is disposed over the substrate. A lower contact is disposed over the stack of dielectric layers. A passivation layer is disposed over the lower contact. A MIM structure is disposed over the passivation layer, the MIM structure including a first conductor layer, a second conductor layer disposed over the first conductor layer, and a third conductor layer disposed over the second conductor layer. A first insulator layer is disposed between the first conductor layer and the second conductor layer. A second insulator layer is disposed between the second conductor layer and the third conductor layer. One or more corners of the third conductor layer are rounded.

Abstract: Via array configurations for metal-insulator-metal (MIM) capacitor structures are disclosed herein. An exemplary MIM capacitor structure includes a capacitor bottom metal layer, a first dielectric layer over the capacitor bottom metal layer, a capacitor middle metal layer over the first dielectric layer, a second dielectric layer over the capacitor middle metal layer, and a capacitor top metal layer over the second dielectric layer. A metal via array, which has a first metal via and a second metal via, is connected to the capacitor top metal layer and the capacitor bottom metal layer. A portion of the capacitor top metal layer covers an area of the second dielectric layer extending from the first metal via to the second metal via. From a top view, the portion of the capacitor top metal layer surrounds the first metal via and the second metal via.

Abstract: A semiconductor packaging structure includes a first passivation layer, a capacitor structure, and a second passivation layer. The capacitor structure is disposed on the first passivation layer. The second passivation layer is disposed on the capacitor structure opposite to the first passivation layer. The second passivation layer has a compressive stress that is smaller than ?0.3 GPa.

Abstract: The present invention relates to an n-type conductive composition comprising a rigid conjugated polymer having a dihedral angle from 0° to 20° and an n-type polymeric cation. Further, the present invention relates to an n-type conductive ink comprising such a composition.

Abstract: The application discloses a method, for building an oscillator frequency adjustment lookup table in a transceiver, wherein the transceiver generates a clock according to a crystal oscillator external to the transceiver for transceiving data. The transceiver includes adjustable capacitor arrays assembly connected to the crystal oscillator, wherein when an equivalent capacitance of the adjustable capacitor assembly is a reference value, the crystal oscillator has a reference frequency, and when the equivalent capacitance changes relative to the reference value, the crystal oscillator correspondingly has a frequency offset relative to the reference frequency. The method includes: performing an interpolation operation according to a first value, a second value, and a third value of the equivalent capacitance, and the corresponding frequency variations, so as to obtain the frequency variations corresponding to a first sub-value between the first value and the second values.

Abstract: A device structure, along with methods of forming such, are described. The device structure includes a structure, a first passivation layer disposed on the structure, a buffer layer disposed on the first passivation layer, a barrier layer disposed on a first portion of the buffer layer, a redistribution layer disposed over the barrier layer, an adhesion layer disposed on the barrier layer and on side surfaces of the redistribution layer, and a second passivation layer disposed on a second portion of the buffer layer. The second passivation layer is in contact with the barrier layer, the adhesion layer, and the redistribution layer.

Abstract: An example connector assembly includes a cage, a first liquid cooling tray, a second liquid cooling tray, and a pressuring spring. The cage includes a frame and partitioning walls. The frame and the partitioning walls define an insertion space. The first liquid cooling tray is provided to a top of the cage, with a lower surface of the first liquid cooling tray constituting an upper wall surface of the insertion space. The second liquid cooling tray is provided to a bottom of the cage, with an upper surface of the second liquid cooling tray constituting a lower wall surface of the insertion space. The pressuring spring is positioned within the insertion space.

Abstract: In a method of manufacturing a semiconductor device, an opening is formed in a first dielectric layer so that a part of a lower conductive layer is exposed at a bottom of the opening, one or more liner conductive layers are formed over the part of the lower conductive layer, an inner sidewall of the opening and an upper surface of the first dielectric layer, a main conductive layer is formed over the one or more liner conductive layers, a patterned conductive layer is formed by patterning the main conductive layer and the one or more liner conductive layers, and a cover conductive layer is formed over the patterned conductive layer. The main conductive layer which is patterned is wrapped around by the cover conductive layer and one of the one or more liner conductive layers.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to improve feature engineering efficiency. An example method disclosed herein includes retrieving a log file in a first file format, the log file containing feature occurrence data, generating a first unit operation based on the first file format to extract the feature occurrence data from the log file to a string, the first unit operation associated with a first metadata tag, generating second unit operations to identify respective features from the feature occurrence data, the second unit operations associated with respective second metadata tags, and generating a first sequence of the first metadata tag and the second metadata tags to create a first vector output file of the feature occurrence data.

Abstract: A connector assembly is provided and includes a guide shielding cage and a heat sink module. The guide shielding cage has at least one insertion space positioned inside. The heat sink module includes a heat dissipating member, a pressure applying elastic member, a lever member and a supporting elastic member. The heat dissipating member has a thermal coupling portion formed downwardly, the lever member is pivoted to the guide shielding cage, the lever member has a pushed end and a pressure applying end, the supporting elastic member upwardly and elastically supports the heat dissipating member. The heat dissipating member is capable of moving between a releasing position which is higher relative to the insertion space and an acting position which is lower relative to the insertion space and where the thermal coupling portion enters into the insertion space.

Abstract: A device structure according to the present disclosure includes a metal-insulator-metal (MIM) stack. The MIM stack includes at least one lower conductor plate layer, a first insulator layer disposed over the at least one lower conductor plate layer, a first conductor plate layer disposed over the first insulator layer, a second insulator layer disposed over the first conductor plate layer, and a second conductor plate layer disposed over the second insulator layer. The device structure further includes a ground via extending through and electrically coupled to a first ground plate in the first conductor plate layer and a first via extending through and electrically coupled to a high voltage plate in the second conductor plate layer. The first ground plate vertically overlaps the high voltage plate and the second insulator layer is different from the first insulator layer.