Patents by Inventor Yuan Yang

Yuan Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11901791
    Abstract: A functional module is provided. The functional module is applied to an electronic device, and includes a housing, a functional member, and a motor assembly. Both the functional member and the motor assembly are disposed in the housing. The motor assembly includes a motor and an output shaft. The motor is configured to drive the output shaft to rotate. The output shaft protrudes from one side of the housing.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: February 13, 2024
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Chia-Min Cheng, Chui-Hung Chen, Ching-Yuan Yang, Cheng-Han Chung
  • Patent number: 11895955
    Abstract: Disclosed is a combined LED grow lighting system, comprising an LED light track and at least one LED light strip which slidably connects with and longitudinally slides along the LED light track; wherein a remote control signal receiver to receive a remote control signal is configured within the LED light track, a processing device for processing the remote control signal received by the remote control signal receiver to generate a control signal for controlling a power of LED in each LED light strip is connected with each LED light strip, respectively; an LED constant current power supply and a constant current control circuit are configured within the LED light strip, and the constant current control circuit is connected with the processing device and receives the control signal regarding the power of the LED light strip sent from the processing device to control the LED constant current power supply.
    Type: Grant
    Filed: January 19, 2021
    Date of Patent: February 13, 2024
    Assignee: SHENZHEN NUMBER ENERGY SAVING CORPORATION
    Inventors: Hongchuan Chen, Yuan Yang, Jiaqin Li, Bing Ma
  • Publication number: 20240027709
    Abstract: A connector assembly includes a cage having at least one inserting passageway and a heat sink frame positioned above the inserting passageway, the heat sink module is assembled to the heat sink frame, the heat sink module includes a movable plate, a heat sink, a pressure-applying spring and a supporting spring; the movable plate has a pushed portion which enters into the inserting passageway, the pressure-applying spring is provided between the movable plate and the heat sink, the supporting spring upwardly and elastically supports the heat sink; the movable plate is capable of moving relative to the heat sink frame between a first position which is in the front and a second position which is in the rear, the heat sink is capable of moving relative to the heat sink frame between a release position which is in the up and a contact position which is in the down.
    Type: Application
    Filed: July 7, 2023
    Publication date: January 25, 2024
    Inventors: Che-Yuan Yang, Ya-Li Xu
  • Patent number: 11881421
    Abstract: An apparatus having a first portion including a first front wall, a first rear wall, and a bottom wall integrally coupled to the first front wall and the first rear wall, and pivotal pin structures integrally coupled to and extending from the first rear wall. The apparatus includes a second portion having a second front wall, a second rear wall, and a top wall integrally coupled to the second front wall and the second rear wall, and pin holders integrally coupled to and extending from the second rear wall and at an offset angle with reference to the top wall. The pivotal pin structure includes a base support connected to the first rear wall and a shaft connected to the base support, and the pin holder defines an opening sized and shaped to accept the shaft. The first and second portions are sized and shaped to be pivotally movable between open and closed configurations.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: January 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tzu-Chung Tsai, Ping-Cheng Ko, Fang-yu Liu, Jhih-Yuan Yang
  • Publication number: 20240014844
    Abstract: The present disclosure discloses a transceiver apparatus having self-calibration mechanism that includes a signal transmission path, a signal receiving path, a path switching circuit, a transceiver circuit and a self-calibration circuit. The path switching circuit includes a switch to switch a connection relation among an antenna, the signal transmission path and the signal receiving path. The transceiver circuit is coupled to the signal transmission path and the signal receiving path. The self-calibration circuit controls the transceiver circuit to transmit a transmission signal through the signal transmission path to the path switching circuit and receives a leakage signal generated according to the transmission signal through the signal receiving path, so as to perform a self-calibration process on the transceiver circuit based on the transmission signal and the leakage signal. The leakage signal has a leakage signal strength larger than a predetermined level.
    Type: Application
    Filed: June 6, 2023
    Publication date: January 11, 2024
    Inventors: HUNG-YUAN YANG, HUNG-MIN LIN, YUN-RU HUANG
  • Publication number: 20240002689
    Abstract: The present invention relates to a method for manufacturing a dispersion solution comprising nanoparticles of a rigid conjugated polymer having a dihedral angle from 0° to 20°, the method comprising the steps of: a) dissolving the rigid conjugated polymer in a first solvent system; b) combining the dissolved rigid conjugated polymer with a second solvent system thus obtaining a precipitate comprising the rigid conjugated polymer; c) collecting the precipitate comprising the rigid conjugated polymer; d) re-dispersing the precipitate in a third solvent system thus obtaining a dispersion solution comprising nanoparticles of the rigid conjugated polymer.
    Type: Application
    Filed: November 20, 2020
    Publication date: January 4, 2024
    Inventors: Simone FABIANO, Magnus BERGGREN, Marc-Antoine STOECKEL, Chi-Yuan YANG
  • Publication number: 20230411897
    Abstract: An example connector assembly includes a guide shielding cage with a cage body and an upper heat sink bracket. The cage body includes upper window. A lower wall of the upper heat sink bracket is formed with a window corresponding to the upper window. The connector assembly also includes an upper heat sink module including a heat dissipating member. The heat dissipating member is capable of moving between a releasing position which is higher and an acting position which is lower relative to the upper insertion space. The cage body further includes fixing pieces positioned at two sides of the top wall and extend upwardly. The lower wall of the upper heat sink bracket engages with the fixing pieces of the cage body, and the upper heat sink bracket further comprises a latching piece which extends from the lower wall and latches into the top wall of the cage body.
    Type: Application
    Filed: September 6, 2023
    Publication date: December 21, 2023
    Inventor: Che-Yuan Yang
  • Publication number: 20230400946
    Abstract: The present application provides a touch sensing circuit, which comprises a plurality of analog front-end circuits, a noise processing circuit, and a compensation circuit. The analog front-end circuits generate a plurality of output signals according to a plurality of sensing signals. The noise processing circuit is coupled to the analog front-end circuits and generates an average noise according to the output signals. The compensation circuit is coupled to the noise processing circuit and compensates the output signals according to the average noise. By applying the touch sensing circuit of the present application, the influence of common-mode noise may be suppressed and the sensitivity of sensing touches may be improved.
    Type: Application
    Filed: January 4, 2023
    Publication date: December 14, 2023
    Inventors: Chen-Yuan Yang, Hung-Yen Tai, Tzu-Hsuan Liu
  • Patent number: 11842959
    Abstract: Semiconductor devices, integrated circuits and methods of forming the same are provided. In one embodiment, a semiconductor device includes a metal-insulator-metal structure which includes a bottom conductor plate layer including a first opening and a second opening, a first dielectric layer over the bottom conductor plate layer, a middle conductor plate layer over the first dielectric layer and including a third opening, a first dummy plate disposed within the third opening, and a fourth opening, a second dielectric layer over the middle conductor plate layer, and a top conductor plate layer over the second dielectric layer and including a fifth opening, a second dummy plate disposed within the fifth opening, a sixth opening, and a third dummy plate disposed within the sixth opening. The first opening, the first dummy plate, and the second dummy plate are vertically aligned.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: December 12, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yuan-Yang Hsiao, Hsiang-Ku Shen, Dian-Hau Chen
  • Publication number: 20230395487
    Abstract: Passive devices are provided. In an embodiment, a passive device includes a substrate comprising a first region and a second region, a first lower contact feature and a second lower contact feature in a dielectric layer and directly over the first region and the second region, respectively, a first vertical stack of conductive features disposed over the first region, a metal-insulator-metal (MIM) capacitor disposed over the second region and comprising a vertical stack of conductor plates, a first contact via extending through the first vertical stack of conductive features and electrically coupled to the first lower contact feature, and a second contact via extending through a portion of the vertical stack of conductor plates and electrically coupled to the second lower contact feature. A number of conductive features penetrated by the first contact via is different than a number of conductor plates penetrated by the second contact via.
    Type: Application
    Filed: June 3, 2022
    Publication date: December 7, 2023
    Inventors: Mao-Nan Wang, Yuan-Yang Hsiao, Chen-Chiu Huang, Dian-Hau Chen
  • Publication number: 20230386996
    Abstract: A device structure according to the present disclosure includes a passivation layer, a first conductor plate layer disposed on the passivation layer, a second conductor plate layer disposed over the first conductor layer, a third conductor plate layer disposed over the second conductor layer, and a fourth conductor plate layer disposed over the third conductor layer. The second conductor plate layer encloses the first conductor plate layer and the fourth conductor plate layer encloses the third conductor plate layer. The device structure, when used in a back-end-of-line passive device, reduces leakage and breakdown due to corner discharge effect.
    Type: Application
    Filed: August 10, 2023
    Publication date: November 30, 2023
    Inventors: Tsung-Chieh Hsiao, Hsiang-Ku Shen, Yuan-Yang Hsiao, Chen-Chiu Huang, Dian-Hau Chen
  • Publication number: 20230387192
    Abstract: A method of manufacturing a semiconductor device includes forming a first conductive layer over a first insulating layer and forming a first dielectric layer over the first conductive layer. A second conductive layer is formed over a first portion of the first dielectric layer. A second dielectric layer is formed over the second conductive layer. A third conductive layer is formed over the second dielectric layer and the second portion of the first dielectric layer. A third dielectric layer is formed over the third conductive layer. A first conductive contact is formed contacting the first conductive layer. A second conductive contact is formed contacting the third conductive layer. The second conductive layer is an electrically floating layer.
    Type: Application
    Filed: May 25, 2022
    Publication date: November 30, 2023
    Inventors: Tsung-Chieh HSIAO, Hsiang-Ku SHEN, Yuan-Yang HSIAO, Wen-Chiung TU, Chen-Chiu HUANG, Dian-Hau CHEN
  • Patent number: 11831278
    Abstract: A voltage-controlled oscillator device includes first and second voltage-controlled oscillators, a first switch group including two first switches, and a second switch group including two second switches. The first voltage-controlled oscillator includes a first inductor group, a first negative resistance circuit and a first voltage output terminal group. The second voltage-controlled oscillator includes a second inductor group, a second negative resistance circuit and a second voltage output terminal group. For the first switch group, first control terminals are electrically connected to the first voltage output terminal group, first input terminals are electrically connected to the second voltage output terminal group, first output terminals are electrically connected.
    Type: Grant
    Filed: August 11, 2022
    Date of Patent: November 28, 2023
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chih-Hsiang Chang, Yu Lee, Hua-Shan Hu, Ching-Yuan Yang
  • Patent number: 11825006
    Abstract: The invention discloses an electronic device. The electronic device comprises a body and a function module. The function module is rotatably disposed in the body, and includes a housing, a function component and a rigid-flex circuit board. The housing includes a shaft portion. The shaft portion is engaged to the body. The function component and the rigid-flex circuit board are disposed in the housing. The rigid-flex circuit board includes a rigid board portion and at least a flexible board portion. The rigid board portion is electrically connected to the function component. The flexible board portion is connected to the rigid board portion. The flexible board portion passes through the shaft portion and extends into the body.
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: November 21, 2023
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Chia-Min Cheng, Chui-Hung Chen, Ching-Yuan Yang, Cheng-Han Chung
  • Publication number: 20230369370
    Abstract: A package structure includes an optical die, an optical die, a supporting structure, and a lens structure. The optical die includes a photonic region. The optical die is disposed on and electrically coupled to the optical die. The supporting structure is disposed on the optical die, where the electric die is disposed between the supporting structure and the optical die. The lens structure is disposed on the supporting structure and optically coupled to the photonic region of the optical die, where the supporting structure is disposed between the lens structure and the electric die.
    Type: Application
    Filed: May 13, 2022
    Publication date: November 16, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jung Chen, Tsung-Fu Tsai, Szu-Wei Lu, Wei-An Tsao, Che-Yuan Yang, Chien-Ting Chen, Chih-Chieh Hung
  • Publication number: 20230369199
    Abstract: A metal-insulator-metal (MIM) structure and methods of forming the same for reducing the accumulation of external stress at the corners of the conductor layers are disclosed herein. An exemplary device includes a substrate that includes an active semiconductor device. A stack of dielectric layers is disposed over the substrate. A lower contact is disposed over the stack of dielectric layers. A passivation layer is disposed over the lower contact. A MIM structure is disposed over the passivation layer, the MIM structure including a first conductor layer, a second conductor layer disposed over the first conductor layer, and a third conductor layer disposed over the second conductor layer. A first insulator layer is disposed between the first conductor layer and the second conductor layer. A second insulator layer is disposed between the second conductor layer and the third conductor layer. One or more corners of the third conductor layer are rounded.
    Type: Application
    Filed: July 26, 2023
    Publication date: November 16, 2023
    Inventors: Yuan-Yang Hsiao, Hsiang-Ku Shen, Dian-Hau Chen, Hsiao Ching-Wen, Yao-Chun Chuang
  • Publication number: 20230352394
    Abstract: A semiconductor packaging structure includes a first passivation layer, a capacitor structure, and a second passivation layer. The capacitor structure is disposed on the first passivation layer. The second passivation layer is disposed on the capacitor structure opposite to the first passivation layer. The second passivation layer has a compressive stress that is smaller than ?0.3 GPa.
    Type: Application
    Filed: April 28, 2022
    Publication date: November 2, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Te CHU, Yuan-Yang HSIAO, Chih-Pin CHIU, Ying-Yao LAI, Mao-Nan WANG, Chen-Chiu HUANG, Dian-Hau CHEN
  • Publication number: 20230352396
    Abstract: Via array configurations for metal-insulator-metal (MIM) capacitor structures are disclosed herein. An exemplary MIM capacitor structure includes a capacitor bottom metal layer, a first dielectric layer over the capacitor bottom metal layer, a capacitor middle metal layer over the first dielectric layer, a second dielectric layer over the capacitor middle metal layer, and a capacitor top metal layer over the second dielectric layer. A metal via array, which has a first metal via and a second metal via, is connected to the capacitor top metal layer and the capacitor bottom metal layer. A portion of the capacitor top metal layer covers an area of the second dielectric layer extending from the first metal via to the second metal via. From a top view, the portion of the capacitor top metal layer surrounds the first metal via and the second metal via.
    Type: Application
    Filed: September 1, 2022
    Publication date: November 2, 2023
    Inventors: Yuan-Yang Hsiao, Hsiang-Ku Shen
  • Publication number: 20230340201
    Abstract: The present invention relates to an n-type conductive composition comprising a rigid conjugated polymer having a dihedral angle from 0° to 20° and an n-type polymeric cation. Further, the present invention relates to an n-type conductive ink comprising such a composition.
    Type: Application
    Filed: November 20, 2020
    Publication date: October 26, 2023
    Inventors: Simone FABIANO, Magnus BERGGREN, Marc-Antoine STOECKEL, Chi-Yuan YANG
  • Patent number: 11799423
    Abstract: The application discloses a method, for building an oscillator frequency adjustment lookup table in a transceiver, wherein the transceiver generates a clock according to a crystal oscillator external to the transceiver for transceiving data. The transceiver includes adjustable capacitor arrays assembly connected to the crystal oscillator, wherein when an equivalent capacitance of the adjustable capacitor assembly is a reference value, the crystal oscillator has a reference frequency, and when the equivalent capacitance changes relative to the reference value, the crystal oscillator correspondingly has a frequency offset relative to the reference frequency. The method includes: performing an interpolation operation according to a first value, a second value, and a third value of the equivalent capacitance, and the corresponding frequency variations, so as to obtain the frequency variations corresponding to a first sub-value between the first value and the second values.
    Type: Grant
    Filed: May 12, 2022
    Date of Patent: October 24, 2023
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hung Min Lin, Hung-Yuan Yang