Patents by Inventor Yu Che

Yu Che has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240143191
    Abstract: A cyclic backup method for a solid-state disk (SSD) device includes writing, by a controller, data into corresponding physical address and reading data from corresponding physical address according to logic address of a first mapping table; receiving, by the controller, a backup signal; writing, by the controller, data into corresponding physical address and reading data from corresponding physical address according to logic address of a second mapping table; reading, by the controller, a first data according to logic address of the first mapping table when the controller cannot read the first data according to logic address of the second mapping table; receiving, by the controller, a recovery signal; and reading, by the controller, data from corresponding physical address according to logic address of the first mapping table.
    Type: Application
    Filed: December 22, 2022
    Publication date: May 2, 2024
    Applicant: Apacer Technology Inc.
    Inventor: Yu-Che Lee
  • Publication number: 20240143529
    Abstract: A method for a host computer to access a target device via a remote extender. The target device is connected to the remote extender, and a target device driver corresponding to the target device is installed on the host computer. The method includes setting up a logic transmission pipe between the host computer and the remote extender with a network connection as the underlying transmission path, and handling an I/O request from the target device driver to access the target device via the logic transmission pipe. The method is used to allow the target device to be treated by the host computer as a local resource. Additionally, the disclosure provides a system for accessing the remote target device and a remote extender thereof.
    Type: Application
    Filed: March 9, 2023
    Publication date: May 2, 2024
    Inventors: YU-HAN LIU, SHENG-CHE CHUEH, CHONG-LI HUANG
  • Publication number: 20240142747
    Abstract: An optical element driving mechanism is for accommodating a first optical element and includes a fixed assembly, a movable part and a driving assembly. The movable part is configured to connect a second optical element, the second optical element corresponds to the first optical element, and the movable part is movable relative to the fixed assembly. The driving assembly is configured to drive the movable part to move relative to the fixed assembly. The fixed assembly includes a first accommodating space configured to accommodate the first optical element.
    Type: Application
    Filed: October 26, 2023
    Publication date: May 2, 2024
    Inventors: Chia-Che WU, Chao-Chang HU, Yu-Chiao LO
  • Patent number: 11973054
    Abstract: A method for transferring an electronic device includes steps as follows. A flexible carrier is provided and has a surface with a plurality of electronic devices disposed thereon. A target substrate is provided corresponding to the surface of the flexible carrier. A pin is provided, and a pin end thereof presses on another surface of the flexible carrier without the electronic devices disposed thereon, so that the flexible carrier is deformed, causing at least one of the electronic devices to move toward the target substrate and to be in contact with the target substrate. A beam is provided to transmit at least a portion of the pin and emitted from the pin end to melt a solder. The electronic device is fixed on the target substrate by soldering. The pin is moved to restore the flexible carrier to its original shape, allowing the electronic device fixed by soldering to separate from the carrier.
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: April 30, 2024
    Assignee: Stroke Precision Advanced Engineering Co., Ltd.
    Inventors: Yu-Min Huang, Sheng Che Huang, Chingju Lin, Wei-Hao Wang
  • Publication number: 20240135990
    Abstract: A resistive memory apparatus including a memory cell array, at least one dummy transistor and a control circuit is provided. The memory cell array includes a plurality of memory cells. Each of the memory cells includes a resistive switching element. The dummy transistor is electrically isolated from the resistive switching element. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is configured to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor to drive the dummy transistor to output a saturation current. The control circuit is further configured to determine a value of a second bit line voltage for driving the memory cells according to the saturation current. In addition, an operating method and a memory cell array of the resistive memory apparatus are also provided.
    Type: Application
    Filed: December 28, 2023
    Publication date: April 25, 2024
    Applicant: Winbond Electronics Corp.
    Inventors: Ming-Che Lin, Min-Chih Wei, Ping-Kun Wang, Yu-Ting Chen, Chih-Cheng Fu, Chang-Tsung Pai
  • Publication number: 20240126174
    Abstract: A method includes the following steps. A photoresist is exposed to a first light-exposure through a first mask, wherein the first mask includes a first stitching region, and a first portion of the photoresist corresponding to a first opaque portion of the first stitching region is unexposed. The photoresist is exposed to a second light-exposure through a second mask, wherein the second mask includes a second stitching region, and a second portion of the photoresist corresponding to a second opaque portion of the second stitching region is unexposed and is overlapping with the first portion of the photoresist.
    Type: Application
    Filed: December 28, 2023
    Publication date: April 18, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Che Tu, Po-Han Wang, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo
  • Publication number: 20240130104
    Abstract: A semiconductor structure including a substrate, a first dielectric layer disposed on the substrate, a second dielectric layer disposed on the first dielectric layer and in physical contact with the first dielectric layer, an opening on the substrate and having a lower portion through the first dielectric layer and an upper portion through the second dielectric layer, an conductive layer disposed on the second dielectric layer at two sides of the opening and in physical contact with the second dielectric layer, a contact structure disposed in the lower portion of the opening, and a passivation layer covering a top surface of the contact structure, a sidewall of the second dielectric layer, and a sidewall of the conductive layer.
    Type: Application
    Filed: December 27, 2023
    Publication date: April 18, 2024
    Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yi-Wang Jhan, Fu-Che Lee, Gang-Yi Lin, An-Chi Liu, Yifei Yan, Yu-Cheng Tung
  • Publication number: 20240120338
    Abstract: A semiconductor device structure is provided. The semiconductor device has a first dielectric wall between an n-type source/drain region and a p-type source/drain region to physically and electrically isolate the n-type source/drain region and the p-type source/drain region from each other. A second dielectric wall is formed between a first channel region connected to the n-type source/drain region and a second channel region connected to the p-type source/drain region. A contact is formed to physically and electrically connect the n-type source/drain region with the p-type source/drain region, wherein the contact extends over the first dielectric wall. The first electric wall has a gradually decreasing width W5 towards a tip of the dielectric wall from a top contact position between the first dielectric wall and either the n-type source/drain region or the p-type source/drain region.
    Type: Application
    Filed: February 15, 2023
    Publication date: April 11, 2024
    Inventors: Ta-Chun LIN, Ming-Che CHEN, Yu-Hsuan LU, Chih-Hao CHANG
  • Publication number: 20240113345
    Abstract: A battery module and a short protection method thereof are provided. The battery module has a battery cell pack and a control circuit. The method includes: detecting a temperature of the battery cell pack as a battery cell temperature through the control circuit; determining whether the battery cell temperature shows a downward trend when the battery cell temperature is higher than a first predetermined temperature value; and deactivating the battery module when the battery cell temperature does not show the downward trend.
    Type: Application
    Filed: May 23, 2023
    Publication date: April 4, 2024
    Applicant: ASUSTeK COMPUTER INC.
    Inventors: Chunyen Lai, Yu-Cheng Shen, Chun Tsao, Chaochan Tan, Huichuan Lo, Wen-Che Chung, Ming Hung Yao
  • Publication number: 20240101847
    Abstract: A quantum dot oil-based ink is provided. The quantum dot oil-based ink includes a quantum dot material, a dispersing solvent, a viscosity modifier, and a surface tension modifying solution. The dispersing solvent includes a linear alkane having 6 to 14 carbon atoms. The viscosity modifier includes an aromatic hydrocarbon having 10 to 18 carbon atoms or a linear olefin having 16 to 20 carbon atoms. The surface tension modifying solution includes a hydrophobic polymer material and a nonpolar solvent.
    Type: Application
    Filed: November 29, 2022
    Publication date: March 28, 2024
    Inventors: Chun Che LIN, Chong-Ci HU, Yi-Ting TSAI, Ching-Yi CHEN, Yu-Chun LEE
  • Publication number: 20240085667
    Abstract: A photolithography projection lens, having a plurality of lens elements and a light diaphragm arranged among them, arranged along an optical axis, and comprising an object side and an image side respectively arranged at the front and rear ends of the plurality of lens elements; wherein: the diopters of the two lenses respectively near the object side and the image side must be positive; each of the lens elements is a single lens without cement; the angle between the chief rays at different image height positions and the optical axis is <1 degree, and the angle between the chief rays at different object height positions and the optical axis is <1 degree; and under the projection of 350˜450 nm wavelength light, it provide the imaging effect of precise magnification.
    Type: Application
    Filed: September 14, 2022
    Publication date: March 14, 2024
    Inventors: SHENG CHE WU, YU HUNG CHOU, YI HUA LIN, YUAN HUNG SU
  • Publication number: 20240081077
    Abstract: A transistor includes a first semiconductor layer, a second semiconductor layer, a semiconductor nanosheet, a gate electrode and source and drain electrodes. The semiconductor nanosheet is physically connected to the first semiconductor layer and the second semiconductor layer. The gate electrode wraps around the semiconductor nanosheet. The source and drain electrodes are disposed at opposite sides of the gate electrode. The first semiconductor layer surrounds the source electrode, the second semiconductor layer surrounds the drain electrode, and the semiconductor nanosheet is disposed between the source and drain electrodes.
    Type: Application
    Filed: September 1, 2022
    Publication date: March 7, 2024
    Applicants: Taiwan Semiconductor Manufacturing Company, Ltd., National Yang Ming Chiao Tung University
    Inventors: Po-Tsun Liu, Meng-Han Lin, Zhen-Hao Li, Tsung-Che Chiang, Bo-Feng Young, Hsin-Yi Huang, Sai-Hooi Yeong, Yu-Ming Lin
  • Patent number: 11919284
    Abstract: A rotary seat including a base includes an outer surface, and a composite material layer attached to at least a part of the outer surface. The base also includes a recess for accommodating a turntable and including a first opening on the outer surface. The material of the composite material layer includes fibers and a resin. Therefore, the rotary seat may be more lightweight. A rotary table is also provided and includes the rotary seat, a driving device which drives the rotary seat to rotate, and a turntable which is rotatably disposed in the recess of the base.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: March 5, 2024
    Assignee: Hiwin Technologies Corp.
    Inventors: Yung-Tsai Chuo, Yaw-Zen Chang, Jui-Che Lin, Yu-Hsien Ho, Yu Liu
  • Patent number: 11913925
    Abstract: A sensing device is provided. The sensing device includes a processing circuit and a multi-sensor integrated single chip. The multi-sensor integrated single chip includes a substrate and a temperature sensor, a pressure sensor, and an environmental sensor disposed on the substrate. The temperature sensor senses temperature. The pressure sensor senses pressure. The environmental sensor senses an environmental state. The processing circuit obtains a first sensed temperature value from the temperature sensor when the environmental sensor does not operate, and it obtains a second sensed temperature value from the temperature sensor when the environmental sensor operates. The processing circuit obtains a sensed pressure value from the pressure sensor. The processing circuit obtains at least one temperature calibration reference of the pressure sensor according to the first and second sensed temperature values and calibrates the sensed pressure value according to the temperature calibration reference.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: February 27, 2024
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Ying-Che Lo, Yu-Sheng Lin, Po-Jen Su, Ting-Hao Hsiao
  • Patent number: 11917339
    Abstract: A light engine includes an image surface, a projected light surface, a projection lens assembly, and a plurality of folding elements. The image surface has three image areas. The projected light surface has three light sources that provide light with different wavelengths. The plurality of folding elements are arranged along a light emitting axis. The image surface and the projected light surface are substantially in parallel with the light emitting axis, and there is an air gap located between the image surface and the projected light surface. The three light sources respectively correspond to the plurality of folding elements and respectively correspond to the three image areas, and the light emitting axis and the projection lens assembly are disposed on the same optical path.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: February 27, 2024
    Assignee: LARGAN PRECISION CO., LTD.
    Inventors: Yu Jie Hong, Chun-Che Hsueh, Fuh-Shyang Yang
  • Publication number: 20240039149
    Abstract: An electronic device includes a first antenna, a second antenna, and an interference reduction device. The first antenna is arranged at a first position. The second antenna is arranged at a second position. The second position is different from the first position. The interference reduction device is arranged at a third position. The third position is different from the first position and the second position. The interference reduction device includes a structural feature configured to couple an electromagnetic wave and reduce radiation of the electromagnetic wave.
    Type: Application
    Filed: July 28, 2023
    Publication date: February 1, 2024
    Inventors: Yu-Che LIN, Jing NIE
  • Patent number: 11881864
    Abstract: An all-digital phase-locked loop (ADPLL) and a calibration method thereof are provided. The ADPLL includes a digitally controlled oscillator (DCO), a time-to-digital converter (TDC) coupled to the DCO, and a normalization circuit coupled to the TDC. The DCO is configured to generate a clock signal according to a frequency control signal. The TDC is configured to generate a digital output signal according to a phase error between the clock signal and a reference signal. The normalization circuit is configured to convert the digital output signal into a clock phase value according to a gain parameter. More particularly, the normalization circuit may modify the gain parameter according to a phase error value between the clock phase value and a reference phase value.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: January 23, 2024
    Assignee: Realtek Semiconductor Corp.
    Inventor: Yu-Che Yang
  • Patent number: 11838027
    Abstract: An all-digital phase-locked loop (ADPLL) and a calibration method thereof are provided. The ADPLL includes a digitally controlled oscillator (DCO), a time-to-digital converter (TDC) coupled to the DCO, and a normalization circuit coupled to the TDC. The TDC is configured to generate a clock signal according to a frequency control signal. The TDC is configured to generate a digital output signal according to a phase difference between the clock signal and a reference signal. The normalization circuit is configured to convert the digital output signal into a clock phase value according to a gain parameter. The normalization circuit selects one of a plurality of candidate gain parameters stored in the normalization circuit in response to the digital output signal, for being utilized as the gain parameter.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: December 5, 2023
    Assignee: Realtek Semiconductor Corp.
    Inventor: Yu-Che Yang
  • Publication number: 20230371233
    Abstract: Techniques are provided herein for forming multi-tier memory structures with graded characteristics across different tiers. A given memory structure includes memory cells, with a given memory cell having an access device and a storage device. The access device may include, for example, a thin film transistor (TFT) structure, and the storage device may include a capacitor. Certain geometric or material parameters of the memory structures can be altered in a graded fashion across any number of tiers to compensate for process effects that occur when fabricating a given tier, which also affect any lower tiers. This may be done to more closely match the performance of the memory arrays across each of the tiers.
    Type: Application
    Filed: May 12, 2022
    Publication date: November 16, 2023
    Applicant: Intel Corporation
    Inventors: Abhishek Anil Sharma, Travis W. Lajoie, Forough Mahmoudabadi, Shailesh Kumar Madisetti, Van H. Le, Timothy Jen, Cheng Tan, Jisoo Kim, Miriam R. Reshotko, Vishak Venkatraman, Eva Vo, Yue Zhong, Yu-Che Chiu, Moshe Dolejsi, Lorenzo Ferrari, Akash Kannegulla, Deepyanti Taneja, Mark Armstrong, Kamal H. Baloch, Afrin Sultana, Albert B. Chen, Vamsi Evani, Yang Yang, Juan G. Alzate-Vinasco, Fatih Hamzaoglu
  • Patent number: 11817397
    Abstract: A semiconductor device package and a method for manufacturing a semiconductor device package are provided. The semiconductor device package includes a carrier, a sensor module, a connector, and a stress buffer structure. The sensor module is disposed on the carrier. The connector is connected to the carrier. The stress buffer structure connects the connector to the sensor module.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: November 14, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chi Sheng Tseng, Lu-Ming Lai, Hui-Chung Liu, Yu-Che Huang