Patents by Inventor Yu Che

Yu Che has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11455941
    Abstract: A control device includes a signal-output device, a signal modulation device, a storage device, and a processing device. The signal-output device outputs a plurality of data signals. The signal modulation device outputs a plurality of modulation signals. The storage device is coupled to the signal-output device and stores a large amount of display data. The processing device is coupled to the signal-output device and the signal modulation device. The processing device controls the signal-output device so that the signal-output device divides the display data and transforms the display data into the data signals according to the repeat performing number and the moving position region, so as to sequentially output the data signals. The processing device controls the signal modulation device, so that the signal modulation device sequentially outputs the modulation signals according to the pulse wave counting number and the pixel unit number.
    Type: Grant
    Filed: November 4, 2020
    Date of Patent: September 27, 2022
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventors: Chun-Hao Huang, Yu-Che Hsieh
  • Patent number: 11440215
    Abstract: A method of making a wooden board assembly includes A) determining a scrap portion of a trunk; B) cutting the trunk horizontally to form multiple boards; C) removing narrow scraps and trimmed sections of each of the multiple boards to obtain multiple trimmed wide boards, and cutting narrow board areas from the scrap portion to form multiple peripheral boards; D) removing a part of the scrap portion and two trimmed sections from each of the multiple peripheral boards; E) connecting the multiple trimmed wide boards and the multiple peripheral boards to form a substrate; F) adhering two straps on the substrate to produce a wood pattern assembly; G) cutting the wood pattern assembly to form multiple cut films; H) adhering one of the multiple cut films with a nonwoven fabric with a transparent adhesive and connecting the multiple cut films on a fixing lamination; and I) cutting the fixing lamination.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: September 13, 2022
    Assignee: Juan Wood Building Materials Co., Ltd.
    Inventor: Yu-Che Huang
  • Publication number: 20220281132
    Abstract: A method of making a wooden board assembly includes A) determining a scrap portion of a trunk; B) cutting the trunk horizontally to form multiple boards; C) removing narrow scraps and trimmed sections of each of the multiple boards to obtain multiple trimmed wide boards, and cutting narrow board areas from the scrap portion to form multiple peripheral boards; D) removing a part of the scrap portion and two trimmed sections from each of the multiple peripheral boards; E) connecting the multiple trimmed wide boards and the multiple peripheral boards to form a substrate; F) adhering two straps on the substrate to produce a wood pattern assembly; G) cutting the wood pattern assembly to form multiple cut films; H) adhering one of the multiple cut films with a nonwoven fabric with a transparent adhesive and connecting the multiple cut films on a fixing lamination; and I) cutting the fixing lamination.
    Type: Application
    Filed: March 5, 2021
    Publication date: September 8, 2022
    Inventor: Yu-Che Huang
  • Patent number: 11430906
    Abstract: An optical device includes a substrate, an electronic component and a lid. The electronic component is disposed on the substrate. The lid is disposed on the substrate. The lid has a first cavity over the electronic component and a second cavity over the first cavity. The sidewall of the second cavity is inclined.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: August 30, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chang Chin Tsai, Yu-Che Huang, Hsun-Wei Chan
  • Patent number: 11410893
    Abstract: The semiconductor structure includes a substrate, a deep well, a first doped region, a source/drain region, and a first heavily doped region. The substrate has a first conductivity type. The deep well has a second conductivity type disposed on the substrate. The first doped region has the first conductivity type disposed on the deep well. The source/drain region has the second conductivity type disposed on the first doped region. The first heavily doped region has the second conductivity type disposed in a first top region of the source/drain region, in which the first conductivity type is opposite to the second conductivity type.
    Type: Grant
    Filed: January 31, 2021
    Date of Patent: August 9, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Yu-Che Li, Tsang-Po Yang, Hsueh-Han Lu
  • Patent number: 11410915
    Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a carrier, a first encapsulant, and an interposer. The first encapsulant is on the carrier and defines a cavity. The interposer is disposed between the first encapsulant and the cavity. The first encapsulant covers a portion of the interposer.
    Type: Grant
    Filed: November 3, 2020
    Date of Patent: August 9, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yu-Che Huang, Chang Chin Tsai
  • Publication number: 20220246485
    Abstract: The semiconductor structure includes a substrate, a deep well, a first doped region, a source/drain region, and a first heavily doped region. The substrate has a first conductivity type. The deep well has a second conductivity type disposed on the substrate. The first doped region has the first conductivity type disposed on the deep well. The source/drain region has the second conductivity type disposed on the first doped region. The first heavily doped region has the second conductivity type disposed in a first top region of the source/drain region, in which the first conductivity type is opposite to the second conductivity type.
    Type: Application
    Filed: January 31, 2021
    Publication date: August 4, 2022
    Inventors: Yu-Che LI, Tsang-Po YANG, Hsueh-Han LU
  • Publication number: 20220215207
    Abstract: A training method for video stabilization and an image processing device using the same are proposed. The method includes the following steps. An input video including low dynamic range (LDR) images is received. The LDR images are converted to high dynamic range (HDR) images by using a first neural network. A feature extraction process is performed to obtain features based on the LDR images and the HDR images. A second neural network for video stabilization is trained according to the LDR images and the HDR images based on a loss function by minimizing a loss value of the loss function to generate stabilized HDR images in a time-dependent manner, where the loss value of the loss function depends upon the features. An HDR classifier is constructed according to the LDR images and the HDR images. The stabilized HDR images are classified by using the HDR classifier to generate a reward value, where the loss value of the loss function further depends upon the reward value.
    Type: Application
    Filed: March 23, 2022
    Publication date: July 7, 2022
    Applicant: Novatek Microelectronics Corp.
    Inventors: Jen-Huan Hu, Wei-Ting Chen, Yu-Che Hsiao, Shih-Hsiang Lin, Po-Chin Hu, Yu-Tsung Hu, Pei-Yin Chen
  • Patent number: 11373060
    Abstract: A training method for video stabilization and an image processing device using the same are proposed. The method includes the following steps. An input video including low dynamic range (LDR) images is received. The LDR images are converted to high dynamic range (HDR) images by using a first neural network. A second neural network for video stabilization is trained to generate stabilized HDR images in a time-dependent manner.
    Type: Grant
    Filed: May 25, 2020
    Date of Patent: June 28, 2022
    Assignee: Novatek Microelectronics Corp.
    Inventors: Jen-Huan Hu, Wei-Ting Chen, Yu-Che Hsiao, Shih-Hsiang Lin, Po-Chin Hu, Yu-Tsung Hu, Pei-Yin Chen
  • Publication number: 20220199550
    Abstract: A semiconductor device package and a method for manufacturing a semiconductor device package are provided. The semiconductor device package includes a carrier, a sensor module, a connector, and a stress buffer structure. The sensor module is disposed on the carrier. The connector is connected to the carrier. The stress buffer structure connects the connector to the sensor module.
    Type: Application
    Filed: December 21, 2020
    Publication date: June 23, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chi Sheng TSENG, Lu-Ming LAI, Hui-Chung LIU, Yu-Che HUANG
  • Patent number: 11336943
    Abstract: A method and an electronic device for detecting the resolution of a video material are provided. The method is applied to an electronic device, and a calculation circuit of the electronic device executes an AI model. The video material includes multiple frames, and each frame includes multiple sub-frames. The AI model processes multiple pixel data to generate an intermediate resolution corresponding to the pixel data. The method includes the following steps: (A) generating a target sub-frame, the number of pixels of the target sub-frame being smaller than the number of pixels in any frame; (B) inputting the target sub-frame into the AI model to generate the intermediate resolution; (C) storing the intermediate resolution; (D) repeating steps (A) to (C) to generate multiple intermediate resolutions; and (E) determining the resolution of the video material based on the intermediate resolutions.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: May 17, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Ching-Lung Chen, Yu-Che Kao
  • Publication number: 20220139812
    Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a carrier, a first encapsulant, and an interposer. The first encapsulant is on the carrier and defines a cavity. The interposer is disposed between the first encapsulant and the cavity. The first encapsulant covers a portion of the interposer.
    Type: Application
    Filed: November 3, 2020
    Publication date: May 5, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yu-Che HUANG, Chang Chin TSAI
  • Publication number: 20220113303
    Abstract: The present invention provides a magnetic-control measurement system, comprises a reaction container and a programable magnetron measurement unit.
    Type: Application
    Filed: October 8, 2021
    Publication date: April 14, 2022
    Inventors: Tzong-Rong Ger, Hong-Siang Wang, Yu-Che Cheng, Hsing-Cheng Chu, Jing-Wen Tsai, Chia-Ke Tsou
  • Patent number: 11303286
    Abstract: The present invention provides a sub-sampling PLL including a first phase detector, a first charge pump, an oscillator and a first buffer is disclosed. In the operations of the sub-sampling PLL, the first phase detector uses a reference clock signal to sample a feedback signal to generate a first phase detection result, the first charge pump generates a first signal according to the first phase detection result and a pulse signal, the oscillator generates an output clock signal according to the first signal, and the first buffer receives the output clock signal to generate the feedback signal, and buffer further using a slew rate control signal to control a slew rate of the feedback signal.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: April 12, 2022
    Assignee: Realtek Semiconductor Corp.
    Inventors: Yu-Che Yang, Ka-Un Chan, Yong-Ru Lu, Shen-Iuan Liu
  • Patent number: 11294779
    Abstract: A memory device includes a non-volatile memory chip, a connector and a memory controller. The non-volatile memory chip includes an access partition and a hidden partition. The memory controller is used to set first logical blocks mapping to mapping physical blocks in the access partition. The memory controller is used to maintain a first mapping table recording the first logical blocks and the mapping physical blocks. During backup, the memory controller is used to duplicate data in the mapping physical blocks to the hidden partition according to the first mapping table to form backup physical blocks, and establish a second mapping table setting second logical blocks to map to the backup physical blocks. During recovery, the memory controller is used to map the second logical blocks to the backup physical blocks according to the second mapping table for the host system to recover an environment set at the backup operation.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: April 5, 2022
    Assignee: Apacer Technology Inc.
    Inventors: Yu-Che Lee, Jiunn-Chang Lee
  • Publication number: 20220067349
    Abstract: A face recognition method for an edge device is provided. Firstly, a recognition data is received from a computing device through a wireless network. Then, a trained model is retrieved from the recognition data. Then, the trained model is stored. Then, a face detection operation is performed to acquire a face image and a face temperature of a detected face. When the face temperature is within a human body temperature range and the face image complies with the trained model, the edge device confirms that the detected face is a face of a real person and the real person is a known user.
    Type: Application
    Filed: August 24, 2021
    Publication date: March 3, 2022
    Inventors: Yu-Kai Kuan, Yu-Che Tsai
  • Publication number: 20220068747
    Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a semiconductor package device, a first constraint structure and a second constraint structure. The first constraint structure is connected to the semiconductor package device. The second constraint structure is connected to the semiconductor package device and under a projection of the semiconductor package device.
    Type: Application
    Filed: August 28, 2020
    Publication date: March 3, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yu-Che HUANG, Lu-Ming LAI, Ying-Chung CHEN
  • Patent number: 11246883
    Abstract: Methods for ameliorating cardiac is juries such as myocardial infarction by either enhancing the activity of a let-7 microRNA or inhibiting the activity of transformation growth factor beta receptor III (T GFBR3). Also provided herein are assay methods for detecting the level of TGFBR3, the level of a let-7 microRNA, or both in a biological sample.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: February 15, 2022
    Assignee: Academia Sinica
    Inventors: Patrick C. H. Hsieh, Chen-Yun Chen, Yu-Che Cheng
  • Publication number: 20220043724
    Abstract: A memory device includes a non-volatile memory chip, a connector and a memory controller. The non-volatile memory chip includes an access partition and a hidden partition. The memory controller is used to set first logical blocks mapping to mapping physical blocks in the access partition. The memory controller is used to maintain a first mapping table recording the first logical blocks and the mapping physical blocks. During backup, the memory controller is used to duplicate data in the mapping physical blocks to the hidden partition according to the first mapping table to form backup physical blocks, and establish a second mapping table setting second logical blocks to map to the backup physical blocks. During recovery, the memory controller is used to map the second logical blocks to the backup physical blocks according to the second mapping table for the host system to recover an environment set at the backup operation.
    Type: Application
    Filed: November 13, 2020
    Publication date: February 10, 2022
    Inventors: Yu-Che Lee, Jiunn-Chang Lee
  • Publication number: 20210398266
    Abstract: An object appearance detection system with posture detection and a control method thereof are provided. A controlling and computing device uses a first sensor and a second sensor to control a conveying production line, and controls a robotic arm to move an object to be detected to a posture detection position and a surface detection position. When the object to be detected is in the posture detection position, the controlling and computing device receives a posture detection image to perform posture detection on the object to be detected. When the object to be detected is in the surface detection position, the controlling and computing device controls the robotic arm to adjust the posture of the object to be detected according to the posture detection result and receives images from a remote imaging device and photographing devices to perform surface defect detection on the object to be detected.
    Type: Application
    Filed: June 20, 2020
    Publication date: December 23, 2021
    Inventors: Hsien-I LIN, Yu-Che HUANG, FAUZY SATRIO WIBOWO, YUDA RISMA WAHYUDI