Abstract: A training method for video stabilization and an image processing device using the same are proposed. The method includes the following steps. An input video including low dynamic range (LDR) images is received. The LDR images are converted to high dynamic range (HDR) images by using a first neural network. A feature extraction process is performed to obtain features based on the LDR images and the HDR images. A second neural network for video stabilization is trained according to the LDR images and the HDR images based on a loss function by minimizing a loss value of the loss function to generate stabilized HDR images in a time-dependent manner, where the loss value of the loss function depends upon the features. An HDR classifier is constructed according to the LDR images and the HDR images. The stabilized HDR images are classified by using the HDR classifier to generate a reward value, where the loss value of the loss function further depends upon the reward value.

Abstract: A method includes forming a 2-D material layer over a substrate, wherein the 2-D material layer comprises transition metal atoms and chalcogen atoms; forming a gate structure over the 2-D material layer; supplying chemical molecules to the 2-D material layer, such that atoms of the chemical molecules react with portions of the chalcogen atoms to weaken covalent bonds between the portions of the chalcogen atoms and the transition metal atoms; and forming source/drain contacts over the 2-D material layer, wherein contact metal atoms of the source/drain contacts form metallic bonds with the transition metal atoms of the 2-D material layer.

Abstract: A face recognition method for an edge device is provided. Firstly, a recognition data is received from a computing device through a wireless network. Then, a trained model is retrieved from the recognition data. Then, the trained model is stored. Then, a face detection operation is performed to acquire a face image and a face temperature of a detected face. When the face temperature is within a human body temperature range and the face image complies with the trained model, the edge device confirms that the detected face is a face of a real person and the real person is a known user.

Abstract: An all-digital phase-locked loop (ADPLL) circuit and a calibration method thereof are provided. The ADPLL circuit includes a digitally controlled oscillator (DCO) circuit, a phase detector circuit, and a calibration circuit coupled between the DCO circuit and the phase detector circuit. The DCO circuit generates a clock signal according to a frequency control signal. The phase detector circuit generates a phase error value according to a reference signal and the clock signal. More particularly, after the ADPLL circuit performs a locking operation for a period of time, the frequency control signal is tied at a locked value which is obtained when the ADPLL circuit performs the locking operation, and the calibration circuit may modify a current of at least one current source within the DCO circuit according to the phase error value.

Abstract: An integrated circuit (IC) includes a transistor, and a first layer including electrically conductive material. In an example, the first layer is conductively coupled to the transistor. The IC further includes a second layer including electrically conductive material above the first layer. The IC further includes one or more intervening layers between the first and second layers. In an example, the one or more intervening layers include at least a third layer, wherein the third layer includes (i) a first metal, (ii) oxygen, and (iii) one or both of a second metal or an oxide thereof within the third layer. In an example, the first layer, the second layer, and the one or more intervening layers form a metal-insulator-metal (MIM) capacitor. In an example, the MIM capacitor and the transistor, in combination, form a memory cell of a dynamic random access memory (DRAM) array.

Abstract: The present invention introduces a new hybrid thermal energy harvesting device that combines electrochemistry and semiconductors to achieve simultaneous high saturation thermo-voltage and high current density. This innovation demonstrates the synergistic effect of integrating semiconductors, commonly used in solid-state thermoelectrics for high current density, with ion-conducting polymer electrolytes, known for their high thermo-voltage. The device ensures constant high-power output from continuous or periodic heat sources. It directly converts heat into electricity for immediate use or stores electricity derived from low-grade temperature differentials and temperature ranges for later discharge. It exhibits characteristics resembling both photovoltaics and capacitors simultaneously.

Abstract: An electronic device is provided. The electronic device includes a substrate, a first gate circuit, a second gate circuit, a signal line, and a shielding layer. The substrate includes a display area and a peripheral area. The first gate circuit is disposed in the peripheral area. The second gate circuit is disposed in the peripheral area. The signal line is coupled between the first gate circuit and the second gate circuit. The signal line includes a specific line segment, and the specific line segment overlaps the display area. The shielding layer is disposed in the display area. The shielding layer overlaps the specific line segment.

Abstract: The present invention discloses a neural network construction method having average quantization mechanism that includes steps outlined below. A weight combination included in each of network layers of a neural network is retrieved. A loss function is generated according to the weight combination of all the network layers and target values. Corresponding to each network layers, a Gini coefficient of the weight combination is calculated and the Gini coefficients corresponding to all the network layers are accumulated as a regularized correction term. The loss function and the regularized correction term are merged as a regularized loss function to perform training on the neural network accordingly to generate a trained weight combination of each of the network layers. A quantization is performed on the trained weight combination of each of the network layers to generate a quantized neural network, in which each of the network layers thereof includes the trained weight combination.

Abstract: The present invention provides a pressure-sensitive adhesive composition, including: an acrylic copolymer and a crosslinking agent. The acrylic copolymer is a reaction product of a mixture of the following monomers: a first alkyl (meth)acrylate, an alkyl group in the first alkyl (meth)acrylate having at least 6 carbon atoms; a second alkyl (meth)acrylate, an alkyl group in the second alkyl (meth)acrylate having 1 to 5 carbon atoms; and a vinyl carboxylic acid, the weight ratio of the vinyl carboxylic acid to the mixture being 4% to 5%. The crosslinking agent is an organometallic chelating agent. The weight ratio of the organometallic chelating agent to the mixture is 0.05% to 0.25%. The pressure-sensitive adhesive composition does not contain an effective amount of a tackifier. The present invention further provides a pressure-sensitive adhesive solution, a pressure-sensitive adhesive tape, and a method for preparing the same.

Abstract: A laminating auxiliary jig includes a base having an accommodating recess, and a pressing plate pivotably attached to the base and having a positioning trough. When the pressing plate is opened, it is separated from the accommodating recess, which a first composite material is put into. When the pressing plate is closed, it is located in the accommodating recess and pressed on the first composite material, the positioning trough communicates with the accommodating recess, and at least one middle foam material is put into the positioning trough to be positioned and attached to the first composite material. When the pressing plate is opened again, a second composite material is put into the accommodating recess to be attached to the middle foam material. Therefore, the laminating auxiliary jig helps a user quickly complete laminating the multilayer composite material. The method of using the laminating auxiliary jig is also provided.

Abstract: The present disclosure provides an optical module. The optical module includes an optical component disposed in or on a carrier and configured to receive a first light. The optical component is further configured to transmit a second light to a first portion of the carrier and transmit a third light to a second portion of the carrier.

Abstract: A heel cap manufacturing method includes the steps of: a) preparing a multilayer composite material; b) performing the first time of molding by thermal pressing to the multilayer composite material by a thermal pressing device to obtain a thermal pressed semi-product; c) taking out the thermal pressed semi-product from the thermal pressing device and fixing it to a heel cap mold; d) performing the second time of molding by cold pressing to the thermal pressed semi-product together with the heel cap mold in a cooling device to obtain a cooled semi-product; and e) demolding and rewarming the cooled semi-product to obtain a finished heel cap. The present invention uses the processing manner of molding twice by cold and thermal pressing to manufacture the structurally more complex heel cap, effectively lowering difficulty of the manufacturing process and raising production efficiency. A heel cap manufacturing equipment is also provided.

Abstract: An all-digital phase-locked loop (ADPLL) and a calibration method thereof are provided. The ADPLL includes a digitally controlled oscillator (DCO), a time-to-digital converter (TDC) coupled to the DCO, and a normalization circuit coupled to the TDC. The TDC is configured to generate a clock signal according to a frequency control signal. The TDC is configured to generate a digital output signal according to a phase difference between the clock signal and a reference signal. The normalization circuit is configured to convert the digital output signal into a clock phase value according to a gain parameter. The normalization circuit selects one of a plurality of candidate gain parameters stored in the normalization circuit in response to the digital output signal, for being utilized as the gain parameter.

Abstract: A semiconductor device package and a method for packaging the same are provided. A semiconductor device package includes a carrier, an electronic component, a buffer layer, a reinforced structure, and an encapsulant. The electronic component is disposed over the carrier and has an active area. The buffer layer is disposed on the active area of the electronic component. The reinforced structure is disposed on the buffer layer. The encapsulant encapsulates the carrier, the electronic component and the reinforced structure.

Abstract: An integrated circuit device includes a semiconductor substrate, a first gate structure, a channel layer, source and drain features, a second gate structure, a first contact, and a second contact. The first gate structure is over the semiconductor substrate. The first gate structure includes a gate dielectric layer and a first gate electrode. The channel layer is over and surrounded by the first gate structure. The source and drain features are respectively on opposite first and second sides of the channel layer. The second gate structure is over the channel layer. The second gate structure includes a programming gate dielectric layer having a data storage layer and a second gate electrode over the programming gate dielectric layer. The first gate contact is on the first gate electrode. The second gate contact is on the second gate electrode.

Abstract: An optical device includes a substrate, an electronic component and a lid. The electronic component is disposed on the substrate. The lid is disposed on the substrate. The lid has a first cavity over the electronic component and a second cavity over the first cavity. The sidewall of the second cavity is inclined.

Abstract: An all-digital phase-locked loop (ADPLL) and a calibration method thereof are provided. The ADPLL includes a digitally controlled oscillator (DCO), a time-to-digital converter (TDC) coupled to the DCO, and a normalization circuit coupled to the TDC. The DCO is configured to generate a clock signal according to a frequency control signal. The TDC is configured to generate a digital output signal according to a phase error between the clock signal and a reference signal. The normalization circuit is configured to convert the digital output signal into a clock phase value according to a gain parameter. More particularly, the normalization circuit may modify the gain parameter according to a phase error value between the clock phase value and a reference phase value.

Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a semiconductor package device, a first constraint structure and a second constraint structure. The first constraint structure is connected to the semiconductor package device. The second constraint structure is connected to the semiconductor package device and under a projection of the semiconductor package device.

Abstract: A heat capacitor with simple structure, easy to manufacture and high thermoelectric conversion efficiency is provided. The heat capacitor includes: a pair of electrodes, at least one said electrode being a carbonaceous electrode; and a thermoelectric electrolyte disposed between the pair of electrodes, wherein the distance between the pair of electrodes is at most 1 mm.

Abstract: An all-digital phase-locked loop (ADPLL) circuit and a calibration method thereof are provided. The ADPLL circuit includes a digitally controlled oscillator (DCO) circuit, a phase detector circuit, and a calibration circuit coupled between the DCO circuit and the phase detector circuit. The DCO circuit generates a clock signal according to a frequency control signal. The phase detector circuit generates a phase error value according to a reference signal and the clock signal. More particularly, after the ADPLL circuit performs a locking operation for a period of time, the frequency control signal is tied at a locked value which is obtained when the ADPLL circuit performs the locking operation, and the calibration circuit may modify a current of at least one current source within the DCO circuit according to the phase error value.