Abstract: A wearable electronic device with a function of detecting a wearing state, comprising: at least one electrode; a capacitance calculating circuit, coupled to the electrode, configured to calculate a capacitance variation generated by at least one of the electrode; and a wearing state determining circuit, coupled to the capacitance calculating circuit, configured to determine the wearing state according to the capacitance variation. By this way, the wearing state can be auto detected and the wearable electronic device can be correspondingly control according to the wearing state.

Abstract: A driving mechanism for moving an optical element is provided, including a housing, a frame, a holder, and a driving assembly. The frame is fixed to the housing and forms a depressed surface adjacent to the housing. Specifically, the depressed surface faces the housing and is not in contact with the housing. The holder is movably disposed in the housing for holding the optical element. The drive assembly is disposed in the housing to drive the holder and the optical element to move relative to the frame.

Abstract: The present disclosure provides a control method for a touch device. The control method of the touch device allows the plurality of pressure sensors to be activated to detect the pressure on the touch position of the touch panel while the capacitive touch sensor is probably invalid and the touch device is abnormal. Therefore, the touch device works continuously when the capacitive touch sensor is probably invalid.

Abstract: A driving mechanism is provided, including a case, a holder and a driving module. The holder is disposed in the case for holding an optical member. The driving module is disposed in the case for driving the holder. The case is substantially quadrilateral and includes a first side and a second side. The driving module includes a first magnetic driving component winding on a periphery of the holder. The first magnetic driving component includes a first segment and a second segment that are respectively substantially parallel to the first side and the second side. The distance between the first segment and the first side is different from the distance between the second segment and the second side.

Abstract: An immunoconjugate includes an anti-Globo H antibody, or a binding fragment thereof, and a therapeutic agent or a label, having the formula: Ab?(L?D)m, wherein Ab is the anti-Globo H antibody or the binding fragment thereof, L is a linker or a direct bond, D is the therapeutic agent or the label, and m is an integer from 1 to 8. The antibody may be a monoclonal antibody, which may be a humanized antibody. A method for treating a cancer includes administering to a subject in need of such treatment a pharmaceutically effective amount of an immunoconjugate containing an antibody against Globo H, or a binding fragment thereof, and a therapeutic agent covalently conjugated with the antibody.

Abstract: Various embodiments of the present application are directed towards an integrated memory chip with an enhanced device-region layout for reduced leakage current and an enlarged word-line etch process window (e.g., enhanced word-line etch resiliency). In some embodiments, the integrated memory chip comprises a substrate, a control gate, a word line, and an isolation structure. The substrate comprises a first source/drain region. The control gate and the word line are on the substrate. The word line is between and borders the first source/drain region and the control gate and is elongated along a length of the word line. The isolation structure extends into the substrate and has a first isolation-structure sidewall. The first isolation-structure sidewall extends laterally along the length of the word line and underlies the word line.

Abstract: Various embodiments of the present application are directed towards an integrated memory chip comprising a memory array with a strap-cell architecture that reduces the number of distinct strap-cell types and that reduces strap-line density. In some embodiments, the memory array is limited to three distinct types of strap cells: a source line/erase gate (SLEG) strap cell; a control gate/word line (CGWL) strap cell; and a word-line strap cell. The small number of distinct strap-cell types simplifies design of the memory array and further simplifies design of a corresponding interconnect structure. Further, in some embodiments, the three distinct strap-cell types electrically couple word lines, erase gates, and control gates to corresponding strap lines in different metallization layers of an interconnect structure. By spreading the strap lines amongst different metallization layers, strap-line density is reduced.

Abstract: A data writing method, a memory controlling circuit unit and a memory storage device are provided. The method includes: receiving a plurality of data; writing the plurality of data into a first physical erasing unit by using a multi-page programming mode; and writing at least one first data of the plurality of data into a second physical erasing unit by using a single-page programming mode; verifying the plurality of data stored in the first physical erasing unit; and if the verification fails, performing a writing operation to a third physical erasing unit by using the multi-page programming mode according to the at least one first data and the plurality of data.

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. A lateral end of each of the first semiconductor layers has a V-shape cross section after the first semiconductor layers are laterally etched.

Abstract: A video conference system, a video conference apparatus and a video conference method are provided. The video conference system includes a video conference apparatus and a display apparatus. The video conference apparatus includes an image detection device, a sound source detection device, and a processor. The image detection device obtains a conference image of a conference space. When the sound source detection device detects a sound generated by a sound source in the conference space, the sound source detection device outputs a positioning signal. The processor receives the positioning signal, and determines whether a real face image exists in a sub-image block of the conference image corresponding to the sound source according to the positioning signal to output the image signal. The display apparatus displays a close-up conference image including the real face image according to the image signal.

Abstract: A transition structure for millimeter wave is provided. The transition structure includes a first layer signal element coupled to an end of a first transmission line and a plurality of first layer ground elements surrounding the end of the first transmission line equidistantly from the end of the first transmission line and disposed along two opposite sides of a strip body of the first transmission line equidistantly from the strip body of the first transmission line. The transition structure further includes an intermediate layer signal element coupled to the first layer signal element and a plurality of intermediate layer ground elements surrounding the intermediate layer signal element quasi-coaxially. A multilayer transition structure including a multilayer structure and the transition structure is also provided. Therefore, the problem of operating frequency caused by the thickness of the multilayer structure can be overcome, thereby increasing the resonance frequency of the multilayer structure.

Abstract: The present disclosure provides a control method for a touch device. The control method of the touch device allows the plurality of pressure sensors to be activated to detect the pressure on the touch position of the touch panel while the capacitive touch sensor is probably invalid and the touch device is abnormal. Therefore, the touch device works continuously when the capacitive touch sensor is probably invalid.

Abstract: A decoding method, a memory controlling circuit unit, and a memory storage device are provided. The method includes: reading a first physical programming unit by using a first read voltage to obtain first data; determining whether a first ratio of a first quantity of a first bit value and a second quantity of a second bit value in the first data is greater than a threshold; when the first ratio is not greater than the threshold, performing a decoding operation according to the first data to generate first decoded data and outputting the first decoded data; and when the first ratio is greater than the threshold, not performing the decoding operation according to the first data.

Abstract: A device includes a die paddle and a plurality of leads. The leads surround the die paddle. Each of the leads includes an inner lead portion adjacent to and spaced apart from the die paddle, an outer lead portion opposite to the inner lead portion and a bridge portion between the inner lead portion and the outer lead portion. The inner lead portion has an upper bond section connected to the bridge portion and a lower support section below the upper bond section. A sum of a thickness of the upper bond section and a thickness of the lower support section is greater than a thickness of the bridge portion.

Abstract: Various embodiments of the present application are directed towards an integrated memory chip with an enhanced device-region layout for reduced leakage current and an enlarged word-line etch process window (e.g., enhanced word-line etch resiliency). In some embodiments, the integrated memory chip comprises a substrate, a control gate, a word line, and an isolation structure. The substrate comprises a first source/drain region. The control gate and the word line are on the substrate. The word line is between and borders the first source/drain region and the control gate and is elongated along a length of the word line. The isolation structure extends into the substrate and has a first isolation-structure sidewall. The first isolation-structure sidewall extends laterally along the length of the word line and underlies the word line.

Abstract: A memory control method, a memory storage device and a memory control circuit unit are provided. The method includes: reading a first physical unit among a plurality of physical units based on a first electrical configuration to obtain first soft information; reading the first physical unit based on a second electrical configuration which is different from the first electrical configuration to obtain second soft information; classifying a plurality of memory cells in the first physical unit according to the first soft information and the second soft information; and decoding data read from the first physical unit according to a classification result of the memory cells.

Abstract: A data writing method, a memory controlling circuit unit and a memory storage device are provided. The method includes: receiving a plurality of data; writing the plurality of data into a first physical erasing unit by using a multi-page programming mode; and writing at least one first data of the plurality of data into a second physical erasing unit by using a single-page programming mode; verifying the plurality of data stored in the first physical erasing unit; and if the verification fails, performing a writing operation to a third physical erasing unit by using the multi-page programming mode according to the at least one first data and the plurality of data.

Abstract: A piezoelectric patch sensor for measuring muscle movement of contraction and extension is disclosed. The sensor is elongated and directly attached to a skin site of a user for the measuring via an interface circuit connected to a host processor. The piezoelectric patch sensor has an adhesive layer with an adhesive bottom surface for firmly attaching to the skin site. An elastic sheet is integrated on top of the adhesive layer. A piezoelectric thread is further integrated on top of the elastic sheet and has a bundle of aligned piezoelectric fibers. The thread is electrically coupled to the interface circuit via a pair of conductive wires, forming a piezoelectric measurement circuitry. Muscle movement under the skin site shrinks or extends the piezoelectric patch sensor in its entirety along the direction of muscle movement due to a corresponding shrinking or extending movement of the skin firmly attached to the adhesive layer.

Abstract: A video conference system, a video conference apparatus and a video conference method are provided. The video conference system includes a video conference apparatus and a display apparatus. The video conference apparatus includes an image detection device, a sound source detection device, and a processor. The image detection device obtains a conference image of a conference space. When the sound source detection device detects a sound generated by a sound source in the conference space, the sound source detection device outputs a positioning signal. The processor receives the positioning signal, and determines whether a real face image exists in a sub-image block of the conference image corresponding to the sound source according to the positioning signal to output the image signal. The display apparatus displays a close-up conference image including the real face image according to the image signal.

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. A lateral end of each of the first semiconductor layers has a V-shape cross section after the first semiconductor layers are laterally etched.