Patents by Inventor Yu-Cheng Hsu

Yu-Cheng Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230290748
    Abstract: A semiconductor package includes a first wafer comprising a first substrate, a first device structure, and a first bonding layer having a pattern of first bonding pads. The first bonding layer is disposed over the first substrate and the first device structure. The semiconductor package includes a second wafer comprising a second substrate, a second device structure, and a second bonding layer having a pattern of second bonding pads. The second bonding layer is disposed over the first bonding layer. The second device structure is disposed over the second bonding layer. The second substrate is disposed over the second device structure. The first bonding pads are each aligned with a corresponding one of the second bonding pads. The first device structure is electrically coupled to the second device structure, through at least one of the first bonding pads and at least one of the second bonding pads.
    Type: Application
    Filed: June 15, 2022
    Publication date: September 14, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry-Hak-Lay Chuang, Wei Cheng Wu, Wen-Tuo Huang, Yu-Ling Hsu, Pai Chi Chou, Ya-Chi Hung
  • Publication number: 20230290411
    Abstract: Various embodiments of the present application are directed towards an integrated memory chip with an enhanced device-region layout for reduced leakage current and an enlarged word-line etch process window (e.g., enhanced word-line etch resiliency). In some embodiments, the integrated memory chip comprises a substrate, a control gate, a word line, and an isolation structure. The substrate comprises a first source/drain region. The control gate and the word line are on the substrate. The word line is between and borders the first source/drain region and the control gate and is elongated along a length of the word line. The isolation structure extends into the substrate and has a first isolation-structure sidewall. The first isolation-structure sidewall extends laterally along the length of the word line and underlies the word line.
    Type: Application
    Filed: May 23, 2023
    Publication date: September 14, 2023
    Inventors: Shih Kuang Yang, Ping-Cheng Li, Hung-Ling Shih, Po-Wei Liu, Wen-Tuo Huang, Yu-Ling Hsu, Yong-Shiuan Tsair, Chia-Sheng Lin
  • Publication number: 20230268418
    Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. A lateral end of each of the first semiconductor layers has a V-shape cross section after the first semiconductor layers are laterally etched.
    Type: Application
    Filed: May 1, 2023
    Publication date: August 24, 2023
    Inventors: Kuo-Cheng CHIANG, Chen-Feng HSU, Chao-Ching CHENG, Tzu-Chiang CHEN, Tung Ying LEE, Wei-sheng YUN, Yu-Lin YANG
  • Publication number: 20230215998
    Abstract: A light-emitting device includes a semiconductor stack, first and second insulative layers, a reflective conductive structure, and first and second pads. The semiconductor stack includes a first semiconductor layer, and a mesa having an active region having a second semiconductor layer and formed on the first semiconductor layer. The first insulative layer is formed on the semiconductor stack and has first openings. The reflective conductive structure is formed on the first insulative layer and is electrically connected to the second semiconductor layer through the first openings. The second insulative layer is formed on the reflective conductive structure and includes second openings and a contact area covering portions overlapped with the first and second openings. A first pad is formed on the second insulative layer and electrically connected to the first semiconductor layer. A second pad formed on the second insulative layer and electrically connected to the second semiconductor layer.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 6, 2023
    Inventors: Chao-Hsing CHEN, Meng-Hsiang HONG, Chi-Shiang HSU, Yen-Liang KUO, Chien-Ya HUNG, Yong-Yang CHEN, Yu-Ling LIN, Xue-Cheng YAO
  • Publication number: 20230203415
    Abstract: A cell and tissue sheet forming package includes a container body, a membrane, a sliding door plate and a sealing film. The sliding door plate is disposed slidably on a top of the container body to cover or expose the membrane. The sliding door plate has a hole and a passive magnetic assembly. The cell injection equipment includes a carrier, an injection mechanism and a drive mechanism. The carrier carries the package, and the drive mechanism moves the carrier and the injection mechanism to have the injection mechanism to inject a solution, through the hole, into the package. A heating element of the carrier is introduced to heat the membrane and the solution to transform the solution into a colloid sheet on the membrane. Then, the positive magnetic assembly engages magnetically the passive magnetic assembly to slide the sliding door plate to expose the colloid sheet on the membrane.
    Type: Application
    Filed: December 23, 2021
    Publication date: June 29, 2023
    Inventors: HSIN-YI HSU, YANG-CHENG LIN, CHAO-HONG HSU, YU-BING LIOU, LI-HSIN LIN, HSIN-HSIN SHEN, YU-CHI WANG, CHANG-CHOU LI, CHIH-HUNG HUANG
  • Publication number: 20230204901
    Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a circuit assembly. The movable assembly is configured to connect an optical element, the movable assembly is movable relative to the fixed assembly, and the optical element has an optical axis. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The circuit assembly includes a plurality of circuits and is affixed to the fixed assembly.
    Type: Application
    Filed: February 23, 2023
    Publication date: June 29, 2023
    Inventors: Sin-Hong LIN, Yung-Ping YANG, Wen-Yen HUANG, Yu-Cheng LIN, Kun-Shih LIN, Chao-Chang HU, Yung-Hsien YEH, Mao-Kuo HSU, Chih-Wei WENG, Ching-Chieh HUANG, Chih-Shiang WU, Chun-Chia LIAO, Chia-Yu CHANG, Hung-Ping CHEN, Wei-Zhong LUO, Wen-Chang LIN, Shou-Jen LIU, Shao-Chung CHANG, Chen-Hsin HUANG, Meng-Ting LIN, Yen-Cheng CHEN, I-Mei HUANG, Yun-Fei WANG, Wei-Jhe SHEN
  • Publication number: 20230190065
    Abstract: A cleaning robot includes a main body and a cleaning module. The main body is configured to move on a floor along a travelling direction. The cleaning module includes a first shaft and some first roller sets. The first shaft is connected with the main body. The first shaft extends along a first axis perpendicular to the travelling direction. The first roller sets are separated from each other. Each first roller set includes a first bearing, a first tire and a first flexible structure. The first shaft penetrates through the first bearing. The first tire includes a first cleaning surface configured to abut against the floor. The first flexible structure includes a first inner surface and a first outer surface. The first inner surface abuts against the first bearing. The first outer surface abuts against the first tire. The first flexible structure has a first elasticity.
    Type: Application
    Filed: December 21, 2022
    Publication date: June 22, 2023
    Inventors: Kun-Chu Wang, Wen-Long Shu, Chung-Hang Sit, Chun-Kuan Wu, Yu-Chung Hsu, Yu-Cheng Wang, Yu-Cheng Ou, Jiun-Ying Yu, Bing-Hung Yang, Hung-Ta Chiu, Chun-Chang Hung, Shih-Jung Hsu
  • Publication number: 20230190066
    Abstract: A cleaning equipment includes a first take-up reel, a first supply reel, a frame, a first cleaning film, and a transmission assembly. The frame includes an inner space accommodating the first take-up reel and the first supply reel side by side and an outer surface having at least one gap communicating with the inner space. The first cleaning film has a supply part on the first supply reel, a take-up part on the first take-up reel, and a middle part at least partially covering the outer surface of the frame. Two ends of the middle part enter the inner space through the at least one gap and are connected to the supply part and the take-up part, respectively. The transmission assembly is coupled to the first supply reel and the first take-up reel and drives at least one of the first supply reel and the first take-up reel to rotate.
    Type: Application
    Filed: December 5, 2022
    Publication date: June 22, 2023
    Inventors: CHUNG HANG SIT, WEN LONG SHU, CHUN KUAN WU, YU-CHUNG HSU, KUN-CHU WANG, YU CHENG OU, JIUN-YING YU, BING HUNG YANG, HUNG-TA CHIU, YU-CHENG WANG
  • Publication number: 20230183533
    Abstract: An adhesive composition includes 0.1 to 1 part by weight of nano panicles, 50 to 95 parts by weight of acrylate resin, and 5 to 50 parts by weight of a monomer or oligomer of acrylate or acrylic acid containing multi-functional groups, and the acrylate resin and the monomer or oligomer of acrylate or acrylic acid containing multi-functional groups have a total weight of 100 parts by weight, in which the acrylate resin has a weight average molecular weight of 100,000 to 1,500,000. The nano particle has a shell covering parts of the surface of the core, and acrylate groups grafted to the surface of the core.
    Type: Application
    Filed: February 28, 2022
    Publication date: June 15, 2023
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Ming-Tzung WU, Te-Yi CHANG, Yao-Jheng HUANG, Yu-Chin LIN, Chen-Cheng YU, Yu-Ying HSU, Shuang-Huei CHEN
  • Publication number: 20230185324
    Abstract: Disclosed herein are related to an integrated circuit to regulate a supply voltage. In one aspect, the integrated circuit includes a metal rail including a first point, at which a first functional circuit is connected, and a second point, at which a second functional circuit is connected. In one aspect, the integrate circuit includes a voltage regulator coupled between the first point of the metal rail and the second point of the metal rail. In one aspect, the voltage regulator senses a voltage at the second point of the metal rail and adjusts a supply voltage at the first point of the metal rail, according to the sensed voltage at the second point of the metal rail.
    Type: Application
    Filed: February 6, 2023
    Publication date: June 15, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Haruki Mori, Hidehiro Fujiwara, Zhi-Hao Chang, Yangsyu Lin, Yu-Hao Hsu, Yen-Huei Chen, Hung-Jen Liao, Chiting Cheng
  • Patent number: 11677010
    Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. A lateral end of each of the first semiconductor layers has a V-shape cross section after the first semiconductor layers are laterally etched.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: June 13, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Chiang, Chen-Feng Hsu, Chao-Ching Cheng, Tzu-Chiang Chen, Tung Ying Lee, Wei-Sheng Yun, Yu-Lin Yang
  • Publication number: 20230176783
    Abstract: A memory control method, a memory storage device, and a memory control circuit unit are provided. The memory control method includes: receiving a read command from a host system; in response to a first physical erasing unit being a first type physical unit, sending a first operation command sequence to instruct a rewritable non-volatile memory module to read a first physical programming unit based on a first electronic configuration; and in response to the first physical erasing unit being a second type physical unit, sending a second operation command sequence to instruct the rewritable non-volatile memory module to read the first physical programming unit based on a second electronic configuration. The first electronic configuration is different from the second electronic configuration.
    Type: Application
    Filed: January 22, 2022
    Publication date: June 8, 2023
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Po-Cheng Su, Chih-Wei Wang, Yu-Cheng Hsu, Wei Lin
  • Patent number: 11665864
    Abstract: An immersion cooling system including a rack and at least one immersion cooling module is provided. The immersion cooling module includes a chassis and a condensation pipeline. The chassis is slidably disposed on the rack and is adapted to accommodate a coolant. At least one heat generating component is adapted to be disposed in the chassis to be immersed in the liquid coolant. The condensation pipeline is disposed in the chassis and is located above the liquid coolant. In addition, an electronic apparatus having the immersion cooling system is also provided.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: May 30, 2023
    Assignee: Wiwynn Corporation
    Inventors: Yu-Cheng Chu, Chin-Hao Hsu, Tsung-Han Li, Ting-Yu Pai
  • Patent number: 11657485
    Abstract: An electronic device used in a method for expanding image depth obtains first images by a first sensor, the first images comprising depth information. The electronic device obtains second images by a second sensor, the second images comprising gradient information, and the first images correspond to the second images. The electronic device determines the pixels in the first images which contain expandable content according to the gradient information of the second images, applies expansion accordingly to the pixels in the first images to generate third images, and generate target depth maps according to the gradient information of the second images and the depth information of the third images.
    Type: Grant
    Filed: April 9, 2021
    Date of Patent: May 23, 2023
    Assignee: Mobile Drive Netherlands B.V.
    Inventors: Yu-Kai Huang, Winston H. Hsu, Yueh-Cheng Liu, Tsung-Han Wu, Tzu-Kuei Huang, Chun-Hsiang Huang
  • Patent number: 11641394
    Abstract: An efficient cloning mechanism is provided for a distributed storage environment, where, for example, a private cloud computing environment and a public cloud computing environment are included in a hybrid cloud computing environment (on-premise object storage to off-premise computation resources), to improve computation workloads. The disclosed algorithm forms an efficient cloning mechanism in a hybrid storage environment where the read/write speed of data from the disk is not limited by its angular velocity.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: May 2, 2023
    Assignee: International Business Machines Corporation
    Inventors: Sasikanth Eda, Deepak R. Ghuge, Yu-Cheng Hsu, Sandeep R. Patil
  • Publication number: 20230123303
    Abstract: A computer-implemented method according to one aspect includes identifying environmental information for a hyper-converged infrastructure (HCI) system; and adjusting one or more resources allocated to one or more applications within the HCI system, based on the environmental information.
    Type: Application
    Filed: October 20, 2021
    Publication date: April 20, 2023
    Inventors: Sandeep Ramesh Patil, Shajeer K. Mohammed, Vinatha Chaturvedi, Yu-Cheng Hsu, Hugh Edward Hockett, Sridhar Muppidi
  • Publication number: 20230115045
    Abstract: A computer-implemented method, according to one approach, includes: monitoring actions of a user having access to a cluster, and in response to determining that the user has performed a risk event, incrementing a risk score assigned to the user. A determination is also made as to whether the incremented risk score is outside a predetermined range, and in response to determining that the incremented risk score is outside the predetermined range, a snapshot quota assigned to the user is dynamically reduced.
    Type: Application
    Filed: October 12, 2021
    Publication date: April 13, 2023
    Inventors: Yu-Cheng Hsu, Sridhar Muppidi, Sandeep Ramesh Patil, Sasikanth Eda, Deepak R. Ghuge
  • Publication number: 20230079199
    Abstract: A computer-implemented method, according to one embodiment, includes: determining, for each pair of HCI systems where each pair includes a first HCI system coupled to another HCI system, a federation relationship setting that corresponds to each pair. The federation relationship settings are used to control a flow of data, as well as to control a flow of workload scheduling, between the first HCI system and the other HCI systems in the respective pairs. Moreover, determining a federation relationship setting that corresponds to a pair includes: determining whether a risk score which corresponds to the pair is outside a predetermined range. In response to determining that the risk score is outside the predetermined range, a restrictive federation relationship setting is assigned to the pair, and in response to determining that the risk score is not outside the predetermined range, a permissive federation relationship setting is assigned to the pair.
    Type: Application
    Filed: September 14, 2021
    Publication date: March 16, 2023
    Inventors: Sandeep Ramesh Patil, Sridhar Muppidi, Yu-Cheng Hsu, Smita J. Raut, Shajeer K. Mohammed, Piyush Chaudhary
  • Patent number: 11604586
    Abstract: A data protection method, a memory storage device and a memory control circuit unit are provided. The method includes: setting a plurality of disk array tags corresponding to a plurality of word lines and a plurality of memory planes, and the plurality of disk array tags corresponding to one of the word lines connected to one of the memory planes are at least partially identical to the plurality of disk array tags corresponding to another one of the word lines connected to another one of the memory planes; receiving a write command and data corresponding to the write command from a host system; and sequentially writing the data into the plurality of word lines and the plurality of memory planes corresponding to the plurality of disk array tags.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: March 14, 2023
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Yu-Cheng Hsu, Hsiao-Yi Lin, Yu-Siang Yang
  • Publication number: 20230071724
    Abstract: A memory management method, a memory storage device, and a memory control circuit unit are provided. The method includes: detecting a first temperature status of a rewritable non-volatile memory module; performing a first write operation on a first physical unit under the first temperature status to store first data to the first physical unit; after performing the first write operation, detecting a second temperature status of the rewritable non-volatile memory module; in response to the first temperature status and the second temperature status meeting a first condition, performing a data refresh operation on the first physical unit under the second temperature status to re-store the first data to a second physical unit different from the first physical unit.
    Type: Application
    Filed: October 12, 2021
    Publication date: March 9, 2023
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Jia-Fan Chien, Wei Lin, Yu-Cheng Hsu, Yu-Siang Yang