Patents by Inventor Yu-Cheng Hsu

Yu-Cheng Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220411992
    Abstract: A manufacturing method for an antibacterial fiber includes the following steps. A dipping step is performed to soak a conductive fiber in a solution, in which the solution includes an ionic compound, and the ionic compound includes a metal cation. An oxidation step is performed by using the conductive fiber as an anode, such that an antibacterial material produced by the solution is adhered to a surface of the conductive fiber, in which the antibacterial material includes a metal oxide.
    Type: Application
    Filed: June 29, 2022
    Publication date: December 29, 2022
    Applicant: FORMOSA PLASTICS CORPORATRION
    Inventors: Chih-Hsiang LIANG, Yu-Cheng HSU, Tang-Chun KAO, Chien-Hsu CHOU, Yi-Chuan CHANG, Chih-Hsuan OU, Han-Chang WU, Long-Tyan HWANG
  • Publication number: 20220365706
    Abstract: A data accessing method, a memory controlling circuit unit, and a memory storage device are provided. The method includes: reading a codeword stored in a physical programming unit, and calculating a bit change ratio of a bit value change in dummy data included in the codeword; adjusting a read voltage level or a log likelihood ratio according to the bit change ratio; and performing a decoding operation on the codeword by using the adjusted read voltage level or the adjusted log likelihood ratio.
    Type: Application
    Filed: June 2, 2021
    Publication date: November 17, 2022
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Yu-Siang Yang, Wei Lin, Shih-Jia Zeng, An-Cheng Liu, Yu-Cheng Hsu
  • Publication number: 20220342547
    Abstract: A memory management method, a memory storage device, and a memory control circuit unit are provided. The method includes: reading first data from a first physical unit by using a first read voltage level according to first management information among multiple candidate management information; decoding the first data and recording first error bit information of the first data; and adjusting sorting information related to the candidate management information according to the first error bit information. The sorting information reflects a usage order of the candidate management information in a decoding operation.
    Type: Application
    Filed: June 17, 2021
    Publication date: October 27, 2022
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Yu-Siang Yang, Yu-Cheng Hsu, Tsai-Hao Kuo, Wei Lin, An-Cheng Liu
  • Publication number: 20210397347
    Abstract: A data protection method, a memory storage device and a memory control circuit unit are provided. The method includes: setting a plurality of disk array tags corresponding to a plurality of word lines and a plurality of memory planes, and the plurality of disk array tags corresponding to one of the word lines connected to one of the memory planes are at least partially identical to the plurality of disk array tags corresponding to another one of the word lines connected to another one of the memory planes; receiving a write command and data corresponding to the write command from a host system; and sequentially writing the data into the plurality of word lines and the plurality of memory planes corresponding to the plurality of disk array tags.
    Type: Application
    Filed: July 6, 2020
    Publication date: December 23, 2021
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Yu-Cheng Hsu, Hsiao-Yi Lin, Yu-Siang Yang
  • Patent number: 11101820
    Abstract: A memory control method for a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: sending a first read command sequence which indicates a reading of a first physical unit by using a first read voltage level to obtain first data; decoding the first data; sending a second read command sequence which indicates a reading of the first physical unit by using a second read voltage level to obtain second data; decoding the second data with assistance information to improve a decoding success rate of the second data if the second read voltage level meets a first condition or the second data meets a second condition; and decoding the second data without the assistance information if the second read voltage level does not meet the first condition and the second data does not meet the second condition.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: August 24, 2021
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Shih-Jia Zeng, Yu-Cheng Hsu, Yu-Siang Yang
  • Patent number: 10969906
    Abstract: The present disclosure provides a control method for a touch device. The control method of the touch device allows the plurality of pressure sensors to be activated to detect the pressure on the touch position of the touch panel while the capacitive touch sensor is probably invalid and the touch device is abnormal. Therefore, the touch device works continuously when the capacitive touch sensor is probably invalid.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: April 6, 2021
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Huang-Chih Chen, Yueh-Hsiang Chen, Kun-Chi Pan, Yu-Cheng Hsu, Chung-Han Lin
  • Patent number: 10936248
    Abstract: A data writing method, a memory controlling circuit unit and a memory storage device are provided. The method includes: receiving a plurality of data; writing the plurality of data into a first physical erasing unit by using a multi-page programming mode; and writing at least one first data of the plurality of data into a second physical erasing unit by using a single-page programming mode; verifying the plurality of data stored in the first physical erasing unit; and if the verification fails, performing a writing operation to a third physical erasing unit by using the multi-page programming mode according to the at least one first data and the plurality of data.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: March 2, 2021
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Yu-Cheng Hsu
  • Publication number: 20210048916
    Abstract: The present disclosure provides a control method for a touch device. The control method of the touch device allows the plurality of pressure sensors to be activated to detect the pressure on the touch position of the touch panel while the capacitive touch sensor is probably invalid and the touch device is abnormal. Therefore, the touch device works continuously when the capacitive touch sensor is probably invalid.
    Type: Application
    Filed: November 21, 2019
    Publication date: February 18, 2021
    Inventors: Huang-Chih Chen, Yueh-Hsiang Chen, Kun-Chi Pan, Yu-Cheng Hsu, Chung-Han Lin
  • Patent number: 10923212
    Abstract: A memory control method for a rewritable non-volatile memory module including a plurality of physical units is provided according to an exemplary embodiment of the disclosure. The method includes: reading first data from a first physical unit of a rewritable non-volatile memory module; decoding the first data by a decoding circuit; updating reliability information according to the decoded first data; reading second data from a second physical unit of the rewritable non-volatile memory module; and decoding the second data by the decoding circuit according to the updated reliability information.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: February 16, 2021
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, An-Cheng Liu, Yu-Cheng Hsu, Yu-Siang Yang
  • Patent number: 10872667
    Abstract: A decoding method, a memory controlling circuit unit, and a memory storage device are provided. The method includes: reading a first physical programming unit by using a first read voltage to obtain first data; determining whether a first ratio of a first quantity of a first bit value and a second quantity of a second bit value in the first data is greater than a threshold; when the first ratio is not greater than the threshold, performing a decoding operation according to the first data to generate first decoded data and outputting the first decoded data; and when the first ratio is greater than the threshold, not performing the decoding operation according to the first data.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: December 22, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Yu-Cheng Hsu, Szu-Wei Chen
  • Publication number: 20200379654
    Abstract: A memory control method, a memory storage device and a memory control circuit unit are provided. The method includes: reading a first physical unit among a plurality of physical units based on a first electrical configuration to obtain first soft information; reading the first physical unit based on a second electrical configuration which is different from the first electrical configuration to obtain second soft information; classifying a plurality of memory cells in the first physical unit according to the first soft information and the second soft information; and decoding data read from the first physical unit according to a classification result of the memory cells.
    Type: Application
    Filed: August 2, 2019
    Publication date: December 3, 2020
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Yu-Cheng Hsu, Hsiao-Yi Lin, Yu-Siang Yang
  • Publication number: 20200379676
    Abstract: A data writing method, a memory controlling circuit unit and a memory storage device are provided. The method includes: receiving a plurality of data; writing the plurality of data into a first physical erasing unit by using a multi-page programming mode; and writing at least one first data of the plurality of data into a second physical erasing unit by using a single-page programming mode; verifying the plurality of data stored in the first physical erasing unit; and if the verification fails, performing a writing operation to a third physical erasing unit by using the multi-page programming mode according to the at least one first data and the plurality of data.
    Type: Application
    Filed: June 26, 2019
    Publication date: December 3, 2020
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Yu-Cheng Hsu
  • Patent number: 10776053
    Abstract: A memory control method for a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: reading first data from a first memory cell of the rewritable non-volatile memory module by a first read voltage level; decoding the first data by a decoding circuit; reading second data from the first memory cell by a second read voltage level; obtaining reliability information according to a first data status of the first data and a second data status of the second data, and the first data status and the second data status reflect that a first bit value of the first data is different from a second bit value of the second data; and decoding the second data by the decoding circuit according to the reliability information.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: September 15, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Yu-Cheng Hsu, Szu-Wei Chen, Yu-Siang Yang
  • Publication number: 20200185032
    Abstract: A decoding method, a memory controlling circuit unit, and a memory storage device are provided. The method includes: reading a first physical programming unit by using a first read voltage to obtain first data; determining whether a first ratio of a first quantity of a first bit value and a second quantity of a second bit value in the first data is greater than a threshold; when the first ratio is not greater than the threshold, performing a decoding operation according to the first data to generate first decoded data and outputting the first decoded data; and when the first ratio is greater than the threshold, not performing the decoding operation according to the first data.
    Type: Application
    Filed: January 16, 2019
    Publication date: June 11, 2020
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Yu-Cheng Hsu, Szu-Wei Chen
  • Publication number: 20200183623
    Abstract: A memory control method for a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: reading first data from a first memory cell of the rewritable non-volatile memory module by a first read voltage level; decoding the first data by a decoding circuit; reading second data from the first memory cell by a second read voltage level; obtaining reliability information according to a first data status of the first data and a second data status of the second data, and the first data status and the second data status reflect that a first bit value of the first data is different from a second bit value of the second data; and decoding the second data by the decoding circuit according to the reliability information.
    Type: Application
    Filed: January 28, 2019
    Publication date: June 11, 2020
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Yu-Cheng Hsu, Szu-Wei Chen, Yu-Siang Yang
  • Patent number: 10679707
    Abstract: A voltage adjusting method, a memory controlling circuit unit and a memory storage device are provided. The method includes: reading a first physical programming unit in a first physical programming unit group to obtain first data; correcting the first data according to a first error check and correction code corresponding to the first data to obtain first corrected data; reading a second physical programming unit in the first physical programming unit group to obtain second data; and adjusting a first read voltage for reading a first memory cell to a second read voltage according to the first data, the first corrected data, and the second data.
    Type: Grant
    Filed: September 3, 2018
    Date of Patent: June 9, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Yu-Cheng Hsu, Tsai-Hao Kuo, Szu-Wei Chen, Lih Yuarn Ou, Hsiao-Yi Lin
  • Publication number: 20200168289
    Abstract: A memory control method for a rewritable non-volatile memory module including a plurality of physical units is provided according to an exemplary embodiment of the disclosure. The method includes: reading first data from a first physical unit of a rewritable non-volatile memory module; decoding the first data by a decoding circuit; updating reliability information according to the decoded first data; reading second data from a second physical unit of the rewritable non-volatile memory module; and decoding the second data by the decoding circuit according to the updated reliability information.
    Type: Application
    Filed: January 18, 2019
    Publication date: May 28, 2020
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, An-Cheng Liu, Yu-Cheng Hsu, Yu-Siang Yang
  • Patent number: 10628229
    Abstract: The present disclosure provides a system and method for automatically composing resources in a data center using a management application. The management application can communicate with a data center management software to collect information of computer resource, storage resource, and network resource of the data center. Based at least upon the network resource information of the data center, the management application can generate a network topology of the data center. In response to receiving a request from a specific user, the management application can compose suitable resources of the data center to match the request.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: April 21, 2020
    Assignee: QUANTA COMPUTER INC.
    Inventors: Kun-Hu Tsai, Ching-Chih Shih, Yu-Cheng Hsu
  • Patent number: 10628259
    Abstract: A bit determining method, a memory control circuit unit and a memory storage device are provided. The method includes: reading a first storage state of a first memory cell to obtain a first value of a first significant bit; reading the first storage state of the first memory cell to obtain at least one second value of at least one second significant bit; performing a first decoding operation according to the at least one second value to obtain at least one third value of the decoded second significant bit; determining whether the first significant bit is a special bit according to the first storage state and a second storage state corresponding to the at least one third value; and if the first significant bit is the special bit, performing a corresponding decoding operation.
    Type: Grant
    Filed: September 3, 2018
    Date of Patent: April 21, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, An-Cheng Liu, Yu-Siang Yang, Yu-Cheng Hsu
  • Patent number: 10622077
    Abstract: A decoding method for a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The decoding method includes: reading first data from memory cells of the rewritable non-volatile memory module, wherein the first data includes a first bit stored in a first memory cell; obtaining a storage state of at least one second memory cell which is different from the first memory cell; obtaining first reliability information corresponding to the first bit according to the storage state of the second memory cell, wherein the first reliability information is different from default reliability information corresponding to the first bit; and decoding the first data according to the first reliability information. Therefore, a decoding efficiency can be improved.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: April 14, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Yu-Cheng Hsu, Szu-Wei Chen, Tien-Ching Wang