Abstract: Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes a first pixel region and a second pixel region within a substrate. A first recess region is disposed along a back-side of the substrate within the first pixel region. The back-side of the substrate within the first pixel region is asymmetric about a center of the first pixel region in a cross-sectional view. A second recess region is disposed along the back-side of the substrate and within the second pixel region. The back-side of the substrate within the second pixel region is asymmetric about a center of the second pixel region in the cross-sectional view. The first recess region and the second recess region are substantially symmetric about a vertical line laterally between the first pixel region and the second pixel region.

Abstract: A decoration panel includes a first substrate, a first transparent conductive element, a transparent structure, a second substrate, a second transparent conductive element, and a first cholesteric liquid crystal layer. The first transparent conductive element is disposed on the first substrate. The transparent structure is disposed on the first substrate. The second substrate is disposed opposite to the first substrate. The second transparent conductive element is disposed on the second substrate. The first cholesteric liquid crystal layer is disposed between the first transparent conductive element and the second transparent conductive element. A display apparatus is adapted to render a decoration pattern, and the decoration pattern corresponds to the transparent structure. Moreover, a display apparatus including the decoration panel is also provided.

Abstract: A semiconductor device includes a gate structure disposed in a first dielectric layer, a conductive segment disposed in the first dielectric layer and separated from the gate structure, a second dielectric layer disposed over the first dielectric layer, a first contact penetrating the second dielectric layer and electrically connected to the gate structure, a second contact penetrating the second dielectric layer and electrically connected to the conductive segment, and a silicon nitride-based layer surrounding at least one of the first and second contacts and connected between the second dielectric layer and the at least one of the first and second contacts. A method for making the semiconductor device is also provided.

Abstract: A method of fabricating an integrated circuit includes placing a first set of conductive feature patterns on a first level, placing a second set of conductive feature patterns on a second level, placing a first set of via patterns between the second set of conductive feature patterns and the first set of conductive feature patterns, placing a third set of conductive feature patterns on a third level different from the first level and the second level, placing a second set of via patterns between the third set of conductive feature patterns and the second set of conductive feature patterns, and manufacturing the integrated circuit based on at least one of the above patterns of the integrated circuit.

Abstract: A sensor package structure includes a substrate, a sensor chip and a ring-shaped solder mask frame those are disposed on the substrate, a ring-shaped support disposed on a top side of the annular solder mask frame, and a light permeable member that is disposed on the ring-shaped support. The sensor chip is electrically coupled to the substrate. A top surface of the sensor chip has a sensing region, and the sensing region is spaced apart from an outer lateral side of the sensor chip by a distance less than 300 ?m. The ring-shaped solder mask frame surrounds and contacts the outer lateral side of the sensor chip. The light permeable member, the ring-shaped support, and the sensor chip jointly define an enclosed space.

Abstract: A container for containing food or liquid is provided. The container includes a body portion, a lid and an attachment. The lid is detachably disposed on the body portion. The attachment is configured to be disposed on the lid or the body portion and includes a magnetic attraction member and a connecting structure. The magnetic attraction member is adapted to be magnetically connected to a mobile electronic device. The connecting structure is disposed between the magnetic attraction member and the container for selectively fixing the magnetic attraction member at a first position or a second position. The connecting structure includes a fastening member, and the fastening member is adapted to be detachably fastened to the body portion or the lid.

Abstract: A container for containing food or liquid is provided. The container includes a body portion, a lid and an attachment. The lid is detachably disposed on the body portion. The attachment includes a magnetic attraction member and a connecting structure. The magnetic attraction member is independent from the lid and adapted to be magnetically connected to a mobile electronic device. The connecting structure is disposed between the magnetic attraction member and the container for selectively fixing the magnetic attraction member at a first position or a second position. At least a portion of the connecting structure is fixed to the container.

Abstract: A method of forming a semiconductor device according to the present disclosure includes forming a metal-insulator-metal (MIM) structure in a substrate and forming an interconnect structure over the substrate. The MIM structure includes first electrodes of a first polarity and second electrodes of a second polarity. The interconnect structure includes conductive paths electrically connecting to the first and second electrodes. The conductive paths are isolated from each other inside the interconnect structure. The method also includes forming first and second contact pads over the interconnect structure. The first contact pad electrically connects a first portion of the conductive paths corresponding to the first electrodes. The second contact pad electrically connects a second portion of the conductive paths corresponding to the second electrodes.

Abstract: A semiconductor device includes a substrate, an interconnect structure, and conductive vias. The substrate has a first side, a second side and a sidewall connecting the first side and the second side, wherein the sidewall includes a first planar sidewall of a first portion of the substrate, a second planar sidewall of a second portion of the substrate and a curved sidewall of a third portion of the substrate, where the first planar sidewall is connected to the second planar sidewall through the curved sidewall. The interconnect structure is located on the first side of the substrate, where a sidewall of the interconnect structure is offset from the second planar sidewall. The conductive vias are located on the interconnect structure, where the interconnect structure is located between the conductive vias and the substrate.

Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a first movable assembly and a first driving assembly. The first movable assembly is configured to connect a first optical element, and the first movable assembly is movable relative to the fixed assembly. The first driving assembly is configured to drive the first movable assembly to move relative to the fixed assembly in a first dimension.

Abstract: An antenna for multi-broadband and multi-polarization communication, may include a plurality of radiators configured to jointly function as one or more dipoles, a first feed terminal for a first signal of a first polarization, and a second feed terminal for a second signal of a second polarization different from the first polarization. Each radiator may be configured to contribute to resonances at two or more nonoverlapping bands. In an embodiment, the antenna may further include a third feed terminal for a third signal of the first polarization, and a fourth feed terminal for a fourth signal of the second polarization.

Abstract: A display device including a substrate, a cholesteric liquid crystal layer, and a transparent electrode layer that are sequentially stacked is provided. The cholesteric liquid crystal layer includes cholesteric liquid crystal molecules and a plurality of transparent photoresist structures. Each of the transparent photoresist structures is a closed structure, and the cholesteric liquid crystal molecules are respectively accommodated in a plurality of patterned areas respectively surrounded by the transparent photoresist structures, so as to form a plurality of cholesteric liquid crystal patterns. The transparent electrode layer includes a plurality of sub-electrodes. The cholesteric liquid crystal patterns are respectively driven by the sub-electrodes. An orthogonal projection of each of the transparent photoresist structures on the substrate falls in an orthogonal projection of a corresponding sub-electrode of the sub-electrodes on the substrate.

Abstract: A sensor package structure includes a substrate, a sensor chip and a ring-shaped solder mask frame those are disposed on the substrate, a ring-shaped support disposed on a top side of the annular solder mask frame, and a light permeable member that is disposed on the ring-shaped support. The sensor chip is electrically coupled to the substrate. A top surface of the sensor chip has a sensing region, and the sensing region is spaced apart from an outer lateral side of the sensor chip by a distance less than 300 ?m. The ring-shaped solder mask frame surrounds and contacts the outer lateral side of the sensor chip. The light permeable member, the ring-shaped support, and the sensor chip jointly define an enclosed space.

Abstract: An electronic circuit includes a first transistor coupled between a first node and a supply voltage and controlled by a first node, a second transistor coupled between a second node and the supply voltage and controlled by the first node, a third transistor coupled between a third node and the supply voltage and controlled by a fourth node, a fourth transistor coupled between the fourth node and the supply voltage and controlled by the fourth node, a fifth transistor coupled between the first node and the fifth node and controlled by a reference voltage, a sixth transistor coupled between the second node and a ground and controlled by the third node, a seventh transistor coupled between the fourth node and the ground and controlled by the second node, a first resistor coupled the fourth node to the ground, and a second resistor coupled to the fifth node.

Abstract: A semiconductor die including mechanical-stress-resistant bump structures is provided. The semiconductor die includes dielectric material layers embedding metal interconnect structures, a connection pad-and-via structure, and a bump structure including a bump via portion and a bonding bump portion. The entirety of a bottom surface of the bump via portion is located within an area of a horizontal top surface of a pad portion of the connection pad-and-via structure.

Abstract: The present invention relates to a reaction platform, which comprises: a machine body with a bottom plate for placing non-porous substrates; and a coater module configured on the top of the machine body and capable of maintaining a preset of a predetermined height for moving along the surface of non-porous substrate, wherein the coater module has one or more slits, and a target liquid can be directly injected or sucking in from the outside of the coater module through the slit, and spreading the target liquid onto a surface of the non-porous substrate while moving along the non-porous substrate; wherein the surface of the non-porous substrate has a target to be coated. The reaction platform of the present invention can not only save time, labor and cost, but also have accurate and reproducible experimental results, showing better results than traditional methods.

Abstract: A semiconductor device includes a first semiconductor structure, a second semiconductor structure, a first isolation block and a second isolation block. The first semiconductor structure includes a first gate structure wrapping around a first sheet structures and a second sheet structures, and a first dielectric wall disposed between and separating the first and second sheet structures. The second semiconductor structure includes a second gate structure wrapping around third sheet structures. The first isolation block is disposed on the first dielectric wall of the first semiconductor structure and separates the first gate structure into a first gate portion wrapping around the first sheet structures and a second gate portion wrapping around the second sheet structures. The second isolation block is disposed between the first and second semiconductor structures and separates the first gate structure from the second gate structure.

Abstract: A structure and method for improving manufacturing yield of passive device dies are disclosed. The structure includes first and second groups of capacitors disposed on a substrate, an interconnect structure disposed on the first and second groups of capacitors, first and second bonding structures disposed on the first and second conductive lines, respectively, and first and second measurement structures connected to the first and second conductive lines, respectively, and configured to measure electrical properties of the first and second groups of capacitors, respectively. The interconnect structure includes first and second conductive line connected to the first and second groups of trench capacitors, respectively. The first bonding structure is electrically connected to the first group of capacitors and the second bonding structure is electrically isolated from the first and second groups of capacitors. The first and second measurement structures are electrically isolated from each other.

Abstract: A communication receiver includes a first signal processing circuit and a second signal processing circuit. The first signal processing circuit includes a first feedforward equalizer and a decision circuit. The first feedforward equalizer processes a received signal to generate a first equalized signal. The decision circuit performs hard decision upon the first equalized signal to generate a first symbol decision signal. The second signal processing circuit includes a second feedforward equalizer, a decision feedforward equalizer, and a first decision feedback equalizer. The second feedforward equalizer processes the first equalized signal to generate a second equalized signal. The decision feedforward equalizer processes the first symbol decision signal to generate a third equalized signal. The first decision feedback equalizer generates a second symbol decision signal according to the second equalized signal and the third equalized signal.

Abstract: A method includes designing a plurality of cells for a semiconductor device, wherein designing the plurality of cells comprises reserving a routing track of a plurality of routing tracks within each of the plurality of cells, wherein each of the plurality of cells comprises signal lines, and the reserved routing track is free of the signal lines. The method includes placing a first cell and a second cell of the plurality of cells in a layout of the semiconductor device. The method includes determining whether any power rails overlap with any of the plurality of routing tracks other than the reserved routing track in the second cell. The method includes adjusting a distance between the first cell and the second cell in response to a determination that at least one power rail overlaps with at least one routing track other than the reserved routing track.