Abstract: An edge-emitting semiconductor laser with high thermal conductivity and low reflection front mirror surface, comprising: an edge-emitting semiconductor laser die having a rear mirror surface and a front mirror surface on the lateral side, and the electromagnetic radiation generated by the edge-emitting semiconductor laser die is in the wavelength range of 635 nm to 1550 nm; a rear mirror surface coating; and a front mirror surface e, and a passivation layer, an affinity layer, a high thermal conductivity layer and a protective layer. Whereby, providing an edge-emitting semiconductor laser with high thermal conductivity and low reflection front mirror surface, and the front mirror surface coating is made of high thermal conductivity insulating materials to form a multi-layer coating structure, so that the front mirror surface coating has the effect of high thermal conductivity and low reflection.

Abstract: Various examples of a circuit device that includes gate stacks and gate seals are disclosed herein. In an example, a substrate is received that has a fin extending from the substrate. A placeholder gate is formed on the fin, and first and second gate seals are formed on sides of the placeholder gate. The placeholder gate is selectively removed to form a recess between side surfaces of the first gate seal and the second gate seal. A functional gate is formed within the recess and between the side surfaces of the first gate seal and the second gate seal.

Abstract: The present disclosure describes a structure with a conductive plate and a method for forming the structure. The structure includes a gate structure disposed on a diffusion region of a substrate, a protective layer in contact with the diffusion region and covering a sidewall of the gate structure and a portion of a top surface of the gate structure, and a first insulating layer in contact with the gate structure and the protective layer. The structure further includes a conductive plate in contact with the first insulating layer, where a first portion of the conductive plate laterally extends over a horizontal portion of the protective layer, and where a second portion of the conductive plate extends over a sidewall portion of the protective layer covering the sidewall of the gate structure. The structure further includes a second insulating layer in contact with the conductive plate.

Abstract: A liquid cooling system includes a liquid coolant conduit in proximity to heat-generating electrical components within an enclosed space. The conduit allows circulation of a liquid coolant to extract heat from the heat-generating components. The heat-generating components includes at least one first heat-generating electrical component and at least one second heat-generating electrical component. The first heat-generating component produces greater heat than the second heat-generating component. The enclosed space includes an inlet and an outlet. The conduit includes a nozzle fluidly connected to the inlet. The nozzle is located within the enclosed space. The nozzle forms first and second aperture sets. The first aperture set directs the liquid coolant to the first heat-generating component. The second aperture set directs the liquid coolant to the second heat-generating component.

Abstract: A sequence detection device includes a decision-feedback equalizer (DFE), a combining circuit, a decision circuit, and a sequence detection circuit. The DFE processes a symbol decision signal to generate a first equalized signal. The combining circuit combines a data signal and the first equalized signal to generate a sample signal. The decision circuit performs hard decision upon the sample signal to generate the symbol decision signal. The sequence detection circuit performs sequence detection upon the data signal to generate and output a symbol sequence. Regarding the sequence detection, the sequence detection circuit selects branches for branch metric calculation according to at least the symbol decision signal.

Abstract: Example implementations relate to power supplied to ports based on charge amounts. In some examples, a computing device can include a charge storage device, an I/O port, and a processor, where the processor is to determine a charge amount of the charge storage device and an operating mode of the computing device, and determine an amount of power to be supplied to the I/O port based on the charge amount and the operating mode.

Abstract: An error detection and correction device includes a decision-feedback equalizer (DFE), a decision circuit, an error detection circuit, and an error correction circuit. The DFE equalizes a data signal to generate a first equalized signal. The decision circuit performs hard decision upon the first equalized signal to generate a symbol decision signal. The error detection circuit performs forward error detection at symbol positions of consecutive symbols included in the symbol decision signal to detect a head position of suspicious error that affects at least one symbol in the symbol decision signal. The error correction circuit performs error correction upon the symbol decision signal in response to the head position of the suspicious error that is detected by the error detection circuit.

Abstract: The disclosure provides a fuse device and an operation method thereof. The fuse device includes a plurality of fuse circuits, a global latch circuit and a plurality of local latch circuits. The global latch circuit is coupled to the fuse circuits. The global latch circuit is used to sense the blown states of the fuse circuits at different times, so as to output the fuse information of the fuse circuits at the different times. The local latch circuits are coupled to the global latch circuits. Each of these local latch circuits latches the fuse information output by the global latch circuit at the different times.

Abstract: A computing device for handling anomaly detection, comprises an encoder, for receiving an input image, to generate a first latent vector comprising a semantic latent vector and a visual appearance latent vector according to the input image and at least one first parameter of the encoder; and a training module, coupled to the encoder, for receiving the input image and the first latent vector, to update the at least one first parameter according to the input image and the first latent vector and a loss function.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a first gate structure over a substrate, and the first gate structure includes a first metal electrode. The method includes forming a second gate structure adjacent to the first gate structure, and the second gate structure includes a second metal electrode. The method also includes forming a mask structure covering the first gate structure and exposing the second gate structure, and etching a portion of the second metal electrode of the second gate structure to form an extending conductive portion. The method includes forming a metal layer over the first gate structure and the extending conductive portion, and etching the metal layer, such that no metal layer is remaining over the first gate structure, and a remaining portion of the metal layer is over the extending conductive portion.

Abstract: An immersion liquid cooling tank assembly includes a tank, a condenser, at least one cross-flow fan, an internal wall system, a top cover, and at least one sloping wall. The tank includes a base and at least one sidewall. The base is connected to the sidewall. The condenser is located within the tank. The condenser is adapted to transform vapor into liquid. The cross-flow fan is near the condenser. The cross-flow fan produces an airflow. The internal wall system is located adjacent to the cross-flow fan to assist in directing the airflow from the cross-flow fan. The top cover is located generally opposite to the base. The sloping wall is located between the top cover and the sidewall. The sloping wall provides a closed airflow loop for the airflow produced by the cross-flow fan.

Abstract: The present disclosure describes a semiconductor device with a diffusion barrier layer on source/drain (S/D) contact structures and a method of fabricating the semiconductor device. The method of fabricating the semiconductor device includes forming a S/D region on a fin structure, forming a S/D contact structure including a metal on the S/D region, forming a barrier layer including silicon and the metal on the S/D contact structure, and forming a via contact structure on the barrier layer. The barrier layer blocks a diffusion of the metal in the S/D contact structure to the via contact structure.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure. The method includes providing a substrate; forming a fin structure on the substrate; forming a first dummy gate on the fin structure; forming a trench to penetrate the first dummy gate and the fin structure; forming a dielectric stack in the trench; removing a top portion of the dielectric stack in the trench to leave a lower portion of the dielectric stack in the trench; and forming a protective layer in the trench and directly on the lower portion of the dielectric stack.

Abstract: A method of manufacturing a through silicon via (TSV) is provided in the present invention, including steps of forming a TSV sacrificial structure in a substrate, wherein the TSV sacrificial structure contacts a metal interconnect on the front side of the substrate, performing a backside thinning process to expose the TSV sacrificial structure from the back side of the substrate, removing the TSV sacrificial structure to form a through silicon hole, and filling the through silicon hole with conductive material to form a TSV.

Abstract: A method includes forming an n-type Fin-Field Effect Transistor (FinFET) and a p-type FinFET. The forming of the n-type FinFFT includes: forming a first auxiliary gate stack over a first semiconductor fin; forming an n-type source/drain region on the first semiconductor fin adjacent to the first auxiliary gate stack; and performing a first etch to form a first recess with a first depth on a first top surface of the n-type source/drain region. The forming of the p-type FinFFT includes: forming a second auxiliary gate stack over a second semiconductor fin; forming a p-type source/drain region on the second semiconductor fin adjacent to the second auxiliary gate stack; and performing a second etch to form a second recess with a second depth on a second top surface of the p-type source/drain region. The first depth is greater than the second depth.

Abstract: A semiconductor structure includes: a plurality of calibration reference features disposed on a substrate and spaced apart from each other in a first direction; and a plurality of columns of first active features and a plurality of columns of second active features respectively disposed on opposite sides of the calibration reference features, wherein each of the columns of first active features is spaced apart from each other in a second direction, each of the columns of second active features is spaced apart from each other in the second direction, and the calibration reference features, the first active features, and the second active features are disposed on the same layer and are a portion of the substrate.

Abstract: Examples of an integrated circuit with a capacitor structure and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate and a trench isolation material disposed on the substrate. An isolation structure is disposed on the trench isolation material. A first electrode disposed on the isolation structure, and a second electrode disposed on the isolation structure. A capacitor dielectric is disposed on the isolation structure between the first electrode and the second electrode. In some such examples, the isolation structure includes a first hard mask disposed on the trench isolation material, a dielectric disposed on the first hard mask, and a second hard mask disposed on the dielectric.

Abstract: A sensor package structure includes a substrate, a sensor chip and a ring-shaped solder mask frame those are disposed on the substrate, a ring-shaped support disposed on a top side of the annular solder mask frame, and a light permeable member that is disposed on the ring-shaped support. The sensor chip is electrically coupled to the substrate. A top surface of the sensor chip has a sensing region, and the sensing region is spaced apart from an outer lateral side of the sensor chip by a distance less than 300 um. The ring-shaped solder mask frame surrounds and contacts the outer lateral side of the sensor chip. The light permeable member, the ring-shaped support, and the sensor chip jointly define an enclosed space.

Abstract: A sensor package structure includes a substrate, a sensor chip and a ring-shaped solder mask frame those are disposed on the substrate, a ring-shaped support disposed on a top side of the annular solder mask frame, and a light permeable member that is disposed on the ring-shaped support. The sensor chip is electrically coupled to the substrate. A top surface of the sensor chip has a sensing region, and the sensing region is spaced apart from an outer lateral side of the sensor chip by a distance less than 300 µm. The ring-shaped solder mask frame surrounds and contacts the outer lateral side of the sensor chip. The light permeable member, the ring-shaped support, and the sensor chip jointly define an enclosed space.

Abstract: A sensor package structure includes a substrate, a sensor chip and a ring-shaped solder mask frame those are disposed on the substrate, a ring-shaped support disposed on a top side of the annular solder mask frame, and a light permeable member that is disposed on the ring-shaped support. The sensor chip is electrically coupled to the substrate. A top surface of the sensor chip has a sensing region, and the sensing region is spaced apart from an outer lateral side of the sensor chip by a distance less than 300 ?m. The ring-shaped solder mask frame surrounds and contacts the outer lateral side of the sensor chip. The light permeable member, the ring-shaped support, and the sensor chip jointly define an enclosed space.